Discussion Session 9. CS/ECE 552 Ramkumar Ravi 26 Mar 2012

Transcription

1 Discussion Session 9 CS/ECE 55 Ramkumar Ravi 6 Mar CS/ECE 55, Spring

2 Mark your calendar IMPORTANT DATES TODAY 4/ Spring break 4/ HW5 due 4/ Project Demo HW5 discussion Error in mem_system_randbench.v (will be corrected and uploaded in course webpage) Other test-bench modules look OK Modification to problem 5 Discussion of a sample state-machine and show sample code (if time permits)

3 Problems and 4 Cache Parameters SIZE = total amount of cache data storage, in bytes BLOCKSIZE = total number of bytes in a single ASSOC = associativity, i.e., # of lines in a set Equation for # of cache lines in cache = size / size Equation for # of sets in cache = size / (size * associativity) You may need this for few of the problems in this HW

4 Address Fields Tag field is compared to the (s) of the ed cache line(s). If it matches, is there (hit). If it doesn t match, is not there (miss). Used to look up a set, whose lines contain one or more memory s. (The # of lines per set is the associativity.) Once a is found, the selects a particular byte or word of data in the.

5 Address Fields (cont.) Widths of address fields (# bits) # bits = log (# sets) # bits = log ( size) # bits = # bits # bits Assuming -bit addresses

6 Example of cache operation Example: Processor accesses a 56-byte direct-mapped cache, which has -byte lines, with the following sequence of addresses. Show contents of the cache after each access. Count # of hits and # of replacements. # bits = log (# sets) = log (8) = # bits = log ( size) = log ( bytes) = 5 # bits = total # address bits # bits # bits = bits bits 5 bits = 4 Thus, the top 6 nibbles (4 bits) of address form the and lower nibbles (8 bits) of address form the and fields.

7 Example address sequence Address (hex) Tag (hex) Index & bits (binary) xff4e xbeef5c xff4e xff4e8 x78 x8e x64 x55c x544 Index (decimal) Comment

8 Analysis of results follows next Address (hex) Tag (hex) Index & bits (binary) Index (decimal) Comment xff4e xff4 7 Miss xbeef5c xbeef Miss xff4e xff4 7 Hit xff4e8 xff4 7 Hit x78 x Miss x8e x8 7 Miss+Replace x64 x Hit x55c x5 Miss+Replace x544 x5 Hit

9 FF4 7 Data FF4 FF4 BEEF FF4 FF Get from memory (slow)

10 BEEF Data BEEF FF4 FF4 BEEF FF4 FF Get from memory (slow)

11 FF4 7 Data BEEF FF4 FF4 BEEF FF4 FF

12 FF4 7 Data BEEF FF4 FF4 BEEF FF4 FF

13 Data BEEF FF4 FF4 BEEF FF4 FF Get from memory (slow)

14 Data BEEF 8 FF4 FF4 BEEF FF4 FF Get from Memory (slow)

15 BEEF 8 Data FF4 BEEF FF4 FF

16 BEEF 8 Data FF4 BEEF FF4 FF Get from memory (slow)

17 Data 5 8 FF4 BEEF FF4 FF

18 Set-Associative Example Example: Processor accesses a 56-byte -way set-associative cache, which has line size of bytes, with the following sequence of addresses. Show contents of cache after each access. Count # of hits and # of replacements. # bits = log (# sets) = log (4) = # bits = log ( size) = log ( bytes) = 5 # bits = total # address bits # bits # bits = bits bits 5 bits = 5

19 Address (hex) Tag (hex) Index & bits (binary) Index (decimal) Comment xff4e xfe8 Miss xbeef5c x7dde Miss x78 x Miss xff4e xfe8 Hit x78 x Hit x8e x47 Miss/Replace x64 x Hit

20 FE8 5 FE8 Data not shown for convenience

21 DDE 7DDE 5 FE8 Data not shown for convenience

22 DDE 5 FE8 Data not shown for convenience

23 FE8 7DDE 5 FE8 Data not shown for convenience

24 DDE 5 FE8 Data not shown for convenience

25 DDE 47 5 FE8 Data not shown for convenience

26 DDE 5 47 Data not shown for convenience

27 PROBLEM 5 Total cache storage (capacity) (64-byte s) * (5 sets) * (# of ways) Total number of bits Tag size = 4 bits - # bits - # bits Block size = valid + dirty + LRU + + data

28 PROBLEMS and Sample FSM presentation Understanding the requirements of the problem