Interrupts. 1.Maskable interrupt request can be ignored or delayed by the microprocessor and used in telephone

Transcription

1 Interrupts The interrupt I/O is a process of data transfer where-by an external device or a peripheral can inform the microprocessor that it is ready for communication The interrupt requests are classified in two categories:.maskable interrupt request can be ignored or delayed by the microprocessor and used in telephone 2.Non - Mask able interrupt request the microprocessor respond immediately and used in smoke detector. The interrupt process can be described by the following steps:.the interrupt should be enabled by writing the instruction EI in main program. 2.When The microprocessor is executing a program, it check the INTR during executing of each instruction. 3.If the line INTR is high, the microprocessor send INTA (acknowledge). 4.The Microprocessor can not accept any other interrupt request. The 885 Interrupts The 885 has five interrupt inputs )Fig.2.) one is called INTR. Which is Identical with INT input in the 88A.The other four are automatically vectored (transferred) to specific location on memory page H without any external hardware.they do not require the INTA signal or an input port ;the necessary hardware is already implemented inside the 885.These interrupts and their call locations are as follows:

2 Priority Input Pin Mask Vector 2 RST D CLR Q Q Locations 3C 6 Reset RST Interrupt Recognized r RST RST C TRAP D Reset Any Interrupt Recognized E S R Interrupt Enable Q e 6 5 INTR Enable Get RST Code from External Hardware Figure (2.) The 885 Interrupts and Vector Locations. Interrupts Call Locations. TRAP 24H 2. RST 3CH 3. RST H 4. RST 5.5 2CH

3 The TRAP has the highest priority, followed by RST,6.5,5.5, and INTR, in that order TARP: a non mask able interrupt known as NMI, it has the highest priority, it need not be enabled ; and it cannot be disable. RST: (Restart) Special Restart Instruction used with interrupts. It can be used as software instruction in a program to transfer program execution to one of the eight Locations. The addresses are: Instruction RST RST RST 2 RST 3 RST 4 RST 5 RST 6 RST 7 Restart Address H 8H H 8H 2H 28H 3H 38H SIM: (set interrupt mask) This is a multipurpose instruction and used to implement The 885 interrupts, 6.5, 5.5, and serial data output. The instruction interrupts the accumulator contents as following:

4 SOD SDE Xxx R MSE M M 6.5 M5.5 RST MASK = available RST 6.5 MASK = masked Ignored If, bit 7 is output to Serial Output Data Latch Serial Output Data : ignored if bit 6= RST 5.5 MASK If,Bits -2 ignored Mask Set Enable -- If, mask is set RESET RST :if,rst flip-flop is reset OFF Figure (2.2) Interpretation of the Accumulator Bit Example (2.). Enable all the interrupts in an 885 system Instructions EI ;Enable interrupts MVI A,8H ;Load bit Pattern to enable RST,6.5 and 5.5 SIM ;Enable RST,6.5,and 5.5 Bit D 3 = in the accumulator makes the instruction SIM functional, and bits D 2, D, and D = enable the interrupts,6.5 and 5.5 Example (2.2) Reset the interrupt from Example 2. Instructions MVI A, 8H ; Set D 4 = SIM ; Reset interrupt flip-flop

5 RIM: (Read Interrupt Mask ) this is a multi purpose instruction used to read the Status of interrupts, 6.5,5.5 and read serial data input bit. The instruction loads eight bits in the accumulator with the following interpretations: SID E Interrupt Masks : = masked Serial Input Data Bit, if any Interrupt Enable Flag : = enabled Pending Interrupts: = Pending Figure (2.3) Interpretation of the Accumulator Bit Pattern for the RIM Instruction CONTROL INSTRUCTIONS.NOP: (No operation ) No operation to be performed. 2. HLT: (Halt and enter wait state ) The CPU finishes executing the current instruction And halts any further execution. 3. DI: (Disable Interrupt System) The interrupt enable flip-flop is reset and all the Interrupts except the TRAP are disabled. No flags are affected. 4. EI: (Enable Interrupt System ) The interrupt enable flip-flop is set and all interrupts Are enabled. No flags are affected.

6 If INTR is activated, the 885 responds with INTA Pulse, during the IINTA pulse, the 885 expect to see an instruction applied to it is data bus. 74LS244 kω AD7 AD6 AD5 kkk kωω ΩΩ E Ω +5v 885 AD4 AD3 AD2 AD AD 7 INTA INTR A circuit that causes an RST4 instruction (E7)H to be executed in response to INTR. The RST4 instruction causes the subroutine stored beginning at OO2H to be executed..