AGENDA Tuesday March

Transcription

1 AGENDA Tuesday March :30 08:55 REGISTRATION 08:55 09:00 WELCOME by Bjørn Gjerstad /CADPIT/DNU 09:00 09:45 Why E-CAD Libraries and Management of Electronic Components Matters by Robert Huxel /Altium/4TEST The key success factor is an integration of library and component data for electronics engineering, tapping all available data sources in the organization and enabling engineering to make smarter decisions. Allowing better decisions from the beginning reduces the development time and cost through standardized and integrated solutions that go way beyond the capabilities of third-parties and vendors, which can provide only partial solutions. 09:45 10:00 15 minutes break & refreshments. 10:00 10:45 HyperLynx DRC by Steve Gascoigne /InnoFour/Mentor Graphics HyperLynx DRC is a powerful, fast design rule checking tool that is fully customizable. It allows for verification of complex design rules that are not easily simulated, such as rules for EMI/EMC. With 23 standard Design Rule Checks (DRCs) for items such as traces crossing splits, reference plane changes, shielding and via checks, you can quickly and easily pinpoint trouble spots on your board that can cause issues with EMI/EMC, Signal Integrity, and Power Integrity. 10:45 11:00 15 minutes break & refreshments. 11:00 11:45 Optimised DDR4 and PCI Express Routing in a 3-D PCB Design Application: Requirements and Results by John Berrie /CTS Bristol/Zuken John Berrie will present, in straightforward terms, key requirements of PCI Express and DDR4, followed by results obtained in Zuken latest new EDA solution CR-8000 Design Force. He will show how continuous 3-D design visibility makes it easier to avoid unexpected design spins by avoiding common errors. Author Bio: John Berrie has been widely published on high-speed PCB design from the 1980s to the present day. He was Session Chair, 3D IC and Package Design Issues at the Design Automation Conference (DAC) 2007, San Diego. John is a Member of the Institute of Electronic and Electrical Engineers and hold a Master of Science degree in digital electronics. 11:45 12:00 15 minutes break & refreshments.

2 12:00 12:45 Advanced Layout Checks for Power-Aware Signal Integrity by Kristoffer Sander Skytte /Cadence/GATEline Abstract: Today's PCB design rules are getting more and more complicated. DRC in the layout tool is the starting point of PCB layout checks. While still important and used for almost every PCB layout design, DRCs are unable to handle complicated design rules. The PCB designers, layout engineers and SI engineers all need more advanced PCB layout check options that provide more insight into the electrical performance of a design. In this presentation we will discuss what electrical design checks can be performed on a layout and discuss how these checks can be used to implement a more electrically aware design yielding a more robust implementation. Several examples will be shown on how these checks can help identify issues in the layout and help mitigate these issues. Kristoffer Sander Skytte is Staff Application Engineer, System Level SI/PI from Cadence Design Systems. 12:45 13:00 15 minutes buffer 13:00 14:00 LUNCH 14:00 14:45 Thermal Analysis of PCB s by IR measurement by Koen Jacobs /Flir/4TEST For several years, thermal cameras are widely used in the field of electronics and printed circuit boards, to great benefit of the users of those systems. With cameras becoming ever more affordable, we see a growing mismatch between the user s measurement requirements and camera performance, leading to faulty conclusions and potential disastrous consequences. During this talk we would like to rectify this situation by shedding a light on all measurement parameters and their influence on the result. The goal is to provide a clear insight in what is and what is not possible when using a thermal camera. 14:45 15:00 15 minutes break & refreshments. 15:00 15:45 Bridging the PCB and HDL-based FPGA design worlds by Olivier Arnauld /InnoFour/Mentor Graphics How many boards embed FPGAs today? How many of your PCB layout experts look forward to placing a pin FPGA Device and constantly have to worry about new pinout coming from the FPGA designer? Today s powerful and extremely high pin-count FPGAs provide engineers with significant opportunities for increased features and more functionality whilst reducing the cost of their products. But with this increased complexity comes significant challenges in integrating these devices onto the Printed Circuit Board, with the need to map hundreds of logical signals to the physical pin out of the device whilst maintaining the electrical integrity of the design. This presentation will show not only how to ease the FPGA-on-board integration process by bridging the two worlds of FPGA and PCB design but also how to guarantee the optimal FPGA I/O design and physical implementation on the PCB significantly reducing both design time cycle and therefore time-to-market as well as manufacturing costs. 15:45 16:00 15 minutes break & refreshments. 16:00 17:30 Annual Meeting DNU by Bjørn Gjerstad /CADPIT/DNU Just for DNU members. After the closing of annual meeting, the board invites to an open meeting and brain storming about the future of DNU. 17:30 19:00 Pause 19:00 00:00 Banquet. 4-course dinner with special wine package in the hotels restaurant.

3 AGENDA Wednesday March The USERDAY is organized as parallelle sessions in separate rooms. Our partners/cad-tool suppliers are responsible for agenda, details and timing this day. LUNCH BREAK 13:00-14:00 for all. Basic information: Seminar fee: NOK includes both days and banquet Tuesday evening. NOK for non-members. Refer to registration for more information. Please fill out all details in the registration, as this is the source for billing and invoice. Hotel room and travel must be booked and paid individual by all attendees. Refer to DNU / Den Norske Utleggerforening when booking. The seminar is open to all attendees. Annual meetings are closed; just for members. You can sign new membership before registration is closed. Seminar hotel: Thon Hotel Linne, Oslo. Booking code: Hotel booking: linne.booking@thonhotels.no Single room standard: kr 1395,- Hotel Link: Address: Statsråd Mathiesens vei 12, 0598 Oslo Phone: linne@thonhotels.no REGISTRATION We may limit the number of attendees without further notice. Those who are affected will get feedback. Registration at DNU website before March 10. MEMBERSHIP IN DNU Please send to: KjellArild.Thu@westcontrol.com Annual fee: NOK per company. Members have discount on seminars.

4 CADSTAR USER DAY 09:00 09:15 Start/Introduction by Jan Erik Johansen / Tony Cadwell 09:15 09:45 What s targeted for CADSTAR 16 by Jeronen Leinders 10:15 10:30 15 minutes break & refreshments. 10:30 11:15 What s targeted for CADSTAR 17 by Jeronen Leinders 11:15 12:00 Why should I care about Power Integrity by Bob Sadowski 12:00 12:10 10 minutes break 12:10 13:00 Future vision and roadmap by Jeronen Leinders 13:00 14:00 LUNCH 14:00 14:45 Cadstar s Integrated Routing Platform by Bob Sadowski 14:45 15:00 15 minutes break & refreshments. 15:00 16:00 Tricks and Tips for Common Design Queries by Bob Sadowski End of day.

5 MENTOR GRAPHICS USER DAY JOINT SESSION Annual Meeting MugNor Market leading Front-end design by Mentor Graphics - Olivier Arnauld Solutions and Strategies for 2015 Coffe Break Market leading Front-end design by Mentor Graphics Continued Library and Part creation Ease of use and enhancements Starter libraries Analog simulation in the same schematic, why draw 2? Migration strategies LUNCH Break Break up into two sessions TRACK A PADS VX Product Update Steve Gascoigne VX, a future-focused desktop platform The PADS VX release is a complete approach to desktop PCB design, offering smarter productivity, higher quality, and greater speed and accuracy to individuals and small teams than ever before. Let s take some time to review the addition which have been made during the last 12 months. VX, a future-focused desktop platform Starter Libraries Land Pattern Creator Central Library Library Management Utilities Easier schematic design Constraint Management Integrated Central Database Design Archive with graphical and data comparisons PADS Futures Steve Gascoigne During 2015 the PADS range of products will see some dramatics advancements. PADS will reinforce its position as the industry s most affordable professional desktop solution that uniquely forms part of a fully scalable, future proofed PCB solution. Mentor have continued t invest in this product and brings more to the customer that ever before. Release Highlights Product plans

6 TRACK B xpcb (Expedition)Layout Environment Olivier Arnaud With the VX release xpcb layout has undergone a significant change in look and feel. The overall goal of this new release is to increase the productivity of everyone on your team! Menus and toolbars refreshment and optimization Greater personalization Maximization of designer s work area Context sensitive menus and instant status All adds up to an improved experience inside Xpedition xpcb Layout Placement/Planning and Routing Automation Olivier Arnaud Learn about the xpcb Layout planning and placement improved methodology through a brand new planning environment including among other features: Component Explorer interface to provide a highly intuitive, personalized environment for PCB layout Explorer spreadsheet to provide valuable placement information and filtering capabilities Graphical cues such as group status icons to relate important information to the designer Ability for the user to defined planning groups on the fly Connectivity visualization through netlines (Dynamic or according to specific preferences) Marking options may be used for both groups and individual parts. Join everyone again Coffe Break HyperLynx Tool suit advancements during 2015 Steve Gascoigne HyperLynx is now a full family of products, each with unique and powerful capabilities. Lets a take a look how each of these tools is being updated and functionality is being more tightly integrated with your PCB design flow. Release Highlights and Product Plans Release Highlights Product plans" Wrap up and questions

7 ORCAD / CADENCE USER DAY Agenda for Day 2 at DNU :00 09:15 Introduction Carl Otto Saugen 09:15 09:45 What s New in OrCAD Capture CIS 16.6 QIRx Carl Otto Saugen Presentation and demonstration 09:45 10:15 What s New in OrCAD/Allegro PCB Editor 16.6 QIRx Melek Mentes Presentation and demonstration 10:15 10:45 New products from Cadence Design Systems and PCB Libraries Carl Otto Saugen & Melek Mentes 10:45 11:15 Coffee break Presentation and demonstration OrCAD Engineering Data Management OrCAD Documentation Editor PCB Library Expert 11:15 11:30 Cadence OrCAD and Allegro release plan for 2015 Melek Mentes 11:30 13:00 Advanced Layout Checks for Power-Aware Signal Integrity Kristoffer Skytte 13:00 14:00 Lunch Workshop Layout based design checks Delay matching checks 14:00 15:15 Continuing, Advanced Layout Checks for Power-Aware Signal Integrity Kristoffer Skytte Workshop DC IR drop layout checks Quantifying influence of routing choices 15:15 15:30 Coffee break 15:30 16:00 Continuing, Advanced Layout Checks for Power-Aware Signal Integrity Kristoffer Skytte Workshop Wrap up of ERC and DC IR drop layout checks

8 ALTIUM USER DAY Bye Robert Huxel from Altium. 1. Corporate Update 2. News in AD - from AD10 till today a. High-speed design with Differential pairs, Multi-trace, length tuning and impedance controlled routing. b. Enhanced Length (Phase and Delay) Tuning and xsignals 3. Using 3D Mechanical parts in practice, how to turn on/off each part for better visualization if the PCB fits into an mechanical part 4. Flex-print functions 5. Vaults: Library Concepts & Scalable Data-Management Solutions 6. QA session Including Classes and Rooms