Synchronous Rectification

Transcription

1 Synchronous Rectification Channel DC/DC Converter IC A synchronous rectification channel DC/DC converter IC adopting the type. It operates at a maximum of MHz with two builtin channels in TSSOP6 and QFN and contributes to coil and capacitor miniaturization. The powersupply voltage range is wide (.V to 7V), making it optimal for electronic devices including digital AV devices. Overview FUJITSU has devoted its efforts to switchingtype builtin powersupply ICs and has already developed many models. As a new product of synchronous rectification channel powersupply IC, we have developed, a synchronous rectification channel DC/DC converter IC that can support a powersupply voltage range of.v to 7V. This product incorporates two channels in TSSOP6 and QFN and is capable of operating at MHz at maximum, contributing to the miniaturization of coils and capacitors. Thanks to / MOS FETtype synchronous rectification, use is possible with synchronous rectification when output voltage is low and with asynchronous rectification when output voltage is relatively high. For use with synchronous rectification, the flyback diode can be removed. Output voltage can be set to an optional value by using an external resistor. In addition, it is equipped with a softstart function that prevents inrush current at powersupply startup with optional setting of powersupply startup time that does not Photo External View (TSSOP6) Photo External View (QFN)

2 depend on output load. It also incorporates a timer latch shortcircuit protection circuit as a protective function. With such features, this product is optimal for various electronic devices including digital AV devices. Product Features Wide powersupply voltage range:.v to 7V For high frequency operation supported: MHz (Max.) For synchronous rectification type supported (CH, CH) Any output voltage setting by external resistor uiltin standby function: 0A (Typ.) Low current consumption:.6ma (Typ., at quiescence condition) uiltin softstart circuit that allows independent control of each channel without load dependency (dual function as capacitance for softstart) uiltin totempoletype output for / external MOS FET Package: TSSOP6, QFN Circuit configuration Figs. and illustrate the pin assignments and Figs. and are block diagrams of TSSOP6 and QFN, respectively. This product is composed of the following functional blocks: DC/DC converter function Triangular wave oscillator block (OSC) The triangular wave oscillator block incorporates a capacitor for oscillation frequency setup. It generates a triangular wave oscillation waveform by connecting a resistor for setting the triangular wave oscillation frequency at the RT terminal. A triangular wave is input to the comparator in the IC. amplifier block ( Amp, ) amplifiers ( Amp, ) are amplifiers that detect the DC/DC converter output voltage and output control signals. Any output voltage can be set up by connecting an external output voltage setting resistor to the error amplifier inverted input terminal. Stable phase compensation against the system can be attained by setting up an optional loop gain through a Figure Pin Assignments (TSSOP6) Figure Pin Assignments (QFN)

3 connection of the feedback resistor and capacitor from the Amp output (F terminal, F terminal) to the inverted input terminal (INE terminal, INE terminal). y connecting a capacitor for softstart to C and terminals, the noninverted input terminals of the error amplifier, inrush current at power startup can be eliminated. y executing softstart detection with an error amplifier, it operates with a stable softstart time independent from the DC/DC converter output load. comparator block ( Comp.) The comparator is a voltagepulse width modulation that controls the output duty depending on the output voltage of the error amplifier ( Amp, ). The output transistor is turned ON when the triangular wave voltage generated by the triangular wave oscillator is lower than the error amplifier output voltage. Output block (Drive,, Drive, ) The output circuit has CMOSstyle construction on both Figure lock Diagram (TSSOP6) A INE 7 stepdown (.8u) (0.8u) (.8u) (0.8u) Amp F 6 << CH >> Vcc Vo A (.V) OUT Drive Drive OUT stepdown VIN (6V to 7V) INE F 0 Amp << CH >> Drive Drive OUT OUT Vo () (.7V) C 9.9V (.7V) C 8 SR Latch.9V (VccV) ias 6 Reset UVLO OSC CT bias (V) Amp Ref. () ias VR Power ON/OFF VCC H:ON (Power ON) L:OFF(Standby mode) VTH=.V RT GND

4 the main and synchronous rectification sides. The main side is capable of driving an external MOS FET while the synchronous rectification side can drive an external MOS FET. Powersupply control block () The system goes into standby status by setting the terminal tollevel (powersupply current at standby 0A Max.). The DC/DC converter block can be put into operation status by setting the terminal tohlevel. Table presents a list of control functions. Protective functions Timer latch shortcircuit protection circuit block ( Comp.) Each channel uses the shortcircuit protection comparator ( Comp., ) to continuously compare the error amplifier output level and the reference voltage. When the load conditions of the DC/DC converter are stable, there is no output fluctuation for error amplifiers; in this way, the short Figure lock Diagram (QFN) A INE 7 stepdown (.8u) (0.8u) (.8u) (0.8u) Amp F Vcco << CH >> Vo A (.V) OUT Drive Drive OUT stepdown VIN (6V to 7V) INE F Amp << CH >> Drive Drive OUT 8 OUT 7 Vo () PGND (.7V) C.9V (.7V) C 8 SR Latch.9V (VccV) ias 0 Reset UVLO OSC CT bias (V) Amp Ref. () ias VR Power ON/OFF 6 VCC H:ON (Power ON) L:OFF(Standby mode) VTH=.V RT GND

5 circuit protection comparators also keep their balance. At this time, C and terminals are retained at their softstart completion voltage (approximately.v). When the load conditions change drastically by load shortcircuit, etc. and the DC/DC converter output decreases, capacitors C and are further charged once the error amplifier output reaches.9v or higher. Latch is set when capacitors C and are charged to approximately and the / external MOS FET is turned OFF (dead time is set to 00%). At this point, latch input is closed and C and terminals are maintained atllevel. When the protection circuit operates, it can be reset by restarting the power supply to set the terminal input to.v (Min.) or lower. Undervoltage lockout protection circuit block (UVLO) Momentary drops in the powersupply voltage may cause the control IC to malfunction and lead to system deterioration or damage. To prevent such malfunction, the undervoltage lockout protection circuit detects decreases in voltage and maintains the OUT terminal and OUT terminal to Hlevel and the OUT terminal and OUT terminal tollevel. The system restores itself when the voltage exceeds the threshold voltage of the undervoltage lockout protection circuit. Table presents a list of functions undervoltage protection circuit (UVLO) operation. Table Table of Control Functions Table Table of Functions under Protective Circuit (UVLO) Operation