IDT79RC32134 RISCore TM Family System Controller Chip User Reference Manual

Transcription

1 IDT79RC32134 RISCore TM Family System Controller Chip User Reference Manual May Stender Way, Santa Clara, California Telephone: (800) TWX: FAX: (408) Printed in U.S.A Integrated Device Technology, Inc.

2 DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc. LIFE SUPPORT POLICY Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IDT. 1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. The IDT logo, Dualsync, Dualasnyc and ZBT are registered trademarks of Integrated Device Technology, Inc. IDT, QDR, RisController, RISCore, RC3041, RC3051, RC3052, RC3081, RC32134, RC32364, RC36100, RC4700, RC4640, RC64145, RC4650, RC5000, RC64474, RC64475, SARAM, Smart ZBT, SuperSync, SwitchStar, Terasync,Teraclock, are trademarks of Integrated Device Technology, Inc. Powering What's Next and Enabling A Digitally Connected World are service marks of Integrated Device Technology, Inc. Q, QSI, SynchroSwitch and Turboclock are registered trademarks of Quality Semiconductor, a wholly-owned subsidiary of Integrated Device Technology, Inc.

3 About This Manual Introduction This reference user manual includes both hardware and software information on the RC32134, a high performance system controller chip that supports IDT s RISCore32300 CPU family. The RC32134 offers a direct connection to IDT s RC bit embedded microprocessor and provides the system logic for boot memory, main memory, I/O, and PCI. It also includes on-chip peripherals such as DMA channels, reset circuitry, interrupts, timers, and UARTs. Together, the RC32364 CPU and the RC32134 system controller form a complete CPU subsystem for embedded designs. Additional Information Information not included in this manual such as mechanicals, package pin-outs and electrical characteristics can be found in the data sheet for this device, which is available from the IDT website ( as well as through your local IDT sales representative. Content Summary Chapter 1, RC32134 Device Overview, provides a complete introduction to the performance capabilities of the RC Included in this chapter is a summary of features for the device as well as a system block diagram and internal register maps. Chapter 2, RC32364 Bus Interface, presents a general overview on the RC32134 s internal bus and bus controller unit that provides an easy connection between peripherals and controllers. Chapter 3, Memory Controller, provides a functional overview on the CPU, DMA or PCI Bridge generated transactions. A block diagram, register maps, signal description table, and timing diagrams for various read and write operations are also included. Chapter 4, Synchronous DRAM Controller, contains a discussion on the operations and support provided by the RC32134 s 32-bit SDRAM controller. Timing diagrams are provided to illustrate the different read and write transactions. Chapter 5, EDODRAM Controller, contains general information on the RC32134 s EDODRAM Controller and includes timing diagrams that illustrate the read and write transactions supported. Chapter 6, PCI Interface Controller, contains descriptions on the PCI host/satellite modes and master/target operations supported in the RC Register maps and register field definitions are included. Chapter 7, DMA Controllers, includes descriptions on the four general purpose DMA channels and the transfer operations supported. Byte swapping between big- and little-endian is also discussed and includes examples. Chapter 8, Expansion Interrupt Controller, provides a functional and operational overview on this controller. This chapter includes a block diagram, signal definitions and register mapping tables for each of the 14 groups supported. Chapter 9, Programmable I/O (PIO) Controller, provides the signal descriptions, register mapping and programming information on the software programmable options of the RC32134 s 12 peripheral pins. Chapter 10, Timer Controller, provides a user overview on the functions of the RC32134 s eight onchip timers. A block diagram, signal definitions and register maps are included. Chapter 11, UART Controller, describes the operations of the two compatible UARTs available on the RC Register maps and descriptions are included. 79RC32134 User Reference Manual i May 4, 2001

4 About This Manual Revision History Chapter 12, JTAG Boundary Scan, introduces the standard JTAG interface used for board-level debugging. A description on the Test Access Port (TAP) interface and TAP controller state assignments is also included. Revision History March 1999, Version 1.0: Initial publication. November 1999, Version 1.1: Removed Serial Peripheral Interface chapter, added new timing diagrams, and made numerous revisions throughout the document. January 2000, Version 1.2: Revised timing diagrams in Figures 3.6 and 3.21 in Chapter 3. In Chapter 9, switched alternate pin signals for pci_eeprom_mdo and pci_eeprom_mdi in Table 9.1 and switched alternate pin signals for uart_rx and uart_tx in Table 9.2. July 12, 2000: Added timing diagram Figure to Chapter 11. September 22, 2000: In Chapter 6, PCI Interface Controller, bit numbers have been corrected in Figure 6.3 and Table 6.7. April 16, 2001: Revised timing diagrams in Figures 2.6 and 2.7. May 4, 2001: Changed reference from 66MHz to 33MHz in Figure 1.2 and in PCI Bridge paragraph on page 1-4. Changed incorrect references on page 6-3 from to RC32134 User Reference Manual ii May 4, 2001

5 Table of Contents About This Manual Introduction...i Additional Information... i Content Summary...i Revision History... ii 1 RC32134 Device Overview Introduction Block Diagram Documentation Conventions and Definitions List of Features System Block Diagram System Overview Pin Descriptions Logic Diagram RC Typical RC32134 Memory Map RC32134 Internal Register Map Addresses and Definitions BIU Control Registers Base Address and Base Mask Registers Memory Control Registers DRAM Memory Controller Registers Expansion Interrupt Registers Programmable I/O Registers Timer Controller Registers UART Control Registers DMA Control Registers PCI Interface Control Registers RC32364 Bus Interface Introduction List of Features Block Diagram Functional Overview Address Module Address Incrementer Address MUX Address Decode Data Module CPU Read/write Operations DMA Read/write Operations Arbitration RC32134 User Reference Manual iii May 4, 2001

6 Table of Contents Memory Port Sizing Bus Turnaround (BTA) Register Reset Logic reset_boot_mode Settings pci_host_mode Settings Watchdog Timer Bus Time-Out Counters Bus Error Timers RC32364 to RC32134 Signal References Register Descriptions BTA Control Register Address Latch Timing Register Arbitration Register BusError Control Register Memory Controller Introduction List of Features Block Diagram Functional Overview Memory Controller Operation CPU Generated Transactions DMA Controller or PCI Bridge Generated Transactions Chip Selects Transceiver Control Interface Using 8- or 16-bit Boot PROMS Wait-State Generator (WSG) Address Decoding Memory Type and Port-Width Size Support Port-Width Size I/O Width Support Programmable Wait-State Generator External Wait-State Behavior Bus Error Recovery Signal Descriptions Register Definitions Memory MSB Base Address Register for Banks 1: Memory MSB Bank Mask Registers for Banks 1: Memory Control Register for Banks 5: Timing Diagrams Synchronous DRAM Controller Introduction Features Block Diagram Functional Overview RC32134 User Reference Manual iv May 4, 2001

7 Table of Contents Base Address Decoding Page Comparator Burst Support RAS/CAS Address MUX Refresh Timer Error Recovery SDRAM Initialization Register Definitions SDRAM Control Register Timing Diagrams EDODRAM Controller Introduction Features Base Address Decoding Page Comparator Memory Width Support Burst Support RAS/CAS Address MUX Refresh Timer Wait-States Reset Initialization and Special Modes Error Recovery External SYSWait Behavior Register Definitions EDODRAM Control Register Timing Diagrams PCI Interface Controller Introduction Features Functional Overview RC32134 PCI Bus Master Operation RC32134 PCI Bus Target Operation PCI Commands Supported PCI Configuration Register Access PCI Interrupts Signal Definitions Register Definitions PCI Controller Interrupt Pending Register CPU to PCI Mailbox Interrupt Pending Register PCI to CPU Mailbox Interrupt Pending Register PCI Arbitration Register PCI Memory Space 1, 2, 3, or I/O Base Register PCI CPU Memory Space 1 Base Register or PCI CPU I/O Space Base Register PCI Configuration Address Register PCI Configuration Data Register RC32134 PCI Configuration Registers RC32134 User Reference Manual v May 4, 2001

8 Table of Contents Vendor ID Register Device ID Register PCI Command Register PCI Status Register Device Revision Identification Register Class Code Register Cacheline Size Master Latency Timer Register Header Type BIST Memory Base Address I/O Base Address Subsystem Vendor ID Subsystem ID Interrupt Line Register Interrupt Pin Register MIN_GNT Register MAX_LAT Register TRDY Timeout Value Retry Timeout Value DMA Controllers Introduction List of Features Block Diagram DMA Operations Endianness Swapping DMA Transfer Modes DMA Transfer Operations Last Partial Word Transfers Transfer Restrictions DMA Arbitration Methods Signal Definitions Internal DMA Interrupt Signals Register Mapping and Descriptions Configuration Register Base Descriptor Address Register DMA Example Current Address Register Source Address Register Destination Address Register Next Descriptor Address Register Status Register Timing Diagrams RC32134 User Reference Manual vi May 4, 2001

9 Table of Contents 8 Expansion Interrupt Controller Introduction Features Block Diagram Operational Overview Signal Definitions Registers and Address Mapping Interrupt Pending Register Interrupt Mask Register Interrupt Clear Register Register Group Settings Register Group 0 Settings Register Group 1 Settings Register Group 2 Settings Register Group 3 Settings Register Group 4 Settings Register Group 5 Settings Register Group 6 Settings Register Group 7 Settings Register Group 8 Settings Register Group 9 Settings Register Group 10 Settings Register Group 11 Settings Register Group 12 Settings Register Group 13 Settings Register Group 14 Settings Timing Diagrams RC32134 Interrupt Flow Initialize Interrupts Wait for Interrupt Software Interrupt Service Routine (ISR) Optional Algorithm for Priority Interrupts Optional Algorithm for Non-Prioritized Interrupts Programmable I/O (PIO) Controller Introduction Features Overview Block Diagram Performing Initialization Programming Signal Definitions Register Mapping and Definitions PIO Data Register PIO Direction Register Pio Function Select Register Timing Diagrams RC32134 User Reference Manual vii May 4, 2001

10 Table of Contents 10 Timer Controller Introduction Features Block Diagram Overview Signal Definitions Register Mapping Timer Control Register Description Timer Count Register Timer Compare Register Timing Diagrams UART Controller Introduction Features Block Diagram Overview User Interrupts Signal Definitions UART Operation Register Definitions Receiver Buffer Register (Rbr) Transmitter Buffer Register (Thr) Interrupt Enable Register (Ier) Divisor Latch, Ls (Dll) Divisor Latch, Ms (Dlm) Interrupt Identity Register (Iir) Buffer Control Register (BCR) Line Control Register - LCR MODEM Control Register - MCR Line Status Register - LSR MODEM Status Register - MSR Scratch Register - SCR Timing Diagram JTAG Boundary Scan Introduction Functional Overview Signal Definitions Tap Controller Test Data Register (DR) Boundary Scan Registers Instruction Register (IR) EXTEST SAMPLE/PRELOAD BYPASS DEVICEID RC32134 User Reference Manual viii May 4, 2001

11 Table of Contents VALIDATE RESERVED UNUSED Usage Considerations RC32134 User Reference Manual ix May 4, 2001

12 Table of Contents 79RC32134 User Reference Manual x May 4, 2001

13 List of Tables Table 1.1 Example of Byte Ordering for "Big Endian" or "Little Endian" System Definition Table 1.2 RC32134 Pin Descriptions Table 1.3 RC32364 and RC32134 Typical Memory Map Table 1.4 Internal Address Map for BIU Control Registers Table 1.5 Internal Address Map for Memory and DRAM Base Address and Base Mask Registers1-18 Table 1.6 Internal Address Map for Memory Control Registers Table 1.7 Internal Address Map for DRAM Memory Controller Registers Table 1.8 Internal Address Mapping of Expansion Interrupt Registers Table 1.9 Internal Address Mapping of Programmable I/O Registers Table 1.10 Internal Address Mapping of Timer Controller Registers Table 1.11 Internal Mapping of UART 0 Registers Table 1.12 Internal Mapping of UART 1 Registers Table 1.13 Internal Address Mapping of DMA Channel 0 Registers Table 1.14 Internal Address Mapping of DMA Channel 1 Registers Table 1.15 Internal Address Mapping for DMA Channel 2 Registers Table 1.16 Internal Address Mapping for DMA Channel 3 Registers Table 1.17 Internal Address Mapping for PCI Interface Control Registers Table 2.1 RC32134 reset_boot_mode Initialization Settings Table 2.2 RC32134 pci_host_mode Initialization Settings Table 2.3 RC32364 to RC32134 Signal References Table 2.4 CPU to IP Register Addresses and Descriptions Table 2.5 Bus Turnaround (BTA) Control Register Field Descriptions Table 2.6 Width Encoding of Bus Turnaround Cycles Table 2.7 Address Latch Timing Bit Field Descriptions Table 2.8 Arbitration Field Values and Action Description Table 2.9 BusError Control Register Field Descriptions Table 2.10 SysID Register Field Descriptions Table and 16-bit LSB Addresses and Write-Enable Connections Table 3.2 RC32364 and RC32134 Typical Memory Map Table 3.3 Memory Type Field Values and Actions Table 3.4 Port Width Size Field Values and Actions Table 3.5 Minimum Wait-State Settings Table 3.6 Memory Controller Pin Descriptions Table 3.7 List of Memory Control Registers Table 3.8 Internal Chip Select Base Addresses Table 3.9 Internal Chip Select Grouping Table 3.10 Memory Mask Field Definitions and Values Table 3.11 Memory Controller Register Field Descriptions, Channels 5: Table 4.1 Supported SDRAMs Table 4.2 SDRAM Address Multiplexing Table 4.3 SDRAM Command Encoding Table 4.4 Base Address and Base Mask Address Map Table 4.5 RC32341 SDRAM Register Map and Descriptions Table 4.6 SDRAM Control Register Field Descriptions Table 5.1 Base Address and Base Mask Address Map Table 5.2 EDODRAM Address Multiplexing Table 5.3 Bank Size Configuration for EDODRAM modules Table 5.4 EDODRAM Register Mapping Table 5.5 EDODRAM Control Register Field Descriptions RC32134 User Reference Manual xi May 4, 2001

14 List of Tables Table 6.1 Initialization Pins mem_addr[22:20] Settings Table 6.2 PCI Address Map Table 6.3 PCI Commands Table 6.4 RC32134 Muxed PCI Pin Names and Directions Table 6.5 Definitions of PCI Control Registers Table 6.6 PCI Controller Interrupt Pending Register 11 Field Descriptions Table 6.7 CPU to PCI Mailbox Interrupt Pending Register 12 Field Descriptions Table 6.8 PCI to CPU Mailbox Interrupt Pending Register 13 Field Descriptions Table 6.9 PCI Arbitration Register Field Descriptions Table 6.10 PCI Memory Space 1, 2, 3 or I/O Base Register Field Descriptions Table 6.11 PCI CPU Memory Space 1 Base Register or PCI CPU I/O Space Base Field Descriptions Table 6.12 PCI Configuration Address Register Field Descriptions Table 6.13 PCI Configuration Data Register Field Description Table 6.14 RC32134 PCI Configuration Registers Table 6.15 Vendor ID Address Field Description Table 6.16 Device ID Address Field Description Table 6.17 Command Register Table 6.18 Configuration PCI Status Register Table 6.19 Configuration Device Revision Identification Register Field Description Table 6.20 Class Code Register Field Description Table 6.21 Class Code Definitions Table 6.22 Configuration Cacheline Size Field Description Table 6.23 Master Latency Timer Register Field Descriptions Table 6.24 Header Type Register Field Description Table 6.25 BIST Register Field Description Table 6.26 Configuration Memory Base Address Field Description Table 6.27 Configuration I/O Base Address Field Description Table 6.28 Subsystem Vendor ID Field Description Table 6.29 Subsystem ID Field Description Table 6.30 Interrupt Line Register Field Description Table 6.31 Interrupt Pin Register Field Description Table 6.32 MIN_GNT Register Field Description Table 6.33 MAX_LAT Register field Description Table 6.34 TRDY Timeout Value Field Description Table 6.35 Retry Timeout Value field Description Table 7.1 Fixed Priority Encoding Table 7.2 DMA Signal Pins and Definitions Table 7.3 DMA Interrupt Definitions Table 7.4 Channel 0 Register Mapping Table 7.5 Channel 1 Register Mapping Table 7.6 Channel 2 Register Mapping Table 7.7 Channel 3 Register Mapping Table 7.8 Configuration Register Field Descriptions Table 7.9 Base Descriptor Address Field Description Table 7.10 Current Descriptor Address Field Description Table 7.11 Source Address Register Field Description Table 7.12 Destination Address Field Description Table 7.13 Next Descriptor Address Field Description Table 7.14 Status Register Table 8.1 Interrupt Signal Pins and Definitions Table 8.2 Address Mapping for Expansion Interrupt Registers, Group Table 8.3 Address Mapping for Bus Error Registers, Group Table 8.4 Address Mapping for PIO Low Registers, Group Table 8.5 Address Mapping for PIO High Registers, Group RC32134 User Reference Manual xii May 4, 2001

15 List of Tables Table 8.6 Address Mapping for Timer Rollover Interrupt Registers, Group Table 8.7 Address Mapping for UART 0 Interrupt Registers, Group Table 8.8 Address Mapping for UART 1 Interrupt Registers, Group Table 8.9 Address Mapping for DMA Channel 0 Registers, Group Table 8.10 Address Mapping for DMA Channel 1 Registers, Group Table 8.11 Address Mapping for DMA Channel 2 Registers, Group Table 8.12 Address Mapping for DMA Channel 3 Registers, Group Table 8.13 Address Mapping for PCI Controller Interrupt Registers, Group Table 8.14 Address Mapping for External Interrupt Registers, Group Table 8.15 Address Mapping for PCI to CPU Interrupt Registers, Group Table 8.16 Address Mapping for SPI Interrupt Registers, Group Table 8.17 Interrupt Pending Field Description Table 8.18 Interrupt Mask Register Table 8.19 Interrupt Clear Register Field Descriptions Table 8.20 Group 0 Register Settings Table 8.21 Group 1 (Bus Error) Register Settings Table 8.22 Group 2 (PIO Low) Register Settings Table 8.23 Group 3 (PIO High) Register Settings Table 8.24 Group 4 (Timer Rollover Interrupt) Register Settings Table 8.25 Group 5 (UART 0 Interrupt) Register Settings Table 8.26 Group 6 (UART 1 Interrupt) Register Settings Table 8.27 Group 7 (DMA Memory2I/O Interrupt 0) Register Settings Table 8.28 Group 8 (DMA Memory2IO Interrupt 1) Register Settings Table 8.29 Group 9 (DMA PCI Master Interrupt 0) Register Settings Table 8.30 Group 10 (DMA PCI Master Interrupt 1) Register Settings Table 8.31 Group 11 (PCI Controller) Register Settings Table 8.32 Group 12 Register Settings Table 8.33 Group 13 Register Settings Table 8.34 Group 14 Register Settings Table 9.1 Serial Mode Protocol/Alternate Signal Descriptions Table 9.2 UART Interface/Alternate Signal Descriptions Table 9.3 Timer/Alternate Signal Descriptions Table 9.4 DMA Interface/Alternate Signal Descriptions Table 9.5 PIO Register Map and Description Table 9.6 PIO Data Register 0 Field Description Table 9.7 PIO Direction Register 0 Description Table 9.8 PIO Effect Select Register 0 Field Descriptions Table 10.1 Pin Definitions for the Timer/Counter Signals Table 10.2 Address Mapping for Timer Register 0 (General Purpose) Table 10.3 Address Mapping of Timer Register 1 (General Purpose) Table 10.4 Address Mapping of Timer Register 2 (General Purpose) Table 10.5 Address Mapping of Register 3, for Watchdog Table 10.6 Address Mapping of Register 4, for CPU Bus Time-out Table 10.7 Address Mapping of Register 5, for IP Bus Time-out Table 10.8 Address Mapping of Register 6, for DRAM Refresh Table 10.9 Address Mapping of Register 7 for Warm Reset Table Timer Controller Register Field Descriptions Table Count Register Fields Descriptions Table Compare Register Fields Descriptions Table 11.1 Divisor Value Examples for Typical Baud Rates Table 11.2 UART Transmit and Receive Data Pins Table 11.3 UART0 Register Address Map Table 11.4 UART1 Register Address Map Table 11.5 Interrupt Enable Register (IER) Field Descriptions Table 11.6 Interrupt Identity Register Fields and Descriptions RC32134 User Reference Manual xiii May 4, 2001

16 List of Tables Table 11.7 Buffer Control Register (BCR) Field Descriptions Table 11.8 Line Control Register (LCR) Field Descriptions Table 11.9 MODEM Control Register (MCR) Field Descriptions Table Line Status Register (LSR) Field Descriptions Table MODEM Status Register (MSR) Field Descriptions Table Scratch Register Field Descriptions Table 12.1 JTAG Pin Descriptions Table 12.2 Instructions Supported By RC32134 s JTAG Boundary Scan RC32134 User Reference Manual xiv May 4, 2001

17 List of Figures Figure 1.1 RC32134 Block Diagram Figure 1.2 System Block Diagram Figure 1.3 Logic Diagram for RC Figure 2.1 IP Bus Bridge Block Diagram Figure 2.2 Subblock Ordered Data Retrieval Figure 2.3 Address Latch Time with Fast Decode Setting Figure 2.4 Address Latch Time with Slow Decode Setting Figure 2.5 RC32364 cpu_ad[31:0] Data Phase Figure 2.6 RC32134 Reset Vector Initialization Figure 2.7 Reset Behavior for cpu_int_n[3] z Figure 2.8 Bus Turnaround (BTA) Control Register Format Figure 2.9 Timing of Bus Turnaround Cycle(s) (example of 1 cycle BTA) Figure 2.10 Address Latch Timing Register Figure 2.11 Arbitration Register Field Figure 2.12 BusError Control Register Fields Figure 2.13 SysID Register Fields Figure 3.1 Block Diagram of RC32134 Memory Controller Figure 3.2 Subblock Ordered Burst Read Sequences Figure 3.3 Memory Base Address Register for Banks 1: Figure 3.4 Memory Bank Mask Register for Banks 1: Figure 3.5 Memory Control Register Channel 5: Figure 3.6 Single Word Memory Read Transaction Figure 3.7 Single Word Memory Read Transaction, with 1 wait-state Figure 3.8 Single Word Memory Write Transaction Figure 3.9 Quad Word Burst Read Memory Transaction Figure 3.10 Memory 4 Word Burst Write Figure 3.11 IOM 1 Word Single Read Figure 3.12 IOM 1 Word Single Write Figure 3.13 IOM 4 Word Burst Read Figure 3.14 IOM 4 Word Burst Write Figure 3.15 IOI 1 Word Single Read Figure 3.16 IOI 1 Word Single Write Figure 3.17 IOI 4 Word Burst Read Figure 3.18 IOI 4 Word Burst Write Figure 3.19 Dual-Port 1 Word Single Read Figure 3.20 Dual-Port 1 Word Single Read with 1 Wait-state Figure 3.21 Dual-Port 1 Word Single Write Figure 3.22 Dual-Port 4 Word Burst Read Figure 3.23 Dual-Port 4 Word Burst Write Figure 4.1 SDRAM Block Diagram Figure 4.2 Subblock Ordered Retrieval Method Figure 4.3 SDRAM Control Register Fields Figure 4.4 SDRAM Non-Page Burst Read Figure 4.5 SDRAM Non-Page Burst Write Figure 4.6 SDRAM Non-page Word Read Figure 4.7 SDRAM Non-page Word Write Figure 4.8 SDRAM Page-Hit Burst Read Figure 4.9 SDRAM Page-Hit Burst Write Figure 4.10 SDRAM Page-Hit Word Read RC32134 User Reference Manual xv May 4, 2001

18 List of Figures Figure 4.11 SDRAM Page-Hit Word Write Figure 4.12 SDRAM Page-Miss Burst Read Figure 4.13 SDRAM Page-Miss Word Read Figure 4.14 SDRAM Refresh Figure 5.1 Subblock Ordered Retrieval Method Figure 5.2 EDODRAM Control Register Fields Figure 5.3 Non-Page Word Read Figure 5.4 Non-Page Word Write Figure 5.5 Non-Page Burst Read Figure 5.6 Non-Page Burst Write Figure 5.7 Page-Hit Single Word Read Figure 5.8 Page-Hit Single Word Write Figure 5.9 Page-Hit Burst Write Figure 5.10 Page-Mode Burst Read Figure 5.11 Page-Miss Single Word Read Figure 5.12 Non-Staggered EDODRAM Refresh Figure 5.13 Staggered EDODRAM Refresh Figure 6.1 PCI Interface Controller Block Diagram Figure 6.2 PCI Controller Interrupt Pending Register 11 Fields Figure 6.3 CPU to PCI Mailbox Interrupt Pending Register 12 Fields Figure 6.4 PCI to CPU Mailbox Interrupt Pending Register 13 Fields Figure 6.5 PCI Arbitration Register Fields Figure 6.6 PCI Memory Space 1, 2, 3 or I/O Base Register Figure 6.7 PCI CPU Memory Space 1 Base Register or PCI CPU I/O Space Base Register Fields 6-9 Figure 6.8 PCI Configuration Address Register Fields Figure 6.9 PCI Configuration Data Register Field Figure 6.10 Vendor ID Register Figure 6.11 Device ID Register Figure 6.12 PCI Command Register Figure 6.13 PCI Status Register Figure 6.14 Configuration Device Revision Identification Register Figure 6.15 Class Code Register Figure 6.16 Cacheline Size Register Figure 6.17 Master Latency Timer Register Fields Figure 6.18 Header Type Register Field Figure 6.19 BIST Register Field Figure 6.20 Memory Base Address Register Figure 6.21 I/O Base Address Register Figure 6.22 Subsystem Vendor ID Register Figure 6.23 Subsystem ID Register Figure 6.24 Interrupt Line Register Figure 6.25 Interrupt Pin Register Figure 6.26 MIN_GNT Register Figure 6.27 MAX_LAT Register Figure 6.28 TRDY Timeout Value Register Figure 6.29 Retry Timeout Register Figure 7.1 Diagram of DMA General Block with IP Bus Interface Figure 7.2 Example of Endianness Swapping of Word Transfers Figure 7.3 Example of Endianness Swapping for Half-Word Transfer Figure 7.4 DMA Transfer Configuration Figure 7.5 Diagram Showing the Rotating Arbitration Scheme Figure 7.6 Configuration Register Fields Figure 7.7 Base Descriptor Address Register Field Figure 7.8 Next Descriptor Address Field Figure 7.9 Source Address Field RC32134 User Reference Manual xvi May 4, 2001

19 List of Figures Figure 7.10 Destination Address Fields Figure 7.11 Next Descriptor Address Field Figure 7.12 Status Register Fields Figure 7.13 Four Word SDRAM to SDRAM access by DMA Figure 8.1 Expansion Interrupt Controller Block Diagram Figure 8.2 Expansion Interrupt Block Diagram Group/Bit-Slice Figure 8.3 Interrupt Pending Register Fields Figure 8.4 Interrupt Mask Register Figure 8.5 Interrupt Clear Register Field Figure 8.6 PIO Input Asserting cpu_int_n[3] Figure 8.7 Internal Condition Asserting cpu_int_n[3] Interrupt Figure 8.8 Pending Register Write Asserting cpu_int_n[3] Figure 8.9 Pending or Clear Register Write De-Asserting cpu_int_n[3] Interrupt Figure 8.10 Internal Condition Asserting PCI Interrupt Figure 8.11 Pending or Clear Register Write De-Asserting PCI Interrupt Figure 9.1 PIO Block Diagram Figure 9.2 PIO Block Diagram Bit-Slice Figure 9.3 PIO Data Register 0 Fields Figure 9.4 PIO Direction Register 0 Field Figure 9.5 PIO Function Select Register 0 Fields Figure 9.6 PIO Input, Affecting Data Register Figure 9.7 Data Register Write, Affecting PIO Output Figure 10.1 Timer Block Diagram Figure 10.2 Diagram of Individual Timer Core Figure 10.3 Timer Control Register Fields Figure 10.4 Count Register Fields Figure 10.5 Compare Register Fields Figure 10.6 Timer Rollover Causing timer_tc_n to Toggle Figure 10.7 timer_gate_n Input Causing Timer to Count Figure 11.1 UART Block Diagram Figure 11.2 Interrupt Flow Figure 11.3 Receiver Buffer Register Figure 11.4 Transmitter Buffer Register Figure 11.5 Interrupt Enable Register Figure 11.6 Divisor Latch, LS Register Figure 11.7 Divisor Latch, MS Register Figure 11.8 Interrupt Identity Register Figure 11.9 Buffer Control Register (BCR)Fields Figure Line Control Register Fields Figure MODEM Control Register Fields Figure Line Status Register Fields Figure MODEM Status Register Fields Figure Scratch Register Fields Figure UART Timing Figure 12.1 Diagram of the JTAG Logic Figure 12.2 State Diagram of RC32134 s TAP Controller Figure 12.3 Diagram of Observe-only Input Cell Figure 12.4 Diagram of Output Cell Figure 12.5 Diagram of Output Enable Cell Figure 12.6 Diagram of Bidirectional Cell Figure 12.7 Device ID Instruction Format RC32134 User Reference Manual xvii May 4, 2001

20 List of Figures 79RC32134 User Reference Manual xviii May 4, 2001

21 Chapter 1 RC32134 Device Overview Introduction The RC32134 is a system controller chip that offers a direct connection to IDT s RC32364 CPU. The RC32134 provides the system logic for boot memory, main memory, IO, and PCI. The RC32134 also includes system logic for DMA, reset, interrupts, timers, and UARTs. Together, the RC32364 CPU and RC32134 System Controller form a complete hardware design core for embedded systems. The RC32134 integrates all of the peripherals commonly associated with an embedded system to reduce real estate consumption, design time, and effort. Block Diagram The RC32134 block diagram is shown in Figure 1.1. The sections that follow present an operational overview of the various peripheral interfaces and controller capabilities that comprise the RC32134 system. Also included in this chapter is a full pin description table and logic diagram. More detailed explanations and user details such as register descriptions, timing diagrams and memory maps are provided in the specific chapter for that function. Timer, UART, Interrupt Modules DMA Channels RC32134 CPU I/F PCI I/F and Bridge EDO/SDRAM Control Memory I/O Control Address bus SDRAM/EDODRAM Control Memory & I/O Control PCI Bus Figure 1.1 RC32134 Block Diagram Documentation Conventions and Definitions Note that throughout this manual the following terms and conventions will be used: To avoid confusion when dealing with a mixture of active-low and active-high signals, the terms assertion and negation are used. The term assert or assertion is used to indicate that a signal is active or true, independent of whether that level is represented by a high or low voltage. The term negate or negation is used to indicate that a signal is inactive or false. To define the active polarity of a signal, a suffix will be used. Signals ending with an _n should be interpreted as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level. To define buses, the most significant bit (MSB) will be on the left and least significant bit (LSB) will be on the right. No leading zeros will be included. To represent numerical values, either decimal, binary, or hexadecimal formats will be used. The binary format is as follows: 0bDDD, where D represents either 0 or 1; the hexadecimal format is as follows: 0xDD, where D represents the hexadecimal digit(s); otherwise, it is decimal. Unless otherwise denoted, a byte will refer to an 8-bit quantity. A halfword will refer to a 16-bit quan- 79RC32134 User Reference Manual 1-1 May 4, 2001

22 RC32134 Device Overview List of Features tity. A triple-byte will refer to a 24-bit quantity. A word will refer to a 32-bit quantity, and a double or double word will refer to a 64-bit quantity. A bit is set when its value is 0b1. A bit is cleared when its value is 0b0. The compressed notation ABC[x y z]d refers to ABCxD, ABCyD, and ABCzD. In words, bit 31 is always the most significant bit and bit 0 is the least significant bit. In halfwords, bit 15 is always the most significant bit and bit 0 is the least significant bit. In bytes, bit 7 is always the most significant bit and bit 0 is the least significant bit. The ordering of bytes within words is referred to as either big endian or little endian. Big endian systems label byte zero as the most significant (leftmost) byte of a word. Little endian systems label byte zero as the least significant (rightmost) byte of a word. bit 31 bit Address of Bytes within Words: Big Endian bit 31 bit Address of Bytes within Words: Little Endian Table 1.1 Example of Byte Ordering for "Big Endian" or "Little Endian" System Definition List of Features RC32300-family System Controller Direct connection between RC32364 and RC32134 Drives latched address bus to memory and peripherals Direct control of optional external data buffers Programmable system watch-dog timers Big or Little endian support Interrupt Control Provides services for internal and external sources Allows status of each interrupt to be read and masked Three general purpose 32-bit timer/counters Programmable IO (PIO) Input/Output/Interrupt source Individually programmable SDRAM/EDODRAM Controller (32-bit memory only) 4 banks, non-interleaved, 256 MB total Automatic refresh generation UART Interface Two Compatible UARTs Baud rate support up to 1.5M 8/16/32-bit boot PROM support Boundary Scan JTAG Interface (IEEE Std compatible) Memory & Peripheral Controller 6 banks, up to 32 or 64MB per bank (bank dependent) 8/16/ or 32-bit interface per bank Supports Flash ROM, SRAM, dual-port memory, and peripheral devices Intel or Motorola style IO supports external wait-state generation 79RC32134 User Reference Manual 1-2 May 4, 2001

23 RC32134 Device Overview System Block Diagram 4 DMA Channels 4 general purpose DMA, each with Endianness swappers and byte lane data alignment Any channel can be used for PCI Supports scatter/gather Supports memory-to-memory, memory-to-i/memory-to-pci, PCI-to-PCI, and I/O-to-I/O transfers Supports chaining via linked lists of records Supports unaligned transfers Supports burst transfers Programmable DMA transactions burst size PCI Bridge 32-bit PCI, up to 66 MHz Revision 2.1 compliant Target and master Host or satellite On-chip three slot PCI arbiter 3.3V operation with 5V compatible I/O 208 pin PQFP package System Block Diagram Figure 1.2 illustrates the typical system implementation, based on the RC32364 CPU and the RC32134 system controller. The RC32134 interfaces directly to the RC32364 and provides all of the necessary control and address signals to drive the external memory and I/O. Note that, depending on the loading of the CPU data bus, external data buffers could be used to reduce the loading and isolate different memory regions. As illustrated in the system block diagram, the external memory and I/O data path is external to the RC RC32364 Clock RC bit Data Bus CPU I/F Serial PIO Timers, UART, Interrupt Ctl DMA Channels DRAM Ctl Memory & I/O Ctl Address & Control SDRAM Memory & I/O PCI Bridge with Arbiter 32-bit 32-bit 32-bit,, 33MHz 33MHz PCI PCI Bus Bus System Overview Figure 1.2 System Block Diagram The RC32134 interfaces directly to the RC32364 s system bus. The RC32134 latches the address from the RC32364 internally and decodes it to detect which memory, I/O, or on-chip peripheral is being accessed, per the internal address map of the RC The RC32134 generates all necessary control signals and address buses to the external memory and I/O. For main memory, I/O, on-chip peripherals, registers, and PCI, the RC32134 divides the physical address space into 13 different regions. The data path from the external memory and peripherals (with the exception of PCI) is external to the RC The data path from the PCI bus and from the internal peripherals and registers is internal to the RC RC32134 User Reference Manual 1-3 May 4, 2001

24 RC32134 Device Overview System Overview Memory Controller. The Memory Controller on the RC32134 provides all of the address buses and control signals for interfacing the RC32364 CPU to standard SRAM, PROM, FLASH, and I/O, and includes the boot PROM interface. The memory controller provides six individual chip selects and supports 8,16, and 32-bit wide memory and I/Os. The two chip selects have highly configurable memory address ranges, allowing selection of various memory types and widths to be supported. The RC32134 provides controls for optional external data transceivers, for systems that require fast signalling with large loads. SDRAM Controller. The SDRAM optimization provides higher throughput while using available DRAM circuitry, adding little to the cost of the system. The SDRAM controller directly manages four banks of 32-bit physical non-interleaved memory. Each bank is 32-bits wide and supports a maximum of 64 MB per bank. Total memory support is 256 MB. The SDRAM controller has a built-in refresh generator. EDODRAM Controller. The RC32134 EDODRAM Controller supports up to 4 banks of non-interleaved 32-bit wide EDODRAMs. Most of the EDODRAM pins are shared with the SDRAM controller and, as such, the two operations can not be simultaneously enabled. Selection between SDRAM or EDODRAM is made at boot-time through system software operations. The EDO supports 256 MB total of EDODRAM. The EDO controller has a built in refresh generator. PCI Bridge. To transfer data between main memory and the PCI bus, the RC32134 incorporates a PCI bridge. At reset time, the PCI bridge can be configured as either a host or satellite bridge. The PCI bridge supports 32-bit PCI at up to 33MHz and is revision 2.1 compliant. As a PCI master, the RC32134 can generate memory, I/O, or configuration cycles for direct local-to-pci bus accesses. The PCI bridge incorporates a 3-slot PCI bus arbiter and includes both Fixed and Round Robin arbitration modes. As a PCI target, the RC32134 allows access to its internal registers and to the RISCore32300 local bus through the PCI, I/O read and write, or Memory read and write commands. The RC32134 PCI bridge supports swapping little endian data to big endian, when the CPU subsystem is configured as a big endian system. DMA Controller. Four general purpose DMA channels move data between source and destination ports. Source and destination ports can be system memory, PCI, or I/O devices. Any of the four channels can be used for PCI initiator reads or writes. All four channels support a descriptor structure, to allow efficient data scatter/gather. The DMA controller supports swapping of data between big and little endian memory and I/O subsystems. It also supports quad-word burst transfers. All external 16 and 8-bit memory I/ Os are treated as memory-mapped, word-aligned devices. Expansion Interrupt Controller. The Expansion Interrupt Controller provides the interrupt logic for software to analyze the various RC32134 generated system interrupts and adds to the control already provided through the CP0 registers of the RC Each system interrupt is registered and the pending status provided through this feature. The pending status can then be used to automatically generate a hardware interrupt to the CPU via individual mask bits. The pending interrupt status can also be optionally set or cleared by a direct software write. PIO. Programmable I/O (PIO) pins are provided on the RC32134 so that any unused peripheral pins can be programmed for use as general purpose discrete I/O pins. These PIO pins can be software programmed as bidirectional lines, allowing pin values to be software programmed in output mode and software readable while in the input mode. The PIO pins can also be used as a source of interrupts to the CPU. Maximum Interfacing flexibility is thus provided without requiring extensive modifications to the board. UART. The RC32134 incorporates two (an enhanced version of the 16450) compatible UARTs. To relieve the CPU of software overhead, the UART can be put into FIFO mode, allowing execution of either or compatible software. Two sets of 16-byte FIFOs are enabled during the mode: one set in the receive data path and one set in the transmit data path. A baud rate generator is included that divides the system clock by 1 to 64K and provides a 16X clock for driving the transmitter and receiver logic. 79RC32134 User Reference Manual 1-4 May 4, 2001

25 RC32134 Device Overview Pin Descriptions Timers/Counters. Three on-chip 32-bit general purpose Timers are provided on the RC Each timer consists of both a count and a compare register. The count register resets to zero and then counts upward until it equals the compare register. When the count and compare registers are equal, the TC_n output is asserted and the count is then reset to zero. JTAG. Board-level manufacturing debugging is facilitated through implementation of a fully compliant IEEE std JTAG Boundary Scan interface. Pin Descriptions The following is a list of interface, interrupt, and miscellaneous pins that are available on the RC Note that several of these pins are multiplexed and have been assigned alternate functions. Pins with this characteristic have their alternate functions listed also in this table. Note that throughout this manual pin names followed by _n are active-low signals. Pin Name Type Alternate Signal(s) Description Local Memory and Peripheral Pins cpu_ad[31:0] I/O Not applicable CPU Address/Data Bus This is the RC32134 s primary multiplexed and bidirectional address and data bus. The RC32134 latches this bus internally and uses it to generate the necessary address lines to the external memory and peripherals. If the transaction is a write, the CPU then drives data on cpu_ad(31:0). During CPU generated transactions, the CPU drives Address(31:4) into the cpu_ad bus, during its address phase. During DMA generated transactions (or RC32134 internal register reads), the address phase is unused and the chip drives data during a write. cpu_addr[3:2] I Not applicable CPU LSB Address Bus During CPU generated transactions, the CPU drives Address(3:2) onto the cpu_addr bus. The RC32134 does not internally use the cpu_addr bus during the data phase. However, 8- or 16-bit memory or I/O systems must attach these two pins instead of mem_addr(3:2). cpu_ale I Not applicable CPU Address Latch Enable During CPU generated transactions, this signal indicates that the cpu_ad (31:0) is driving a valid address and can be latched internally by the RC cpu_cip_n I Not applicable CPU Cycle In Progress During CPU generated transactions, this active-low signal indicates that a bus transaction is active. An external pullup resistor is required. cpu_wr_n I Not applicable CPU Write Status During CPU generated transactions, this active-low signal indicates whether or not a write is occurring. If a write is not occurring, then the implication is that a read is in progress. Table 1.2 RC32134 Pin Descriptions (Part 1 of 11) 79RC32134 User Reference Manual 1-5 May 4, 2001

26 RC32134 Device Overview Pin Descriptions Pin Name Type Alternate Signal(s) Description cpu_be_n[3:0] I Not applicable CPU Byte Enable Bus During CPU generated transactions, these active-low signals indicate which byte lanes are in use. Note: The table below indicates which cpu_be_n signal corresponds to which byte lane, whether or not the system is in big or little endian mode cpu_be_n[0] 7:0 cpu_be_n[1] 15:8 cpu_ack_n O Not applicable CPU Acknowledge During CPU generated transactions, this active-low signal is generated by the RC32134 to indicate that the present data have been accepted. cpu_last_n I Not applicable CPU Last Data During CPU generated transactions, this active-low signal indicates during the data phase that the present data is the last data. cpu_buserr_n O Not applicable CPU Bus Error During both CPU and DMA generated transactions, this active-low signal indicates that a bus error has occurred. This signal can also be optionally attached to an interrupt line. cpu_masterclk I sdram_clk CPU Master System Clock Provides the basic system clock. This clock must be the same clock that is provided to the RC32364 and also, if used, to SDRAM. cpu_coldreset_n I Not applicable CPU Cold Reset This active-low signal is asserted to the RC32364 CPU and RC32134 after V cc becomes valid on the initial power-up. The Reset initialization vectors, for both the RC32364 and the RC32134, are latched by cold reset. cpu_reset_n O Not applicable CPU Warm Reset This active-low signal is a secondary reset signal asserted to the CPU at least 256 clocks after cold reset, allowing, for instance, stabilization of RC32364 s PLL. cpu_busreq_n O Not applicable CPU Bus Request This active-low signal requests the CPU bus from the RC32364, for instance, by RC32134 to perform a DMA operation. cpu_busgnt_n I Not applicable CPU Bus Grant This active-low signal is a CPU bus grant from the RC32364, indicating that the local CPU bus has been released to the RC Table 1.2 RC32134 Pin Descriptions (Part 2 of 11) Data Bits cpu_be_n[2] 23:16 cpu_be_n[3] 31:24 79RC32134 User Reference Manual 1-6 May 4, 2001

27 RC32134 Device Overview Pin Descriptions Pin Name Type Alternate Signal(s) Description cpu_int_n O interrupt_n CPU Interrupt This active-low signal is an interrupt indication to the CPU from RC32134 s Interrupt Controller. Note: This pin is typically hooked up to the CPU s interrupt 3. cpu_dt_r_n O mem_245_dt_r_n, sdram_245_dt_r_n, edodram_245_dt_r_n PCI Interface CPU Direction Transmit/Receive This active-low signal controls the DT/R pin of an optional FCT245 transceiver bank. It is asserted during DMA read operations. This signal is tri-stated during CPU accesses (when the CPU owns the bus) and driven during DMA generated accesses. Note: An external pull-up resistor is required. pci_ad[31:0] I/O Not applicable PCI Multiplexed Address/Data Bus This address is driven by the Bus Master during initial frame_n assertion. The Data is then driven by the Bus Master during writes; or the Data is driven by the Bus Slave during reads. pci_cbe_n[3:0] I/O Not applicable PCI Multiplexed Command/Byte Enable Bus The Command bus (active high) is driven by the Bus Master during the initial frame_n assertion. The Byte Enable bus (active low) is driven by the Bus Master during the data phase(s). Note: The table below indicates which cpu_be_n signal corresponds to which byte lane, whether or not the system is in big or little endian mode. pci_be[0] 7:0 pci_be[1] 15:8 pci_par I/O Not applicable PCI Parity This signal indicates even parity of the pci_ad[31:0] bus and is driven by the Bus Master during Address and Write Data phases. During the Read data phase, this signal is driven by the Bus Slave. pci_frame_n I/O Not applicable PCI Frame Negated This active-low signal is driven by the Bus Master and indicates the duration of a PCI transfer. Assertion indicates the beginning of a bus transaction. De-assertion indicates the last data. pci_trdy_n I/O Not applicable PCI Target Ready Negated This active-low signal is driven by the Bus Slave and indicates that the current data can complete (the bus slave can accept/drive data). pci_irdy_n I/O Not applicable PCI Initiator Ready Negated Driven by the Bus Master, this active-low signal indicates that the current data can complete (PCI initiator is ready to accept/drive data). Table 1.2 RC32134 Pin Descriptions (Part 3 of 11) Data Bits pci_be[2] 23:16 pci_be[3] 31:24 79RC32134 User Reference Manual 1-7 May 4, 2001