Computer Hardware and System Software Concepts

Transcription

1 Computer Hardware and System Software Concepts Introduction to Computer Architecture Welcome to this course on Computer Hardware and System Software Concepts 1

2 Course Objective To introduce fundamentals of Computer Architecture To introduce the concepts of System Software. To introduce the concepts of Operating Systems. To introduce the concepts of Computer Networks. 2 By the end of the course, you will have Knowledge of Computer Architecture Knowledge about different kinds of System Software viz., Compilers, Assemblers, Interpreters etc Knowledge about Operating System as a resource manager managing resources like memory, processors, peripherals and information Knowledge about Computer Networks NOTE: This course does not cover Technologies used to fabricate CPU, memory etc. Design and implementation of compilers, linkers, loaders etc. No particular OS whether at the command level or internals No particular protocol such as TCP/IP No day to day software Internet, Netscape etc. 2

3 References Andrew S. Tanenbaum: Structured Computer Organization, PHI, 3rd edition, Silberschatz and Galvin: Operating System Concepts, 4th edition, Addison-Wesley Pub, Andrew S. Tanenbaum: Computer Networks, PHI, Alfred V.Aho, Ravi Sethi, Jeffrey D.Ullman: Compilers - Principles, Techniques and Tools, Narosa Publishing House,

4 Session Plan Day 1 Create a background Main components of computer architecture Different addressing modes Day 2 Introduce System Software Introduce Operating Systems/Memory Management 4 Day 1 Day2 Create a background Just to warm up everybody, and avoid an abrupt start, we are going to set up a background. Here we will be discussing very trivial/obvious questions and answers. Main components of computer architecture To discuss about the following CPU Main Memory Input/Output Devices Bus Different Addressing modes To discuss about the following Implied Addressing Immediate Addressing Direct Addressing Relative Addressing Indexed Addressing Indirect Addressing Introduce System Software To discuss about the following Assemblers Loaders Linkers Compilers To introduce Operating Systems/Memory Management To discuss about the following Operating System Functions of Operating System Memory Management Memory Management Schemes 4

5 Session Plan Day 3 Introduce Process Management Introduce File Management Day 4 Introduce Device Management Introduce Computer Networks 5 Day 3 Day 4 To introduce Process Management To introduce File management. To introduce Device Management Introduction I/O channels, interrupts and interrupt handling Structure of an I/O system Allocation Policy Case Study: MS-DOS vs. Unix To introduce Computer Networks Computer Networks what and why Network Topology The OSI model: layered approach Communication methods: Circuit, Packet and Message Switching Important Routing Devices 5

6 Background What is a Computer? Is an electronic device used to Store Retrieve and, Process data. To process data a set of instructions need to be given to the computer. What is a Program? Is a set of instructions. 6 A Computer is a machine which solves problems for people written as programs. A Program is a sequence of statements/steps stating how to perform a task. For each step an arithmetic and logical operation is done. For each operation a different set of control signals is needed i.e. an instruction. An instruction can be machine language instructions or assembly language instructions or even high level language instructions. A hardware is something that is tangible. For e.g. CPU, Memory, I/O devices, Bus etc. A software is a collection of programs. Trigger the question to identify the differences between software, program, function/procedure etc. Software is mainly of two types system software and application software. Programs such as compilers, linkers, loaders, assemblers are known as system software. Application software provides a solution to user application by making use of system software. E.g. banking software, payroll software. A firmware is software embedded in hardware during manufacture. E.g. home appliances etc 6

7 Computer Architecture Is concerned with the structure and behavior of the computer as seen by the user/programmer. It includes attributes such as Instruction Formats Addressing Modes Instruction Sets I/O Mechanisms 7 Architecture refers to how various components in a computer are organised & the design aspect of a computer. Talk about the difference between computer architecture and organization. Computer Organization is how features are implemented, typically hidden from the programmer. E.g. control signals, interfaces, memory technology etc. It is basically concerned with the way the hardware components operate and the way they are connected together to form the computer system. An instruction consists of an opcode always, along with some additional information such as where the operands come from and where the final results go to etc. Thus, there can be zero, one, two or three addresses present. Different machines have different instruction formats. Addressing basically refers to the way in which the operands are specified in an instruction. There are different ways in which the bits of an address field can be interpreted to find the operand. Addressing modes refer to these different ways. 7

8 Computer Architecture Main components in a computer system Hardware Software Firmware 8 We are going to study the computer architecture. We are not going to open the system and show where the CPU is located where the main memory is fixed and how the I/O devices are connected. Rather, we will study what are the components of a computer, what are their characteristics and functions. 8

9 Organization of a simple computer Central Processing Unit (CPU) Main Memory Input / Output devices Bus 9 9

10 CPU (Processor) What is it? Brain of the computer Function Fetch instructions from memory Examine Execute Consists of 3 functional units Control Unit (CU) ALU Registers 10 CPU is the part of the computer that performs the bulk of the data processing operations. Its main function is to execute programs stored in the main memory by fetching the instructions, examining them and executing them. 10

11 CPU Functional Units CPU Control Unit ALU Registers Fetches Instructions from memory Interprets the instructions Performs arithmetic operations Performs Logical operations Very high speed memory units in the CPUfor storing very small amount of data. Examples Program Counter (PC) Instruction Register (IR) Memory Address Register (MAR) Memory Buffer Register (MBR) Accumulator (A) 11 11

12 Examples of CPU (Processor) Intel Processors Motorola Processors Pentium 12 12

13 Memory MEMORY Internal Main Cache Secondary Memory Memory Memory Memory RAM ROM Internal Cache External Cache 13 13

14 Memory Internal Memory In the form of Registers Registers are small memory units internally available within the CPU. Volatile/Non volatile Memory 14 14

15 Memory - Primary or main Memory Volatile/Non volatile Memory Main Memory Read Only Memory Random Access Memory 15 Read Only Memory is Non Volatile in nature RAM is Volatile 15

16 Memory - Cache Memory A memory placed between CPU and main memory Contains a copy of the portion of main memory Processor when needs some information first checks cache If not found in cache, the block of memory containing the needed information is moved to the cache CPU Cache Main Memory 16 16

17 Memory - Secondary memory devices Type Description Readable Writable Typical size Hard disk These are placed separately along with the CPU (in the cabinet) and are usually not portable. Yes Yes 40 GB 80 GB Floppy disk CD ROM CD Read/ Write The Floppy disks are portable. These come in smaller sizes compared to Hard Disk. Compact Disc, Read Only Memory (CD-ROMs) are portable. These are typically read-only, meaning they could be used only to read the contents. This is simillar to CD-ROMs except that it is also used to write the information on to the special CD-ROM which are of Read-Write type. Yes Yes 1.44 MB Yes No MB Yes Yes MB 17 17

18 Comparison of different types of memory Storage type Implementation Features Contents Example Typical Size Internal Memory Very high speed devices, located within CPU(chip); expensive, and volatile. Very costly, hence limited in capacity. Holds instructions under execution and associated data item. Registers, Internal Cache memory Registers will be few in number. The internal Cache could be 256 KB or 512 KB Primary Memory High speed devices (but slower than the internal CPU registers) located outside the CPU (on the motherboard), Less costlier compared to internal memory. Usually larger in capacity. Entire (almost) program contents being executed; holds small volume of data. RAM (volatile), ROM (Non volatile), External Cache Memory 256 MB 512 MB Secondary Memory Low speed, Nonvolatile, low cost. Huge in capacity. Programs not currently being executed; holds large volume of data Hard Disk, Compact Disks(CDs), Floppy disks 40GB 80 GB 18 18

19 Memory hierarchy 19 19

20 Bus Parallel wires that carry several bits at a time Carries instructions, data, addresses or commands Unidirectional or bi-directional Major Categories Data bus Address bus Control bus Bus width and Bus speed are the two major components for performance measure. 20 A bus is a ribbon like set of parallel wires that can carry several bits at the same time. Data Bus: This transfers the data along both the directions. Hence, known as a bi-directional bus. Address Bus: This carries the address of the memory location which carries the program. Hence, known as a uni-directional bus. Control Bus: This transfers the control signals like READ, WRITE necessary to fetch and execute any program. Bus Width and Speed The size of a bus, known as the Bus width is important because it determines how much data can be transmitted at one instance of time transferred at once. For example, a 16-bit bus can transmit 16 bits of data, whereas a 32-bit bus can transmit 32 bits of data. This is analogous to the broadness of the road which decides how many vehicles could be allowed on it at a the same time. Every bus has its own speed with which it can transfer information and is measured in terms of MHz. A faster bus allows data to be transferred faster, which makes the application in turn run faster. Hertz (Hz) is a unit of frequency measure. 20

21 Different types of registers Categories:- General Purpose Registers are those which are used by the programmer to store data. all CPUs will have one register called Accumulator. Special Purpose Registers The special purpose registers are used by the CPU for temporary storage of data for calculations and other purposes. Ex.: MAR MBR IR PC 21 21

22 Registers, CPU and the memory 22 22

23 Harvard Architecture - Data & program stored separately. The Advantages of this architecture is the clear separation of the data region and the code region. Also the separate data and program busses are used, hence speeding up the process. Disadvantages could be the separate mechanisms to fetch data and the programs

24 Von Neumann architecture Data & Program, both stored in the same place. The Advantages of this architecture is that it treats data and programs alike meaning the same mechanisms to fetch data and the programs. The disadvantage is the same bus used for both program as well the data leads to so called Von Neumann bottleneck. 24 John Von Neumann proposed that the instruction and the data could be placed in the same physical memory. Until that point in time the data and the programs were placed in different physical memory locations. 24

25 Von Neumann architecture - characteristics One processor Use of stored programs Sequential processing of instructions Single Instruction, Single Data stream (SISD) mode 25 Even in Harvard, the instructions were sequentially processed and the SISD was followed with only one processor. The difference was only with the stored program concept. 25

26 Execution of the Instructions The execution process of the instruction stored in the memory happens in three phases. Fetch Phase: In this phase the instructions retrieved picked from the memory. Decode Phase: Once the instructions are retrieved these are decoded by the CU. Execute Phase: Once the instructions are decoded, they are executed by the ALU (in case they are Arithmetic instructions). 26 The execution process of the instruction stored in the memory happens in three phases. Fetch Phase: In this phase the instructions retrieved picked from the memory. Decode Phase: Once the instructions are retrieved these are decoded by the CU. Execute Phase: Once the instructions are decoded, they are executed by the ALU. 26

27 Fetch-decode-execute cycle 27 Fetch Phase The CU is responsible for the execution of this phase. 1.The contents of PC are transferred to Memory MAR 2.The content of the Main Memory as pointed by the MAR is accessed through the Address Bus 3.The current instruction is fetched into MBR. These contents flow through the Data Bus 4.The instruction is then transferred from MBR to IR Decode Phase The Instruction decoder unit in the CU is responsible for the execution of this phase 5.The opcode part of the instruction is transferred to the Instruction Decoder 6.The Instruction Decoder then decodes the opcode part (ADD), interprets and understands what to do (In this case the Adder in ALU is invoked) 7.The PC is then incremented to point to the next instruction 27

28 Fetch-decode-execute cycle Fetch Phase Decode Phase Execute Phase 28 The fetch-decode-execute cycle are explained in the next slides. 28

29 Fetch phase Contents of PC are transferred to MAR Main memory is accessed and current instruction is fetched into MBR Instruction is transferred from MBR to IR 29 29

30 Decode phase Opcode of the instruction is decoded Contents of PC are incremented by 1(in case of 1 byte instruction or equal to the no. of bytes of the instruction currently being executed.) Execution phase follows ( specific to the given instruction ) 30 The opcode of the instruction is decoded by the decoder At the same time, the PC is incremented by 1 to prepare it for fetching the next instruction. 30

31 Execute phase Execute the instruction Store the results in the proper place (go to the fetch phase to begin executing the next instruction) 31 The instruction is executed and the results are stored in the required register and the control goes back to the fetch cycle again. 31

32 Fetch-decode-execute cycle-example 2 32 Fetch Phase 1. The PC value is copied into MAR 2. The CU then refers to the Memory pointed to by the MAR 3. The Instruction is fetched into the MBR 4. The entries in MBR are transferred to the IR Decode Phase The Instruction decoder unit in the Control unit is responsible for the execution of this phase. 5. The opcode part of the instruction is transferred to the Instruction Decoder 6. The Instruction Decoder then decodes the opcode part (ADD), interprets and understands what to do (In this case the adder in ALU is invoked) 7. The PC is incremented to point to the next consecutive instruction 32

33 Instruction categories Arithmetic Instructions Ex.: Add, Sub, Mul etc. Logical instructions Instructions doing comparison operations. Program Control instructions Ex.: Jump to some memory location where the code is place & return etc. I/O instructions Ex.: In, Out Data Transfer instructions Register-Memory / Memory-Register Register-Register Memory-Memory. 33 Arithmetic instructions operate on numerical data. For e.g. addition, subtraction etc. Logical instructions perform boolean operations. For e.g. <, > etc. Program Control instructions are those instructions which change the sequence of execution. For e.g. jump, procedure call and return etc. I/O instructions are those instructions which are responsible for transfer of information between CPU or memory to and from I/O devices. Data Transfer instructions perform operations involving register and memory viz., Register-Memory/Memory-Register: allows memory words to be fetched into registers where they can be used as ALU inputs for subsequent instructions and vice-versa to store the register contents into the main memory. Register Register: fetches two operands from the registers, brings them to the ALU input registers and performs some operation on them. Memory - Memory: This happens in two stages. A memory to register data transfer and register to memory data transfer. This mode of data transfer fetches its operands from memory into the ALU input registers, performs the operations and writes the data back into the memory. 33

34 Instruction categories (Cont ) Data Transfer instructions Register-Memory / Memory-Register Register-Register Memory-Memory. Memory to memory Memory 34 34

35 Variations of CPU Architecture SISD SIMD MIMD MISD 35 The Von Neumann architecture consists of one ALU and one CU in the CPU. Since there is only one CU in the instructions can be executed sequentially one after another. Similarly only one set of data can be executed with one ALU. For example consider an instruction ADD R1, R2. Here the instruction to be decoded is ADD and the set of data to be operated on is R1 and R2. This type of architecture is also called as the Single Instruction Single Data (SISD). The next possibility is to have multiple ALUs in a CPU. This is useful in case of the same instruction operating on different set of data. For example ADD R1, R2 could be one instruction. The next instruction in the same program could be ADD R3, R4. Both the instructions do Addition of two different set of data. But the fact that the same operation is done on both the set of data prevents the CPU from separately decoding the instruction and hence saving the time involved in decoding the instructions. Also these two computations can be done simultaneously using two different ALUs. This architecture, where there are multiple ALUs and one CU is called as the Single Instruction Multiple Data (SIMD). Another variation is to have multiple ALUs and multiple CUs. This helps in decoding different instructions simultaneously and operate on multiple set of data at the same time. For example the two instructions ADD R1, R2 and MUL R3, R4 can both be simultaneously executed in case we have two sets of ALUs and CUs. This architecture is called as Multiple Instructions Multiple Data (MIMD). This architecture is also called as the Multi Processor architecture. A last variation is that of having multiple CUs but only one ALU. This is called as Multiple Instructions Single Data (MISD). This architecture is very rarely implemented because of its limited usage. 35

36 I/O devices Why needed? O/P Devices: Monitor Printer 36 Most of the computations involve CPU and memory. However, other components are required to feed information for computation and these components are known as I/O devices. The purpose of the I/O devices is to transfer information between CPU and the outside world. 36

37 I/O devices Input Devices:- Mouse Keyboard 37 37

38 I/O devices Input/Output Devices 38 38

39 Measures of CPU performance MIPS - is a measure of the speed of the processor. Clock Speed is another metric used to measure performance. FLOPS is a measure of the speed of the Floating Point Unit (FPU) which is a co-processor unit. 39 MIPS (Millions Instructions Per Second) is a measure of the speed of the processor. The time taken for executing different instructions is not the same. Hence, a mix of different instructions are taken to find out how many instructions on an average a computer can execute in a second. Clock Speed is another metric used to measure performance. A particular instruction always takes an exact number of clock pulses to complete. But the number of clock pulses differ across different instructions. The clock speed is measured in MHz which gives an indication of how fast a program runs. FLOPS( Floating Point Operations Per Second) is a measure of the speed of the Floating Point Unit (FPU) which is a co-processor unit. It is similar to MIPS except that the former is for non-floating operations where as this is for floating point operations. 39

40 Addressing A way of accessing memory locations which contain the data for processing Modes of addressing Implied Addressing Immediate Addressing Direct or Absolute Addressing Relative Addressing Indirect addressing 40 Addressing can also be defined as the way in which the operand is specified in an instruction. A number of strategies have been developed and implemented for determining a specific memory location. Based on the different strategies, there are different addressing modes as mentioned in the slide above. 40

41 Implied Addressing Operands are specified implicitly in the definition of the instruction Instruction specifies a fixed and unvarying address Example:- DEC (Decrement A register) 1. The CU decodes the instruction (fetch and decode phase) 2. The CU then fetches the contents of the register A 3. The value of the A will be transferred to the ALU 4. The ALU then decrements this value and updates the register A 41 41

42 Immediate addressing In it, data is a part of instruction itself. Example:- MOVE #100H, R1 Here the data 100h is moved to R1. The following steps are involved in the execution of this instruction. The CU decodes the instruction (fetch and decode phase) The data 100H available with the instruction is sent to Register R1. Control Unit R1 2 1 MOVE #100H R1 42 Here, data is a part of the instruction. MVI A, 01 MVI stands for Move Immediate. This basically implies move 01 to A. 42

43 Direct (Absolute ) addressing The address where data is available is part of the instruction Ex.: MOVE 30A4, R1 Control Unit R1 3 30A MOVE 30A4H R Steps involved in the execution of above instruction:- The CU decodes the instruction (fetch and decode phase) The memory location 50A4 is accessed The data from this location is copied onto Register R1. 43

44 Problem with Direct Addressing 44 44

45 Indirect Addressing Problem of direct addressing :the change in the location of the program is associated with the change in all absolute memory references. Solution : is to represent the address of the data indirectly. There are two ways to do it: 1) Register Indirect Addressing : the address of the data is stored in a Register. 2) Memory Indirect Addressing : the address of the data is stored in another memory location 45 45

46 1) Register Indirect Addressing : Ex.: MOVE [R2], R1 Memory Control Unit 2 R A MOVE [R2] R1 R1 The register R2 is assumed to be pre- loaded with a value of 30A4 46 A notation of enclosing the operand in Square brackets is used to denote that the register holds the address of the operand. In the above example R2 is put in a square bracket, meaning contents of register R2 is the address of the data location in memory. The register R2 is assumed to be loaded with a value of 30A4 (address of the operand). (Refer to Figure 1-18 ). The CU first fetches the instruction from the memory, decodes the instruction and then comes to the point of fetching the operands from the memory. The following steps are followed by the Control Unit to fetch the contents of source operand and load it into destination operand The CU fetches the instruction and decodes it. The content of the R2 is first fetched (in this example it is 30A4) The memory location pointed to by 30A4 (content of R2) is referred for getting the data at that memory location Finally the content of 30A4 (=75) is fetched and loaded into R1 46

47 1) Memory Indirect Addressing : Ex: MOVE [ 7010 ], R

48 Problems with Indirect Addressing 48 The problems with the relocation of the memory are not completely solved even with indirect addressing. This is because of the fact that the relocation of the program still requires the changes in the contents of the registers or the memory locations holding the absolute addresses. Assume the program begins at a location In the program a data is fetched from within the program s memory location which is at 30A4. If for some reason the program is shifted to a location 3000,then the data is also moved accordingly to 50A4. But the instruction (MOVE [R2], R1) is still referring to the data present at location 30A4 (because the R2 is loaded with 30A4). This drawback can be solved by using the relative addressing. One could have just mentioned the relative location of the data (= 20A4) from the start of the program and then added this starting address to the relative address to get the actual address of the data location. This technique is used in the Base Index addressing and is explained subsequent slides. 48

49 Base - Indexed Addressing Ex.: MOVE [BX] + [Ri], R Memory ADDER (ALU) A4 Base Register (BX) 1 Index Register Ri 2 20A4 50A4 75 MOVE [BX] [Ri] R1 hold the Base value of the program. holds the Offset (relative) address. 75 R In the running example instead of using the direct addressing, the relative location of the data could be mentioned (20A4) instead of the direct 30A4. This Base value is then added to the relative address (which could be 1000 in the first case and 3000 in the second case when the program is pushed) Consider an instruction MOVE [BX] + [Ri], R1. Here BX is considered to be a register used to hold the Base value of the program. Ri is a register which holds the Offset (relative) address. The steps followed are as follows (Refer Figure 1-21): The contents of the Base register BX is fetched The contents of the Index register is also fetched The value of the Base and the Index registers are added to get the effective address The memory location pointed to by this effective address is accessed The data from this location is fetched into the destination (register R1) This concept of the Base Index addressing can be best used in Arrays (set of data). Here any component in the array can be accessed by knowing the address of the base and then by adding the Index to this base to get the actual address of the data. 49

50 Problem with usage of shared memory 50 So far in the example programs considered, the data and the code were being placed in the same area. If a program has to be relocated to some other place in the memory then care should be taken to see that the data used by the program is not overwritten by the relocated program. This problem is illustrated in above Figure. 50

51 Segment Register Addressing 51 The above problem can be rectified by dividing the entire memory into smaller parts called segments. This mechanism of dividing the memory into segments is called segmentation. Typically there exist several segments like the code segment which is used to store the instructions, the data segment which is used to store the data etc. Usually the starting address of the segment is kept in the segment registers. Now for addressing any location in the memory one needs to add the segment register value to the base and Index register values. 51

52 Segment Register Addressing Memory Segment1 (code) ADDER (ALU) Segment2 (Data) Segment Register (SR) Base Register (BX) 1 Index Register Ri Segment3 MOVE [SR] [BX] [Ri] R R

53 Summary Background Components of a computer system Von Neumann architecture Fetch Decode Execute Cycle Memory I/O devices Bus Addressing Modes 53 53

54 Thank You! 54 54