Introduction to Graphical Programming for FPGAs

Transcription

1 Introduction to Graphical Programming for FPGAs Ian Bell National Instruments UK

2 The Long Tail of Embedded Large teams, influenced heavily by component costs Small teams, influenced heavily by development time/cost

3 The Long Tail of Embedded Innovation in Embedded Control & Monitoring

4 Embedded Monitoring Jet Plume Testing AFRL

5 Advanced Data Acquisition ISIS Proton Synchrotron

6 Fuel Cell Engine Control Ford Motor Company

7 Biomedical Device KC BioMedix

8 Test Measurement Industrial Embedded Prototyping

9 Software-Defined Hardware

10 Software-Defined Hardware

11 Software-Defined Hardware = FPGA Software Programmable (and Reconfigurable) Hardware Reliable (and Repeatable) High-speed Signal Processing (and Parallel Processing) Extreme Determinism (and clock-cycle control)

12 If FPGAs are so great - why doesn t everyone use them? Traditional Approach = not so easy

13 Traditional Approach Hardware Custom Hardware Embedded Expertise Analog Expertise System Integrator Programming Hardware Description Fixed point math Single Point processing Simulation

14 A Vision for Simplifying FPGA in order to allow any engineer or scientist to use FPGAs Hardware Configurable Custom Hardware and Modular Embedded off-the-shelf Expertise Analog Hardware Expertise System Integrator Software Graphical Hardware Description System Fixed point math Design Platform Single Point processing Simulation

15 An Approach to unlocking FPGAs FPGA The FPGA by itself is not enough, because it needs I/O

16 An Approach for unlocking FPGAs FPGA Varied Modular I/O for any signal Only having I/O is not enough, because it needs to communicate with the rest of the system

17 An Approach for unlocking FPGAs Host Processing Real-Time or PC- Based FPGA Varied Modular I/O for any signal This system represents a flexible hardware platform, but you need to design each part.

18 Validated Approach Major semiconductor companies are validating this approach with their latest offerings

19 RIO Architecture NI Approach for unlocking FPGAs Host Processing Real-Time or PC- Based FPGA Varied Modular I/O for any signal Highly-productive LabVIEW for Programming Host, FPGA, I/O, and bus interfaces. LabVIEW Graphical Programming

20 Why a graphical approach? FPGAs are dataflow systems FPGAs are parallel Graphical programming is an approachable way to program FPGAs for any engineer

21 FPGAs are Dataflow Systems E E F F Implementing Logic on FPGA: F = {(A+B)CD} E A B C D

22 FPGAs are Dataflow Systems E F Implementing Logic on FPGA: F = {(A+B)CD} E A B C D

23 FPGAs are Dataflow Systems LabVIEW FPGA Code Implementing Logic on FPGA: F = {(A+B)CD} E E F A B C D

24 FPGAs are Parallel Systems E F A B C D Z W X Y

25 FPGAs are Parallel Systems E F A B C D Z W X Y

26 Graphical Programming and Appropriate Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL 66 Pages ~4000 lines

27 Basics of LabVIEW Environment Project = System Configuration VI = program or function Front Panel = user interface Block Diagram = code

28 LabVIEW for FPGA Project = FPGA I/O Configuration VI = Hierarchical FPGA Design Front Panel = Interface Elements Block Diagram = Implementation

29 Graphical Version of the Entity/Architecture Pair entity LED_Toggle is Port ( CLK_50MHZ : in STD_LOGIC; LED : out STD_LOGIC); end LED_Toggle; architecture rtl of LED_Toggle is signal LED_local : std_logic; signal CounterValue : unsigned(31 downto 0); signal ToggleLED : boolean; constant kcountertc : unsigned(countervalue'range):= x"017d7840";

30 begin Blink an LED: hello world of hardware LED <= LED_local; process (CLK_50MHZ) begin if rising_edge(clk_50mhz) then if ToggleLED then LED_local <= not LED_local; end if; end if; end process; CounterProc: process (CLK_50MHZ) begin if rising_edge(clk_50mhz) then if CounterValue = kcountertc then CounterValue <= (others => '0'); ToggleLED <= true; else CounterValue <= CounterValue + 1; ToggleLED <= false; end if; end if; end process CounterProc; end rtl; VHDL Implementation Processes Physical wire connection to LED

31 begin Blink an LED: hello world of hardware LED <= LED_local; process (CLK_50MHZ) begin if rising_edge(clk_50mhz) then if ToggleLED then LED_local <= not LED_local; end if; end if; end process; CounterProc: process (CLK_50MHZ) begin if rising_edge(clk_50mhz) then if CounterValue = kcountertc then CounterValue <= (others => '0'); ToggleLED <= true; else CounterValue <= CounterValue + 1; ToggleLED <= false; end if; end if; end process CounterProc; end rtl; VHDL Implementation Processes Physical wire connection to LED Toggle the actual LED when interna signal ToggleLED is true. Execute every tick of the 50Mhz clock.

32 begin Blink an LED: hello world of hardware VHDL Implementation Processes LED <= LED_local; process (CLK_50MHZ) begin if rising_edge(clk_50mhz) then if ToggleLED then LED_local <= not LED_local; end if; end if; end process; Physical wire connection to LED Toggle the actual LED when interna signal ToggleLED is true. Execute every tick of the 50Mhz clock. CounterProc: process (CLK_50MHZ) begin if rising_edge(clk_50mhz) then if CounterValue = kcountertc then CounterValue <= (others => '0'); ToggleLED <= true; else CounterValue <= CounterValue + 1; ToggleLED <= false; end if; end if; end process CounterProc; Counter to establish the timing of ToggleLED signal. Goes true wh counter reaches 50,000,000 (1 sec resets counter. end rtl;

33 Blink an LED: hello world of hardware LabVIEW Implementation

34 Blink an LED: hello world of hardware LabVIEW Implementation LED I/O Resource

35 Blink an LED: hello world of hardware LabVIEW Implementation LED I/O Resource NOT (Toggle)

36 Blink an LED: hello world of hardware LabVIEW Implementation Loop Timing (1000ms) LED I/O Resource NOT (Toggle)

37 Graphical Programming for FPGAs Simplifying FPGA so any Scientist or Engineer can use them

38 Only if required Additional Slides

39 Simplified FPGA Design Flow Design Entry Simulation V&V Compilation On-Chip V&V

40 Simplified FPGA Design Flow Design Entry Cycle-by-Cycle G Software-like G HDL/IP Integration Configuration-based Interface Abstraction Hierarchical Simulation V&V Compilation Stop D Q En On-Chip V&V Clock

41 Simplified FPGA Design Flow Design Entry Software-like G Cycle-by-Cycle G HDL/IP Integration Configuration-based Interface Abstraction Hierarchical Simulation V&V Interactive Window Debugging Functional Simulation Cycle-Accurate Simulation Export Compilation On-Chip V&V

42 Simplified FPGA Design Flow Design Entry Software-like G Cycle-by-Cycle G HDL/IP Integration Configuration-based Interface Abstraction Hierarchical Simulation V&V Interactive Window Debugging Functional Simulation Cycle-Accurate Simulation Export Compilation One-click automation of the Xilinx Tools Local Computer, Server, or Cloud Compilation On-Chip V&V

43 Simplified FPGA Design Flow Design Entry Software-like G Cycle-by-Cycle G HDL/IP Integration Configuration-based Interface Abstraction Hiearchical Simulation V&V Interactive Window Debugging Functional Simulation Cycle-Accurate Simulation Export Compilation One-click automation of the Xilinx Tools Local Computer, Server, or Cloud Compilation On-Chip V&V Xilinx Chip Scope Instrumentation

44 High-Level FPGA Applications Digital Protocols and Communication Busses High-Speed or Precision Control Automated Test Custom Data Acquisition Fast Stimulus/Response Testing Signal Processing (DSP) Filtering/Transforms Certified Reliability Applications Medical, Mil/Aero RF & Wireless Modulation/Downconversion/Encoding HIL Simulation Sensors and systems Off-Loading or In-Line processing

45 Example: NI CompactRIO Host Processing Real-Time FPGA Varied Modular I/O for any signal Highly-productive LabVIEW for Programming Host, FPGA, I/O, and bus interfaces.

46 Example: NI FlexRIO & MultifunctionRIO Host Processing Real-Time or PC FPGA Varied Modular I/O for any signal Highly-productive LabVIEW for Programming Host, FPGA, I/O, and bus interfaces.

47 Example: NI Single-Board RIO FPGA Host Processing Real-Time or PC Varied Modular I/O for any signal Highly-productive LabVIEW for Programming Host, FPGA, I/O, and bus interfaces.