FPGA Schematic Design Step Guide

Transcription

1 FPGA Schematic Design Step Guide Schematic design is a powerful design method to help illustrate your design hierarchy and signal interconnect. The isplever 5.1 software supports schematic/vhdl and schematic/verilog HDL entries for FPGAs, including LatticeECP/EC, LatticeXP, LatticeSC, and MachXO device families. Note In FPGA schematic designs, the lowest-level sources must be VHDL or Verilog modules. Schematic Design Tools The Lattice Schematic Editor, Symbol Editor, and Library Manager allow you to capture your design with a combination of schematics, FPGA library macros, or HDL modules. Hierarchy is established by instantiating a symbol from a customer symbol produced by the IPexpress or your own RTL module. The following lists the major schematic tools included in isplever. Schematic Editor a graphical editor for placing library symbols, adding attributes, and wiring connections Symbol Editor a graphical editor for creating and modifying library symbols Library Manager a graphical interface to collect library symbols Hierarchy Navigator a graphical tool to explore schematic/hdl design hierarchy Design Steps This section shows the major design steps that are specific for an FPGA schematic design. Steps are as follows: Create a new project. First you need to create a new FPGA design project and select schematic/vhdl or schematic/verilog as your design entry type. Create a schematic symbol from the IPexpress or an HDL module. A schematic is mainly comprised of symbols, wires, and attributes. In this step, you ll learn how to create a symbol (*.sym) from the IPexpress or from an existing Verilog or VHDL module. These symbols can later be added to your schematic design source. Instantiate design modules. In this step, you ll add the schematic symbols you created in the prior step into a schematic (*.sch) and then add necessary wires, I/O makers, etc. to complete the schematic. isplever 5.1 Documentation 1

2 Edit net attributes. After finishing the schematic, you can apply net attributes. Net attributes include IO configuration and pin lock attributes. You can apply them to a net from or to the external signals. Create an HDL template from a schematic symbol. You can use the Symbol Editor to create a Verilog or VHDL template from a schematic symbol. These templates can later be imported into the project as the lower-level sources. Create an HDL simulation model from a schematic. You can create a Verilog or VHDL simulation model from a schematic file (*.sch) depending on your design source type. The model will be used to perform functional simulation on the schematic design project. Simulate a Schematic. This step shows you how to perform functional and timing simulation on your FPGA schematic design. Create a New Project Using the Project Navigator s Project Wizard, you can create a new schematic design targeting an FPGA device. The Wizard will guide you through the steps of specifying project name and location, choosing design entry type and synthesis tool, as well as selecting a target device. To create a new project: 1. In the Project Navigator, choose File > New Project. 2. In the first dialog of Project Wizard, do the following: Under Project Name, enter a name for your project. The default project name is Untitled. Under Location, click... to open the Browse for Folder dialog box. Browse for the desired location, or click New Folder to create a new directory to place the new project, and then click OK. Note that you should not place more than one project in the same directory. Under Design Entry Type, select Schematic/VHDL or Schematic/ Verilog HDL. Under Synthesis Tools, choose a synthesis tool. Click Next. 3. In the Select Device dialog box, select the desired FPGA device family and a specific device within that family. Then choose the options you want for that device. When you finish, click Next. 4. In the Add Source dialog box, click Next. You can add design sources later. 5. In the Project Information dialog box, make sure the project settings are correct and then click Finish. The new FPGA schematic design project is created and displayed in the Project Navigator. isplever 5.1 Documentation 2

3 Create a Schematic Symbol from the IPexpress or an HDL Module Schematic symbols (*.sym) are generally created from the IPexpress or from an existing HDL module. To create a schematic symbol from the IPexpress: 1. Run the IPexpress and configure the module or IP core. 2. In the configuration tab, click Generate. The IPexpress writes a new schematic symbol file (*.sym) into your project directory using the interface ports defined by your module. To create a schematic symbol from an existing HDL module: 1. In the Project Navigator, add the HDL module to your Schematic/VHDL or Schematic/Verilog project. 2. In the Sources window, select the HDL source. In the Processes window, double-click Generate Schematic Symbol. The Project Navigator writes a new schematic symbol file (*.sym) into the project directory using the interface ports defined by your HDL module. Note that if you prefer to use the Parameter Configuration File (*.lpc) as the source in your project, you may add the related HDL file temporarily to your project to create a schematic symbol. Once a symbol is created, you can modify it in the Symbol Editor. Instantiate Design Modules You can insert the symbol you created into a schematic (*.sch). To add a symbol to a schematic: 1. If you have not already done so, open or create a schematic file (*.sch). 2. In the Schematic Editor, press F2 or choose Add > Symbol to open the Symbol Libraries dialog box. The Library box displays all the available symbol library paths. The symbols you created for the project are stored in the [Local] path. 3. In the Library box, select the desired path. In the Symbol box, select the symbol you wan to add to your schematic. The symbol is attached to your mouse cursor. 4. Click the left mouse button to drop the symbol to the desired location in your schematic. You can continue to place the same symbol by clicking the left mouse button, or select a new symbol to add. When you finish, close the Symbol Libraries dialog box. After placing the symbols, you can add necessary wires and I/O markers to complete the schematic. isplever 5.1 Documentation 3

4 Set a User Symbol Library As mentioned in the above procedure, the symbols you created for the project are by default stored in the [Local] path. You can also set a user symbol library (*.lib) to store the user symbols that are commonly used. Then, when you want to insert symbols to a schematic, you can select your user library and add the symbols within it to your schematic. To set a user symbol library: 1. In the Project Navigator, choose Window > Library Manager. 2. In the Library Manager, choose File > New to create a new library file (*.lib) 3. Choose Edit > Add Symbol(s). 4. In the Add Symbols to Library dialog box, browse for the symbol (*.sym) you want to add to the user library, and then select it. You can select more than one symbol at a time by using the SHIFT and CTRL keys on your keyboard. 5. Click Open. The Library Manager copies the symbol(s) into the current library. The original symbols still exist and may be deleted if so desired. 6. Choose File > Save As to save the new library with a specific name. 7. In the Project Navigator, choose Options > User Defined Symbol Libraries Configuration. 8. In the dialog box, click the New icon. A new line is displayed in the list box. 9. Click the... button to the right of the new line to open the Select User Defined Symbol Library dialog box. Navigate to the user library you just created, and then click Open. 10. Click OK to close the Set User Defined Symbol Libraries dialog box. Now you have completed setting your user library. Next time when you open the Schematic Editor and choose Add > Symbol, you ll see your user library listed in the Symbol Libraries dialog box. You can select the user library and then choose any symbol included in the library to add to your schematic. Edit Net Attributes After completing your schematic file (*.sch), you can set IO configuration and pin lock attributes for the net from or to the external signals. To add a net attribute to a schematic: 1. In the Schematic Editor, make sure the schematic file you want to work with is open. 2. Choose Edit > Attribute > Net Attribute to open the Net Attribute Editor dialog box. 3. On the schematic, select the net you want to add attribute for. The net name and default net attributes for Lattice FPGA design appear in the dialog box. isplever 5.1 Documentation 4

5 4. To assign a device pin to the selected net, select LOC= in the dialog box, type in the desired pin name in the text box, and press Enter. The net is locked to the pin. To apply a certain IO configuration to the selected net, select the desired attribute, type in the value, and press Enter. The new attribute value is applied. 5. You can continue to edit net attributes the same way. When you finish, close the Net Attribute Editor dialog box. Create an HDL Template from a Schematic Symbol You can use the Symbol Editor to create a Verilog HDL or VHDL template from a schematic symbol. To create a Verilog or VHDL template from the Symbol Editor: 1. In the Symbol Editor, choose File > VHDL Template or Verilog Template. 2. In the Select File dialog box, browse for the symbol instance for which you want to create a template, and then click Open. Note If a symbol is open in the Symbol Editor, the Select File dialog box won t appear. The Symbol Editor will create an HDL template from the current symbol. The software creates the required template in the directory of the current project (the project currently opened in the Project Navigator). A Notice will tell you that the template has been generated. Create an HDL Simulation Model from a Schematic You can create a Verilog or VHDL simulation model from a schematic file (*.sch) based on the source type of your design. If you have a schematic/ VHDL design, you can create a VHDL simulation model. If your design type is schematic/verilog, you create a Verilog simulation model. The model is used to perform functional simulation on the schematic. To create a Verilog or VHDL simulation model from a schematic: 1. In the Project Navigator Sources window, select the schematic (*.sch) file. 2. In the Processes window, do either of the following: If your design type is schematic/verilog, double-click Verilog Functional Simulation Model. This process produces a Verilog HDL functional simulation model (<schematic>.v) file containing a Verilog module of the schematic design. If your design type is schematic/vhdl, double-click VHDL Functional Simulation Model. This process produces a VHDL functional simulation model (<schematic>.vhd) file containing a VHDL design module of the schematic design. The required model is created in the project directory. isplever 5.1 Documentation 5

6 Simulate a Schematic To simulate a project that uses schematic diagrams, first you need to generate an HDL test bench or test fixture, and then you can perform functional or timing simulation. To generate a Verilog test fixture or VHDL test bench: 1. In the Project Navigator Sources window, select the schematic (*.sch) file. 2. In the Processes window, do either of the following: If your design type is schematic/verilog, double-click the following processes. Verilog Test Fixture Template Produces a Verilog Template File (<schematic>.tft) with a complete model that instantiates the schematic module as a Verilog module. Verilog Test Fixture Declaration Produces a Verilog Test Fixture Declarations Include File (<schematic>.tfi) with the schematic module I/O and instance declarations. The TFI files are typically referenced by a test fixture using the include compiler directive. By using TFI file in your simulation test fixtures, you ensure that your design and your test fixtures stay synchronized. If your design type is schematic/vhdl, double-click VHDL Test Bench Template. This process produces a VHDL Template File (<schematic>.vht) with a complete model that instantiates the schematic module as a VHDL component. The related test fixture or test bench template file is created in the project directory. Note The Lattice edition of ModelSim does not support a mixture of VHDL and Verilog source files. In order to use the file as a test fixture or test bench in your design, you must edit it and change the file extension name. For Verilog test fixture file, change the extension to.v. For VHDL test bench file, change the extension to.vhd. Then you can import the file into your project and run functional or timing simulation. To perform functional or timing simulation for a schematic design project: 1. In the Project Navigator, import the VHDL test bench or Verilog test fixture depending on the design source type of your project. 2. In the Sources window, select the VHDL test bench or Verilog test fixture. The Processes window will display VHDL or Verilog Functional and Timing Simulation processes. 3. Double-click the desired process to run simulation. isplever 5.1 Documentation 6