MPQ4423A 3A, 36V, High-Efficiency, Synchronous, Step-Down Converter AEC-Q100 Qualified

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1 The Future of Analog IC Technology DESCRIPTION The MPQ4423A is a high-efficiency, synchronous, rectified, step-down, switch-mode converter with built-in power MOSFETs. It offers a very compact solution that achieves 3A of continuous output current with excellent load and line regulation over a wide input supply range. The MPQ4423A uses synchronous mode operation to achieve higher efficiency over the output current load range. Current-mode operation provides fast transient response and eases loop stabilization. Full protection features include over-current protection (OCP) and thermal shutdown. The MPQ4423A requires a minimal number of readily available, standard, external components and is available in a compact QFN-8 (3mmx3mm) package. MPQ4423A 3A, 36V, High-Efficiency, Synchronous, Step-Down Converter AEC-Q100 Qualified FEATURES Wide 4V to 36V Continuous Operating Input Range 85mΩ/55mΩ Low R DS(ON) Internal Power MOSFETs High-Efficiency Synchronous Mode Operation Default 410kHz Switching Frequency Synchronizes to a 200kHz to 2.2MHz External Clock High Duty Cycle for Automotive Cold Crank Forced CCM Mode Internal Soft Start Power Good Over-Current Protection (OCP) and Hiccup Thermal Shutdown Output Adjustable from 0.8V Available in a QFN-8 (3mmx3mm) Package Available in AEC-Q100 Grade 1 APPLICATIONS Automotive Industrial Control System Distributed Power Systems All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. MPS and The Future of Analog IC Technology are registered trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION MPQ4423A Rev

2 ORDERING INFORMATION Part Number* Package Top Marking MPQ4423AGQ QFN-8 (3mmx3mm) See Below MPQ4423AGQ-AEC1 QFN-8 (3mmx3mm) * For Tape & Reel, add suffix Z (e.g. MPQ4423AGQ Z) TOP MARKING APP: Product code of MPQ4423AGQ and MPQ4423AGQ-AEC1 Y: Year code LLL: Lot number PACKAGE REFERENCE TOP VIEW FB 1 8 PG VCC 2 7 IN EN/SYNC 3 6 SW BST 4 5 GND QFN-8 (3mmx3mm) MPQ4423A Rev

3 ABSOLUTE MAXIMUM RATINGS (1) V IN V to 40V V SW V to 41V V BS... V SW + 6V All other pins V to 6V (2) Continuous power dissipation (T A = +25 C) (3) QFN-8 (3mmx3mm) W Junction temperature C Lead temperature C Storage temperature C to 150 C Recommended Operating Conditions Continuous supply voltage (V IN )...4V to 36V Output voltage (V OUT )...0.8V to 0.9 x V IN Operating junction temp. (T J ) -40 C to +125 C Thermal Resistance (4) θ JA θ JC QFN-8 (3mmx3mm) C/W NOTES: 1) Absolute maximum ratings are rated under room temperature unless otherwise noted. Exceeding these ratings may damage the device. 2) For details on EN s ABS MAX rating, please refer to the Enable/SYNC Control section on page 14. 3) The maximum allowable power dissipation is a function of the maximum junction temperature T J (MAX), the junction-toambient thermal resistance θ JA, and the ambient temperature T A. The maximum allowable continuous power dissipation at any ambient temperature is calculated by P D (MAX) = (T J (MAX)-T A )/θ JA. Exceeding the maximum allowable power dissipation produces an excessive die temperature, causing the regulator to go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 4) Measured on JESD51-7, 4-layer PCB. MPQ4423A Rev

4 ELECTRICAL CHARACTERISTICS V IN = 12V, T J = -40 C to +125 C, unless otherwise noted. Typical values are at T J = +25 C. Parameter Symbol Condition Min Typ Max Units Supply current (shutdown) I SHDN V EN = 0V 8 μa Supply current (quiescent) I Q V EN = 2V, V FB = 1V, no switching ma HS switch on resistance R ON_HS V BST-SW = 5V mω LS switch on resistance R ON_LS V CC = 5V mω Switch leakage I LKG_SW V EN = 0V, V SW = 12V 1 μa Current limit I LIMIT Under 40% duty cycle A Oscillator frequency f SW V FB = 750mV khz Foldback frequency f FB V FB < 400mV khz Maximum duty cycle D MAX V FB = 750mV, 410kHz % Minimum on time (5) t ON_MIN 70 ns Sync frequency range f SYNC MHz Feedback voltage V FB T J = 25 C mv Feedback current I FB V FB = 820mV na EN rising threshold V EN_RISING V EN falling threshold V EN_FALLING V EN threshold hysteresis V EN_HYS 150 mv EN input current V IN under-voltage lockout threshold rising V IN under-voltage lockout threshold falling V IN under-voltage lockout threshold hysteresis I EN V EN = 2V 4 8 μa V EN = μa INUV RISING V INUV FALLING V INUV HYS 200 mv VCC regulator V CC I CC = 0mA V VCC load regulation I CC = 5mA % Soft-start period t SS V OUT from 10% to 90% ms Thermal shutdown (5) C Thermal hysteresis (5) 30 C PG rising threshold PG Vth_RISING as a percentage of V FB % PG falling threshold PG Vth_FALLING as a percentage of V FB % MPQ4423A Rev

5 ELECTRICAL CHARACTERISTICS (continued) V IN = 12V, T J = -40 C to +125 C, unless otherwise noted. Typical values are at T J = +25 C. Parameter Symbol Condition Min Typ Max Units PG threshold hysteresis PG Vth_HYS as a percentage of V FB 6 % PG rising delay PG Td_RISING μs PG falling delay PG Td_FALLING μs PG sink current capability V PG Sink 4mA V PG leakage current I LKG_PG na NOTE: 5) Derived from bench characterization. Not tested in production MPQ4423A Rev

6 TYPICAL CHARACTERISTICS RISING 3.4 RISING FALLING 3.3 FALLING MPQ4423A Rev

7 TYPICAL CHARACTERISTICS (continued) MPQ4423A Rev

8 TYPICAL PERFORMANCE CHARACTERISTICS V IN = 12V, V OUT = 3.3V, L = 10µH, R BST = 20Ω, T A = +25 C, unless otherwise noted. MPQ4423A Rev

9 TYPICAL PERFORMANCE CHARACTERISTICS (continued) V IN = 12V, V OUT = 3.3V, L = 10µH, R BST = 20Ω, T A = +25 C, unless otherwise noted. MPQ4423A Rev

10 TYPICAL PERFORMANCE CHARACTERISTICS (continued) V IN = 12V, V OUT = 3.3V, L = 10µH, R BST = 20Ω, T A = +25 C, unless otherwise noted. MPQ4423A Rev

11 TYPICAL PERFORMANCE CHARACTERISTICS (continued) V IN = 12V, V OUT = 3.3V, L = 10µH, R BST = 20Ω, T A = +25 C, unless otherwise noted. V IN 5V/div. V IN 5V/div. V OUT 2V/div. I L 2A/div. V SW 10V/div. V OUT 2V/div. I L 2A/div. V SW 10V/div. MPQ4423A Rev

12 PIN FUNCTIONS Pin # Name Description 1 FB Feedback. Connect FB to the tap of an external resistor divider from the output to GND to set the output voltage. When the FB voltage is below 660mV, the frequency foldback comparator lowers the oscillator frequency to prevent current limit runaway during a shortcircuit fault condition. 2 VCC Bias supply. Decouple VCC with a 0.1μF to 0.22μF capacitor. Select a capacitor that does not exceed 0.22μF. 3 Enable/synchronize. Drive EN/SYNC high to enable the MPQ4423A. Apply an external EN/SYNC clock to EN/SYNC to change the switching frequency. 4 BST Bootstrap. A capacitor connected between SW and BST is required to form a floating supply across the high-side switch driver. A 20Ω resistor placed between the SW and BST cap is strongly recommended to reduce SW voltage spikes. 5 GND System ground. GND is the reference ground of the regulated output voltage. GND requires special consideration during PCB layout. For best results, connect GND with copper traces and vias. 6 SW Switch output. Connect using a wide PCB trace. 7 IN Supply voltage. The MPQ4423A operates from a 4V to 36V input rail. C1 is required to decouple the input rail. Connect using a wide PCB trace. 8 PG Power good. The output of PG is an open drain and goes high if the output voltage exceeds 90% of the nominal voltage. MPQ4423A Rev

13 BLOCK DIAGRAM Figure 1: Functional Block Diagram MPQ4423A Rev

14 OPERATION The MPQ4423A is a high-efficiency, synchronous, rectified, step-down, switch-mode converter with built-in power MOSFETs. It offers a very compact solution that achieves 3A of continuous output current with excellent load and line regulation over a wide input supply range. The MPQ4423A operates in a fixed-frequency, peak-current-control mode to regulate the output voltage. An internal clock initiates a PWM cycle. The integrated high-side power MOSFET (HS- FET) turns on and remains on until its current reaches the value set by the COMP voltage (V COMP ). When the power switch is off, it remains off until the next clock cycle begins. If the current in the power MOSFET does not reach the current value set by COMP within 95% of one PWM period, the power MOSFET is forced off. Internal Regulator The 5V internal regulator powers most of the internal circuitries. This regulator takes the V IN input and operates in the full V IN range. When V IN exceeds 5.0V, the output of the regulator is in full regulation; when V IN falls below 5.0V, the output of the regulator decreases following V IN. A 0.1µF decoupling ceramic capacitor is needed at VCC. Error Amplifier (EA) The error amplifier compares the FB voltage against the internal 0.8V reference (REF) and outputs a COMP voltage that controls the power MOSFET current. The optimized internal compensation network minimizes the external component count and simplifies the control loop design. Enable/SYNC Control EN/SYNC is a digital control that turns the regulator on and off. Drive EN/SYNC high to turn on the regulator; drive EN/SYNC low to turn off the regulator. An internal 500kΩ resistor from EN/SYNC to GND allows EN/SYNC to be floated to shut down the chip. EN/SYNC is clamped internally using a 6.5V series Zener diode (see Figure 2). Connect the EN/SYNC input through a pull-up resistor to any voltage connected to V IN. The pull-up resistor limits the EN/SYNC input current below 150µA. For example, with 12V connected to V IN, R PULLUP (12V - 6.5V) 150µA = 36.7kΩ. Connecting EN/SYNC directly to a voltage source without a pull-up resistor requires limiting the voltage amplitude below or equal to 6V to prevent damage to the Zener diode. EN/SYNC Figure 2: 6.5V-Type Zener Diode To use the synchronous function, connect an external clock in the range of 200kHz to 2.2MHz to EN/SYNC. The external clock should be connected at least 2ms after the output voltage is set. The internal clock rising edge is synchronized to the external clock rising edge when the external clock is connected. The pulse width of the external clock signal should be below 1.7μs. Under-Voltage Lockout (UVLO) Under-voltage lockout (UVLO) protects the chip from operating at an insufficient supply voltage. The MPQ4423A UVLO comparator monitors the output voltage of the internal regulator (VCC). The UVLO rising threshold is about 3.5V, while its falling threshold is 3.3V. Internal Soft Start (SS) The soft start (SS) prevents the converter output voltage from overshooting during start-up. When the chip starts up, the internal circuitry generates a soft-start voltage that ramps up from 0V to 1.2V. When SS is lower than REF, SS overrides REF so the error amplifier uses SS as the reference. When SS exceeds REF, the error amplifier uses REF as the reference. The SS time is internally set to 1.5ms. Over-Current Protection (OCP) and Hiccup The MPQ4423A uses a cycle-by-cycle overcurrent limit when the inductor current peak value exceeds the set current-limit threshold. If the output voltage drops until FB is below the undervoltage (UV) threshold (typically 84% below the reference), the MPQ4423A enters hiccup mode to restart the part periodically. This protection mode is especially useful when the output is dead-shorted to ground. MPQ4423A Rev

15 The average short-circuit current is reduced greatly to alleviate the thermal issue and to protect the regulator. The MPQ4423A exits hiccup mode once the over-current condition is removed. Thermal Shutdown Thermal shutdown prevents the chip from operating at exceedingly high temperatures. When the silicon die temperature exceeds 170 C, the entire chip shuts down. When the temperature drops below its lower threshold (typically 140 C), the chip is enabled again. Floating Driver and Bootstrap Charging An external bootstrap capacitor powers the floating power MOSFET driver. A dedicated internal regulator charges and regulates the bootstrap capacitor voltage to about 5V (see Figure 3). When the voltage between the BST and SW nodes drops below regulation, a PMOS pass transistor connected from V IN to BST turns on. The charging current path is from V IN to BST and then to SW. The external circuit should provide enough voltage headroom to facilitate charging. As long as V IN is higher than SW significantly, the bootstrap capacitor remains charged. When the HS-FET is on, V IN is approximately equal to V SW, so the bootstrap capacitor cannot charge. When the LS-FET is on, V IN - V SW reaches its maximum for fast charging (the charging path is shown in Figure 3a). When the HS-FET and LS-FET are both off, V SW is equal to V OUT, so the difference between V IN and V OUT can charge the bootstrap capacitor (the charging path is shown in Figure 3b). The floating driver has its own UVLO protection, with a rising threshold of 2.2V and hysteresis of 150mV. A 20Ω resistor placed between the SW and BST cap is strongly recommended to reduce SW voltage spikes. 3b: BST Charging Path when HS-FET and LS-FET are Both Off Figure 3: Internal Bootstrap Charging Circuit Start-Up and Shutdown If both V IN and EN exceed their appropriate thresholds, the chip starts up. The reference block starts first, generating a stable reference voltage and current, and then the internal regulator is enabled. The regulator provides a stable supply for the remaining circuitries. Three events can shut down the chip: EN low, V IN low and thermal shutdown. In the shutdown procedure, the signaling path is blocked first to avoid any fault triggering. V COMP and the internal supply rail are then pulled down. The floating driver is not subject to this shutdown command. Power Good (PG) The MPQ4423A has a power good (PG) output. PG is the open drain of the MOSFET. It should be connected to VCC or another voltage source through a resistor (e.g.: 100kΩ). In the presence of an input voltage, the MOSFET turns on so that PG is pulled low before SS is ready. When V FB reaches 90%xREF, PG is pulled high after a delay (typically 90μs). When V FB drops to 84%xREF, PG is pulled low. PG is also pulled low if thermal shutdown occurs or if EN is pulled low. 3a: BST Charging Path when LS-FET is On MPQ4423A Rev

16 APPLICATION INFORMATION Setting the Output Voltage The external resistor divider sets the output voltage (see Typical Application on page 1). The feedback resistor (R1) sets the feedback loop bandwidth with the internal compensation capacitor. Choose R1 to be around 40kΩ. R2 can then be calculated with Equation (1): R1 R2 (1) VOUT V The T-type network is highly recommended when V OUT is low (see Figure 4). Choose the inductor ripple current to be approximately 30% of the maximum load current. The maximum inductor peak current can be calculated with Equation (3): IL IL(MAX) ILOAD (3) 2 Use a larger inductor for improved efficiency below 100mA under light-load conditions. V IN Under-Voltage Lockout (UVLO) Setting The MPQ4423A has an internal, fixed, undervoltage lockout (UVLO) threshold. The rising threshold is 3.5V, while its falling threshold is about 3.3V. The application needs a higher UVLO point, so the external resistor divider between EN/SYNC and IN can be used to achieve a higher equivalent UVLO threshold (see Figure 5). Figure 4: T-Type Network RT + R1 is used to set the loop bandwidth. The higher RT + R1 is, the lower the bandwidth is. To ensure loop stability, it is strongly recommended to limit the bandwidth below 40kHz based on the 410kHz default f sw. Table 1 lists the recommended T-type resistor values for common output voltages. Table 1: Resistor Selection for Common Output Voltages V OUT (V) R1 (kω) R2 (kω) RT (kω) (1%) 13 (1%) 51 (1%) (1%) 7.68 (1%) 51 (1%) Selecting the Inductor Use a 1µH to 10µH inductor with a DC current rating at least 25% higher than the maximum load current for most applications. For the highest efficiency, an inductor with a small DC resistance is recommended. For most designs, the inductance value can be derived from Equation (2): L 1 V OUT (VIN V OUT ) V I f IN L OSC Where ΔI L is the inductor ripple current. (2) Figure 5: Adjustable UVLO using EN/SYNC Divider The UVLO threshold can be calculated with Equation (4) and Equation (5): INUV INUV R5 (1 ) (4) 500k//R6 RISING V EN_RISING R5 (1 ) (5) 500k//R6 FALLING V EN_FALLING Where V EN_RISING is 1.4V and V EN_FALLING is 1.25V. When selecting R5, ensure that it is large enough to limit the current flows into EN/SYNC below 150µA. Selecting the Input Capacitor The input current to the step-down converter is discontinuous and therefore requires a capacitor to supply AC current to the step-down converter while maintaining the DC input voltage. For best performance, use low ESR capacitors. Ceramic capacitors with X5R or X7R dielectrics are recommended because of their low ESR and small temperature coefficients. MPQ4423A Rev

17 For most applications, a 22µF ceramic capacitor is sufficient to maintain the DC input voltage. It is strongly recommended to use another lower value capacitor (e.g.: 1µF) with a small package size (0603) to absorb high-frequency switching noise. Place the smaller capacitor as close to IN and GND as possible (see PCB Layout Guidelines on page 18). Since C1 absorbs the input switching current, it requires an adequate ripple current rating. The RMS current in the input capacitor can be estimated with Equation (6): V V I C1 ILOAD 1 (6) V V OUT IN OUT IN The worse case condition occurs at V IN = 2V OUT, shown in Equation (7): ILOAD IC1 2 (7) For simplification, choose an input capacitor with an RMS current rating greater than half of the maximum load current. The input capacitor can be electrolytic, tantalum, or ceramic. When using electrolytic or tantalum capacitors, add a small, high-quality ceramic capacitor (e.g.: 1μF) placed as close to the IC as possible. When using ceramic capacitors, ensure that they have enough capacitance to provide a sufficient charge to prevent an excessive voltage ripple at input. The input voltage ripple caused by capacitance can be estimated with Equation (8): ILOAD V OUT V OUT VIN 1 (8) fs C1 VIN VIN Selecting the Output Capacitor The output capacitor (C2) maintains the DC output voltage. Use ceramic, tantalum, or low- ESR electrolytic capacitors. For best results, use low ESR capacitors to keep the output voltage ripple low. The output voltage ripple can be estimated with Equation (9): V OUT V OUT 1 VOUT 1 RESR fs L1 VIN 8fS C2 (9) Where L 1 is the inductor value and R ESR is the equivalent series resistance (ESR) value of the output capacitor. For ceramic capacitors, the capacitance dominates the impedance at the switching frequency and causes the majority of the output voltage ripple. For simplification, the output voltage ripple can be estimated with Equation (10): V OUT V OUT ΔVOUT 1 (10) 2 8f V S L1C2 IN With tantalum or electrolytic capacitors, the ESR dominates the impedance at the switching frequency. For simplification, the output ripple can be approximated with Equation (11): V OUT OUT ΔVOUT 1 RESR fs L 1 V IN V (11) The characteristics of the output capacitor also affect the stability of the regulation system. The MPQ4423A can be optimized for a wide range of capacitance and ESR values. BST Resistor and External BST Diode A 20Ω resistor in series with a BST capacitor is recommended to reduce SW voltage spikes. A higher resistance is better for SW spike reduction but compromises efficiency. An external BST diode can enhance the efficiency of the regulator when the duty cycle is high (>65%). A power supply between 2.5V and 5V can be used to power the external bootstrap diode. Either VCC or VOUT can be used as the power supply in this circuit (see Figure 6). VCC BST SW External BST diode 1N4148 R BST C BST L VCC/V OUT C OUT V OUT Figure 6: Optional External Bootstrap Diode to Enhance Efficiency The recommended external BST diode is IN4148, and the recommended BST capacitor value is 0.1µF to 1μF. MPQ4423A Rev

18 PCB Layout Guidelines Efficient PCB layout, especially the input capacitor and VCC capacitor placement, is critical for stable operation. For best results, refer to Figure 7 and follow the guidelines below. 1. Place the ceramics input capacitor as close to IN and GND as possible, especially the small package size (0603) input bypass capacitor. 2. Keep the connection of the input capacitor and IN as short and wide as possible. 3. Place the VCC capacitor to VCC and GND as close as possible. 4. Make the trace length of VCC to the capacitor to GND as short as possible. 5. Use a large ground plane connected directly to GND. 6. Add vias near GND if the bottom layer is the ground plane. 7. Route SW and BST away from sensitive analog areas such as FB. 8. Place the T-type feedback resistor close to the chip to ensure that the trace connecting to FB is as short as possible. Top Layer Bottom Layer Figure 7: Recommended PCB Layout MPQ4423A Rev

19 TYPICAL APPLICATION CIRCUITS Figure 8: 3.3V Output Typical Application Circuit MPQ4423A Rev

20 PACKAGE INFORMATION QFN-8 (3mmx3mm) NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MPQ4423A Rev

21 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Monolithic Power Systems (MPS): MPQ4423AGQ-Z MPQ4423AGQ-AEC1-P MPQ4423AGQ-AEC1-Z MPQ4423AGQ-P