NCP MHz, 1A, High Efficiency, Low Ripple, Adjustable Output Voltage Step-down Converter

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1 .7MHz, A, High Efficiency, Low Ripple, Adjustable Output Voltage Step-down Converter The NCP529 stepdown DCDC converter is a monolithic integrated circuit for portable applications powered from one cell Liion or three cell Alkaline/NiCd/NiMH batteries. The device is able to deliver up to. A on an output voltage range externally adjustable from.9 V to 3.9 V or fixed at.2 V or.35 V. It uses synchronous rectification to increase efficiency and reduce external part count. The device also has a builtin.7 MHz (nominal) oscillator which reduces component size by allowing a small inductor and capacitors. Automatic switching PWM/PFM mode offers improved system efficiency. Additional features include integrated softstart, cyclebycycle current limiting and thermal shutdown protection. The NCP529 is available in a space saving, low profile 2x2x.5 mm UDFN6 package and TSOP5 package. Features Up to 96% Efficiency Best In Class Ripple, including PFM mode Source up. A.7 MHz Switching Frequency Adjustable from.9 V to 3.9 V or Fixed at.2 V or.35 V Synchronous rectification for higher efficiency 2.7 V to 5.5 V Input Voltage Range Low Quiescent Current 28 A Shutdown Current Consumption of.3 A Thermal Limit Protection Short Circuit Protection All Pins are Fully ESD Protected These are PbFree Devices Typical Applications Cellular Phones, Smart Phones and PDAs Digital Still Cameras MP3 Players and Portable Audio Systems Wireless and DSL Modems USB Powered Devices Portable Equipment L V IN VIN SW CIN COUT V OUT 5 TSOP5 SN SUFFIX CASE 483 MARKING DIAGRAM DXJ = Specific Device Code A = Assembly Location Y = Year W = Work Week = PbFree Package (Note: Microdot may be in either location) UDFN6 MU SUFFIX CASE 57AB L V IN VIN SW V OUT CIN COUT DXJAYW XXM XX = Specific Device Code M = Date Code = PbFree Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet OFF ON EN FB GND R R2 C ff OFF ON EN FB GND Figure. Typical Application for Adjustable Version Figure 2. Typical Application for Fixed Version Semiconductor Components Industries, LLC, 2 September, 2 Rev. 5 Publication Order Number: NCP529/D

2 PIN FUNCTION DESCRIPTION Pin TSOP5 Pin UDFN6 Pin Name Type Description 6 EN Analog Input Enable for switching regulators. This pin is active HIGH and is turned off by logic LOW on this pin. 2 2,4,7 (Note ) GND Analog / Power Ground This pin is the GND reference for the NFET power stage and the analog section of the IC. The pin must be connected to the system ground. 3 5 SW Analog Output Connection from power MOSFETs to the Inductor. 4 3 VIN Analog / Power Input Power supply input for the PFET power stage, analog and digital blocks. The pin must be decoupled to ground by a 4.7 F ceramic capacitor. 5 FB Analog Input Feedback voltage from the output of the power supply. This is the input to the error amplifier.. Exposed pad for UDFN6 package, named Pin 7, must be connected to system ground. PIN CONNECTIONS EN 5 FB FB 6 EN GND 2 GND SW SW 3 4 VIN VIN 3 4 GND (Top View) Figure 3. Pin Connections TSOP5 (Top View) Figure 4. Pin Connections UDFN6 PERFORMANCES EFFICIENCY (%) I OUT (ma) Figure 5. Efficiency vs Output Current V IN = 3.6 V, V OUT = 3.3 V 2

3 FUNCTIONAL BLOCK DIAGRAM Q V battery VIN PWM/PFM CONTROL Q2 SW 2.2 H F 4.7 F GND I LIMIT R 8 pf Enable EN LOGIC CONTROL & THERMAL SHUTDOWN FB REFERENCE VOLTAGE R2 Figure 6. Simplified Block Diagram 3

4 MAXIMUM RATINGS Rating Symbol Value Unit Minimum Voltage All Pins V min.3 V Maximum Voltage All Pins (Note 2) V max 7. V Maximum Voltage EN V max V IN +.3 V Thermal Resistance, JunctiontoAir (TSOP5 Package) Thermal Resistance using TSOP5 Recommended Board Layout (Note 9) R JA 3 C/W Thermal Resistance, JunctiontoAir (UDFN6 Package) Thermal Resistance using UDFN6 Recommended Board Layout (Note 9) R JA 22 4 C/W Operating Ambient Temperature Range (Notes 7 and 8) T A 4 to 85 C Storage Temperature Range T stg 55 to 5 C Junction Operating Temperature (Notes 7 and 8) T j 4 to 5 C Latchup Current Maximum Rating (T A = 85 C) (Note 5) Other Pins Lu ma ESD Withstand Voltage (Note 4) Human Body Model Machine Model V esd 2. 2 kv V Moisture Sensitivity Level (Note 6) MSL per IPC Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at T A = 25 C. 3. According to JEDEC standard JESD22A8B. 4. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) per JEDEC standard: JESD22A4. Machine Model (MM) per JEDEC standard: JESD22A5. 5. Latchup current maximum rating per JEDEC standard: JESD JEDEC Standard: JSTD2A. 7. In applications with high power dissipation (low V IN, high I OUT ), special care must be paid to thermal dissipation issues. Board design considerations thermal dissipation vias, traces or planes and PCB material can significantly improve junction to air thermal resistance R JA (for more information, see design and layout consideration section). Environmental conditions such as ambient temperature T A brings thermal limitation on maximum power dissipation allowed. The following formula gives calculation of maximum ambient temperature allowed by the application: T A MAX = T J MAX (R JA x P d ) Where: T J is the junction temperature, P d is the maximum power dissipated by the device (worst case of the application), and R JA is the junctiontoambient thermal resistance. 8. To prevent permanent thermal damages, this device include a thermal shutdown which engages at 8 C (typ). 9. Board recommended TSOP5 and UDFN6 layouts are described on Layout Considerations section. P D, POWER DISSIPATION (mw) TSOP T A, AMBIENT TEMPERATURE ( C) UDFN6 I OUTmax, MAXIMUM OUTPUT CUR- RENT (ma) UDFN6 TSOP V IN, INPUT VOLTAGE (V) Figure 8. Power Derating Figure 7. Maximum Output Current, T A = 45 C 4

5 ELECTRICAL CHARACTERISTICS (Typical values are referenced to T A = +25 C, Min and Max values are referenced 4 C to +85 C ambient temperature, unless otherwise noted, operating conditions V IN = 3.6 V, V OUT =.2 V, unless otherwise noted.) Rating Conditions Symbol Min Typ Max Unit INPUT VOLTAGE Input Voltage Range V in V Quiescent Current No Switching, No load I Q A Standby Current EN Low I STB.3. A Under Voltage Lockout V IN Falling V UVLO V Under Voltage Hysteretis V UVLOH mv ANALOG AND DIGITAL PIN Positive going Input High Voltage Threshold V IH.2 V Negative going Input High Voltage Threshold V IL.4 V EN Threshold Hysteresis V ENH mv EN High Input Current EN = 3.6 V I ENH.5 A OUTPUT Feedback Voltage Level Output Voltage Range (Notes, ) Adjustable Version Fixed Version at.2 V Fixed Version at.35 V USB or 5 V Rail Powered Applications (V IN from 4.3 V to 5.5 V) (Note 2) Output Voltage Accuracy Room Temperature (Note 3) Overtemperature Range V FB V OUT.9.9 V OUT Maximum Output Current (Note ) I OUTMAX A Output Voltage Load Regulation Overtemperature Load Transient Response Rise/Fall Time s Load = ma to ma (PWM Mode) Load = ma to ma (PFM Mode) ma to ma Load Step (PFM to PWM Mode) 2 ma to 6 ma Load Step (PWM to PWM Mode) V LOADR V LOADT Output Voltage Line Regulation Load = ma V IN = 2.7 V to 5.5 V V LINER.5 % Line Transient Response Load = ma 3.6 V to 3.2 V Line Step (Fall Time = 5 s) V LINET 6. mv PP Output Voltage Ripple I OUT = ma I OUT = 3 ma V RIPPLE mv PP Switching Frequency F SW MHz Duty Cycle D % SoftStart Time Time from EN to 9% of Output Voltage t START 3 5 s POWER SWITCHES HighSide MOSFET OnResistance R ONHS 4 m LowSide MOSFET OnResistance R ONLS 3 m HighSide MOSFET Leakage Current I LEAKHS.5 A LowSide MOSFET Leakage Current I LEAKLS. A PROTECTION DCDC Short Circuit Protection Peak Inductor Current I PK.6 A Thermal Shutdown Threshold T SD 8 C Thermal Shutdown Hysteresis T SDH 4 C. Functionality guaranteed per design and characterization.. Whole output voltage range is available for adjustable versions only. By topology, the maximum output voltage will be equal or lower than the input voltage. 2. See chapter USB or 5 V Rail Powered Applications. 3.For adjustable versions only, the overall output voltage tolerance depends upon the accuracy of the external resistor (R and R2). Specified value assumes that external resistor have.% tolerance V V % % mv 5

6 TABLE OF GRAPHS Typical Characteristics for Stepdown Converter Figure Efficiency vs. Output Current,, 2 I q ON Quiescent Current, PFM no load vs. Input Voltage 9 I q OFF Standby Current, EN Low vs. Input Voltage 8 F SW Switching Frequency vs. Ambient Temperature 3 V LOADR Load Regulation vs. Load Current 4 V LOADT Load Transient Response 6, 7 V LINER Line Regulation vs. Output Current 5 V LINET Line Transient Response 8, 9 t START Soft Start 2 I PK Short Circuit Protection 2 V UVLO Under Voltage Lockout Threshold vs. Ambient Temperature 22 V IL, V IH Enable Threshold vs. Ambient Temperature 23 P, G Phase & Gain Performance 24 6

7 I stb, STANDBY CURRENT ( A) V IN, INPUT VOLTAGE (V) Figure 9. Standby Current vs. Input Voltage (Enable =, Temperature = 25 C) I q, QUIESCENT CURRENT ( A) V IN, INPUT VOLTAGE (V) Figure. Quiescent Current vs. Input Voltage (Open Loop, Feedback =, Temperature = 25 C) EFFICIENCY (%) C 85 C I OUT, OUTPUT CURRENT (ma) 4 C Figure. Efficiency vs. Output Current (V IN = 3.3 V, V OUT =.2 V) EFFICIENCY (%) V BAT = 2.7 V I OUT, OUTPUT CURRENT (ma) 5.5 V 3.3 V Figure 2. Efficiency vs. Output Current (V out =.2 V, Temperature = 25 C) EFFICIENCY (%) V 3.3 V V OUT =.9 V I OUT, OUTPUT CURRENT (ma) Figure 3. Efficiency vs. Output Current (V IN = 3.6 V, Temperature = 25 C) SWITCHING FREQUENCY (MHz) V IN = 2.7 V 3.6 V 5.5 V T A, AMBIENT TEMPERATURE ( C) Figure 4. Switching Frequency vs. Ambient Temperature (V out =.2 V, I out = 2 ma) 7

8 LOAD REGULATION (%) C 85 C 4 C LINE REGULATION (%).. 2. I OUT = 8 ma ma ma I OUT, OUTPUT CURRENT (ma) Figure 5. Load Regulation vs. Output Current (V IN = 5.5 V, V OUT =.2 V) V IN, INPUT VOLTAGE (V) Figure 6. Line Regulation vs. Input Voltage (V OUT =.2 V, Temperature = 25 C) Figure 7. ma to ma Load Transient in s (V IN = 3.6 V, V OUT =.2 V, Temperature = 25 C) Figure 8. 2 ma to 6 ma Load Transient in s (V IN = 3.6 V, V OUT =.2 V, Temperature = 25 C) Figure V to 3.6 V Line Transient, Rise = 5 s (V IN =.2 V, I OUT = ma, Temperature = 25 C) Figure V to 3. V Line Transient, Fall = 5 s (V IN =.2 V, I OUT = ma, Temperature = 25 C) 8

9 Figure 2. Typical SoftStart (V IN = 3.6 V, V OUT =.2 V, I OUT = ma, Temperature = 25 C) Figure 22. ShortCircuit Protection (V IN = 3.6 V, V OUT =.2 V, I OUT = CC, Temperature = 25 C) UNDERVOLTAGE LOCKOUT THRESHOLD (V) UVLOrise UVLOfall T A, AMBIENT TEMPERATURE ( C) Figure 23. Undervoltage Lockout Threshold vs. Ambient Temperature 7 ENABLE THRESHOLD VOLTAGES (V) V IH V IL T A, AMBIENT TEMPERATURE ( C) Figure 24. Enable Threshold Voltages vs. Ambient Temperature GAIN (db) 3 Gain Phase PHASE ( ) FREQUENCY (Hz) Figure 25. Phase and Gain Performance (V IN = 3.6 V, V OUT =.2 V, I OUT = 2 ma, Temperature = 25 C) 9

10 DC/DC OPERATION DESCRIPTION Detailed Description The NCP529 uses a constant frequency, current mode stepdown architecture. Both the main (Pchannel MOSFET) and synchronous (Nchannel MOSFET) switches are internal. The output voltage is set by an external resistor divider in the range of.9 V to 3.9 V and can source at least A. The NCP529 works with two modes of operation; PWM/PFM depending on the current required. In PWM mode, the device can supply voltage with a tolerance of 3% and 9% efficiency or better. Lighter load currents cause the device to automatically switch into PFM mode to reduce current consumption and extended battery life. Additional features include softstart, undervoltage protection, current overload protection and thermal shutdown protection. As shown on Figure, only six external components are required. The part uses an internal reference voltage of.6 V. It is recommended to keep NCP529 in shutdown mode until the input voltage is 2.7 V or higher. PWM Operating Mode In this mode, the output voltage of the device is regulated by modulating the ontime pulse width of the main switch Q at a fixed.7 MHz frequency. The switching of the PMOS Q is controlled by a flipflop driven by the internal oscillator and a comparator that compares the error signal from an error amplifier with the sum of the sensed current signal and compensation ramp. The driver switches ON and OFF the upper side transistor (Q) while the lower side transistor is switched OFF then ON. At the beginning of each cycle, the main switch Q is turned ON by the rising edge of the internal oscillator clock. The inductor current ramps up until the sum of the current sense signal and compensation ramp becomes higher than the error amplifier s voltage. Once this has occurred, the PWM comparator resets the flipflop, Q is turned OFF while the synchronous switch Q2 is turned ON. Q2 replaces the external Schottky diode to reduce the conduction loss and improve the efficiency. To avoid overall power loss, a certain amount of dead time is introduced to ensure Q is completely turned OFF before Q2 is being turned ON. V OUT I SW V SW Figure 26. PWM Switching Waveforms (V IN = 3.6 V, V OUT =.2 V, I OUT = 6 ma, Temperature = 25 C) PFM Operating Mode Under light load conditions, the NCP529 enters in low current PFM mode of operation to reduce power consumption. The output regulation is implemented by pulse frequency modulation. If the output voltage drops below the threshold of PFM comparator a new cycle will be initiated by the PFM comparator to turn on the switch Q. Q remains ON during the minimum on time of the structure while Q2 is in its current source mode. The peak inductor current depends upon the drop between input and output voltage. After a short dead time delay where Q is switched OFF, Q2 is turned in its ON state. The negative current detector will detect when the inductor current drops below zero and sends a signal to turn Q2 to current source mode to prevent a too large deregulation of the output voltage. When the output voltage falls below the threshold of the PFM comparator, a new cycle starts immediately. V OUT V SW I SW Figure 27. PFM Switching Waveforms (V IN = 3.6 V, V OUT =.2 V, I OUT = ma, Temperature = 25 C)

11 SoftStart The NCP529 uses softstart to limit the inrush current when the device is initially powered up or enabled. Soft start is implemented by gradually increasing the reference voltage until it reaches the full reference voltage. During startup, a pulsed current source charges the internal softstart capacitor to provide gradually increasing reference voltage. When the voltage across the capacitor ramps up to the nominal reference voltage, the pulsed current source will be switched off and the reference voltage will switch to the regular reference voltage. Cyclebycycle Current Limitation From the block diagram, an I LIM comparator is used to realize cyclebycycle current limit protection. The comparator compares the SW pin voltage with the reference voltage, which is biased by a constant current. If the inductor current reaches the limit, the I LIM comparator detects the SW voltage falling below the reference voltage and releases the signal to turn off the switch Q. The cyclebycycle current limit is set at 6 ma (nom). Low Dropout Operation The NCP529 offers a low input to output voltage difference. The NCP529 can operate at % duty cycle. In this mode the PMOS (Q) remains completely ON. The minimum input voltage to maintain regulation can be calculated as: V out V OUT(max) I OUT RDS(on) _R INDUCTOR (eq. ) V OUT : Output Voltage (V) I OUT : Max Output Current R DS(on) : PChannel Switch R DS(on) R INDUCTOR : Inductor Resistance (DCR) Undervoltage Lockout The Input voltage V IN must reach 2.4 V (typ) before the NCP529 enables the DC/DC converter output to begin the start up sequence (see softstart section). The UVLO threshold hysteresis is typically mv. Shutdown Mode Forcing this pin to a voltage below.4 V will shut down the IC. In shutdown mode, the internal reference, oscillator and most of the control circuitries are turned off. Therefore, the typical current consumption will be.3 A (typical value). Applying a voltage above.2 V to EN pin will enable the DC/DC converter for normal operation. The device will go through softstart to normal operation. Thermal Shutdown Internal Thermal Shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction Temperature is exceeded. If the junction temperature exceeds 8 C, the device shuts down. In this mode all power transistors and control circuits are turned off. The device restarts in softstart after the temperature drops below 4 C. This feature is provided to prevent catastrophic failures from accidental device overheating. Short Circuit Protection When the output is shorted to ground, the device limits the inductor current. The dutycycle is minimum and the consumption on the input line is 55 ma (typ). When the short circuit condition is removed, the device returns to the normal mode of operation. USB or 5 V Rail Powered Applications For USB or 5 V rail powered applications, NCP529 is able to supply voltages up to 3.9 V, 6 ma, operating in PWM mode only, with high efficiency (Figure 28), low output voltage ripple and good load regulation results over all current range (Figure 29) C C C EFFICIENCY (%) LOAD REGULATION (%) I OUT, OUTPUT CURRENT (ma) Figure 28. Efficiency vs. Output Current (V IN = 5. V, V OUT = 3.9 V) 25 C 85 C 4 C I OUT, OUTPUT CURRENT (ma) Figure 29. Load Regulation vs. Output Current (V IN = 5. V, V OUT = 3.9 V)

12 APPLICATION INFORMATION Output Voltage Selection In case of adjustable versions, the output voltage is programmed through an external resistor divider connected from V OUT to FB then to GND. For low power consumption and noise immunity, the resistor from FB to GND (R2) should be in the [k6k] range. If R2 is 2 k given the V FB is.6 V, the current through the divider will be 3. A. The formula below gives the value of V OUT, given the desired R and the R value: V out V FB ( R R2) (eq. 2) V OUT : Output Voltage (V) V FB : Feedback Voltage =.6 V R: Feedback Resistor from V OUT to FB R2: Feedback Resistor from FB to GND Input Capacitor Selection In PWM operating mode, the input current is pulsating with large switching noise. Using an input bypass capacitor can reduce the peak current transients drawn from the input supply source, thereby reducing switching noise significantly. The capacitance needed for the input bypass capacitor depends on the source impedance of the input supply. The maximum RMS current occurs at 5% duty cycle with maximum output current, which is IO, max/2. For NCP529, a low profile ceramic capacitor of 4.7 F should be used for most of the cases. For effective bypass results, the input capacitor should be placed as close as possible to the VIN Pin Table. LIST OF INPUT CAPACITORS Manufacturer Part Number Case Size Value ( F) DC Bias (V) Technology MURATA GRM5 series X5R MURATA GRM8 series X5R TDK C68 series X5R TDK C68 series X5R Output LC Filter Design Considerations The NCP529 operates at.7 MHz frequency and uses current mode architecture. The correct selection of the output filter ensures good stability and fast transient response. Due to the nature of the buck converter, the output LC filter must be selected to work with internal compensation. For NCP529, the internal compensation is internally fixed and it is optimized for an output filter of L = 2.2 H and C OUT = F. The corner frequency is given by: f 2 L C OUT H F 34 khz (eq. 3) The device operates with inductance value of 2.2 H. If the corner frequency is moved, it is recommended to check the loop stability depending of the accepted output ripple voltage and the required output current. Take care to check the loop stability. The phase margin is usually higher than 45. Table 2. LC FILTER EXAMPLE Inductance (L) Output Capacitor (C OUT ) 2.2 H F 4.7 H 4.7 F Inductor Selection The inductor parameters directly related to device performances are saturation current and DC resistance and inductance value. The inductor ripple current ( I L ) decreases with higher inductance: I L V OUT V OUT L f SW V IN (eq. 4) I L : Peak to peak inductor ripple current L: Inductor value f SW : Switching frequency The saturation current of the inductor should be rated higher than the maximum load current plus half the ripple current: I L(max) I O(max) I L 2 (eq. 5) I L(max) : Maximum inductor current I O(max) : Maximum Output current The inductor s resistance will factor into the overall efficiency of the converter. For best performances, the DC resistance should be less than.3 for good efficiency. 2

13 Table 3. LIST OF INDUCTORS Manufacturer Part Number Case Size (mm) Height Max (mm) L ( H) DCR Typ ( ) DCR Max ( ) Rated Current (ma) Inductance Drop Rated Current (ma) Temperature Drop Structure COILCRAFT DO65T x NA.7 8 (-%) 7 (+4 C) Wire Wound COILCRAFT EPL x (-3%) 2 (+4 C) Wire Wound COILCRAFT EPL x (-3%) 8 (+4 C) Wire Wound MURATA LQM2HPN2R2 2.5 x NA 3 (+4 C) Multilayer MURATA LQH3NPN2R2 3. x (-3%) 46 (+4 C) Wire Wound MURATA LQH44PN2R2 4. x (-3%) 8 (+4 C) Wire Wound TDK MLP252S2R2L 2.5 x (-3%) NA Multilayer TDK VLS252T2R2 2. x (-3%) (+4 C) Wire Wound WURTH ELEC x (-35%) 7 (+4 C) Wire Wound Output Capacitor Selection Selecting the proper output capacitor is based on the desired output ripple voltage. Ceramic capacitors with low ESR values will have the lowest output ripple voltage and are strongly recommended. The output capacitor requires either an X7R or X5R dielectric. The output ripple voltage in PWM mode is given by: V OUT I L 4 f SW C OUT ESR (eq. 6) Table 4. LIST OF OUTPUT CAPACITORS Manufacturer Part Number Case Size Value ( F) DC Bias (V) Technology MURATA GRM5 series X5R MURATA GRM8 series X5R MURATA GRM8 series X5R TDK C68 series X5R TDK C68 series X5R TDK C68 series X5R FeedForward Capacitor Selection (Adjustable Only) The feed-forward capacitor sets the feedback loop response and acts on soft-start time. A minimum 8 pf feed-forward capacitor is needed to ensure loop stability. Having feed-forward capacitor of nf or higher can increase softstart time and reduce inrush current. Choose a small ceramic capacitor X7R or X5R or COG dielectric. 3

14 LAYOUT CONSIDERATIONS Electrical Layout Considerations Implementing a high frequency DCDC converter requires respect of some rules to get a powerful portable application. Good layout is key to prevent switching regulators to generate noise to application and to themselves. Electrical layout guide lines are: Use short and large traces when large amount of current is flowing. Keep the same ground reference for input and output capacitors to minimize the loop formed by high current path from the battery to the ground plane. Isolate feedback pin from the switching pin and the current loop to protect against any external parasitic signal coupling. Add a feedforward capacitor between V OUT and FB which adds a zero to the loop and participates to the good loop stability. A 8 pf capacitor is recommended to meet compensation requirements. A four layer PCB with a ground plane and a power plane will help NCP529 noise immunity and loop stability. Thermal Layout Considerations High power dissipation in small package leads to thermal consideration such as: Enlarge V IN trace and added several vias connected to power plane. Connect GND pin to top plane. Join top, bottom and each ground plane together using several free vias in order to increase radiator size. For high ambient temperature and high power dissipation requirements, UDFN6 package using exposed pad connected to main radiator is recommended. Refer to Notes 7, 8, and 9. V OUT Trace FB Trace EN Trace V IN Trace FB Trace SW Trace V IN Trace SW Trace V OUT Trace GND Plane EN Trace Figure 3. TSOP5 Recommended Board Layout GND Plane Figure 3. UDFN6 Recommended Board Layout ORDERING INFORMATION Device Nominal Output Voltage Marking Package Shipping NCP529ASNTG Adj DXJ TSOP5 3 / Tape & Reel NCP529MUTBG Adj TL NCP529MU2TBG.2 V TC NCP529MU35TBG.35 V RC UDFN6 3 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8/D. 4

15 PACKAGE DIMENSIONS TSOP5 CASE 4832 ISSUE G 2X 2X NOTE 5. T.2 T L H G A B C D 5X.2 C A B T S SEATING PLANE J K DETAIL Z M DETAIL Z NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y4.5M, CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. 5. OPTIONAL CONSTRUCTION: AN ADDITIONAL TRIMMED LEAD IS ALLOWED IN THIS LOCATION. TRIMMED LEAD NOT TO EXTEND MORE THAN.2 FROM BODY. MILLIMETERS DIM MIN MAX A 3. BSC B.5 BSC C.9. D.25.5 G.95 BSC H.. J..26 K.2.6 L M S SOLDERING FOOTPRINT* SCALE : mm inches *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 5

16 PACKAGE DIMENSIONS UDFN6 2x2,.65P CASE 57AB ISSUE A D A B NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y4.5M, CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN.5 AND.2mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 2X PIN ONE REFERENCE. C 2X. C. C ÍÍ ÍÍ A3 E MILLIMETERS DIM MIN MAX A A..5 A3.27 REF b D 2. BSC D2.5.7 E 2. BSC E2.8. e.65 BSC K L X.8 C D2 A A C SEATING PLANE SOLDERING FOOTPRINT*.95 6X.47 6X.4 6X L 3 e 4X.7 E2 6X K 6 4 BOTTOM VIEW 6X b. C.5 C A B NOTE PITCH DIMENSIONS: MILLIMETERS *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. The product described herein (NCP529), may be covered by the following U.S. patents: TBD. There may be other patents pending. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 827 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NCP529/D

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