ISSCC 2003 / SESSION 2 / MULTIMEDIA SIGNAL PROCESSING / PAPER 2.7

Transcription

1 ISSCC 23 / SESSION 2 / MULTIMEDIA SIGNAL PROCESSING / PAPER A 1GOPS Reconfigurable Signal Processing IC with Embedded FPGA and 3-1.2GB/s Flash Memory Subsystem M. Borgatti, L. Calì, G. De Sandre, B. Forêt, D. Iezzi, F. Lertora, G. Muzzi, M. Pasotti, M. Poles, P.L. Rolandi STMicroelectronics, Agrate Brianza, Italy Increasing complexity of system design and shorter time-to-market requirements lead research towards the investigation of hybrid systems including processors enhanced by programmable logic [1][2]. A dynamically reconfigurable processing unit tightly connected to a Flash EEPROM memory subsystem is presented. The reconfigurable processing unit targets image-voice processing and recognition application domains and is implemented by joining a configurable and extensible processor core and an SRAM-based embedded FPGA. Application-specific HW units are added and dynamically modified by embedded FPGA reconfiguration. By implementing application-specific vector processing instructions the unit shows a peak computing power of 1GOPS. Efficient read-writeerase access to code, data and FPGA bitstreams is provided by a specific memory subsystem based on a modular 8Mb, 4-bank Flash memory. It features 3 content-specific I/O ports and delivers an aggregate peak read throughput of 1.2GB/s. The system architecture is illustrated in Fig The functional purposes of the embedded FPGA are: i) extension of the processor datapath supporting a set of additional special-purpose C- callable microprocessor instructions; ii) bus-mapped coprocessors (connected to the system bus through a master/slave interface); iii) flexible I/O (to connect external units or sensors with applicationspecific communication protocols). Even though such different circuit purposes require different kinds of programmable logic for best implementation of either arithmetic-dominated or controldominated logic, this implementation is a single programmable logic fabric to be shared among different purposes both in space (same configuration) and time (subsequent configurations). A single, high I/O count, fine-grain e-fpga operates as a datapath for the microprocessor pipeline and as dedicated control logic for bus coprocessor and I/O control interface. FPGA reconfiguration is concurrent to software execution. A local bus connects a dedicated 32b Flash memory port (FP) to the FPGA programming interface. A DMA channel handles the bitstream transfer while microprocessor fetches instructions and data from different Flash memory ports: 64b wide code port (CP) and data port (DP). To support streaming applications a 1kB dual-port buffer is used to interface fast decoding hardware and slower software running on the processor. The memory sub-system architecture is shown in Fig The modular memory (dotted line) includes charge pumps (Power Block), testability circuits (DFT), a power management arbiter (PMA) and a customizable array of N independent 2Mb flash memory modules, depending on the storage requirements (N=4 in the current implementation). The modular memory features (N+2) 128b target ports and implements a N-bank uniform memory. An 8b microprocessor (µp) is devoted to handle complex file-system functions (defrag, compression, virtual erase, etc.) not natively supported by DP, and assists for built-in self test. A (N+2)x4 128b crossbar connects the modular memory with the four initiators (CP, DP, FP and µp) providing that three banks can be read in parallel at full speed. The memory space of the four modules is arranged in three programmable user-defined partitions, each one devoted to a port. Each 2Mb flash memory module has a 128b IO data bus with 4ns access time, resulting in 4MB/s, and a program/erase control unit. Simultaneous memory operations use the power management arbiter (PMA) for optimal scheduling. Available power and user-defined priorities are considered to schedule conflicting resource requests in a single clock cycle. The memory system allows up to four simultaneous operations (with a limit of one both for write and erase). Figure depicts the memory hierarchy and parallelism across the system. CP and DP are interfaced to the 64b, 8MB/s AHB system bus. At a system clock rate of 1MHz each I/O port can independently operate at maximum speed. An aggregate peak read rate of 1.2GB/s can be sustained as it is limited by memory access time. In the current implementation the e-fpga reconfiguration takes 5µs at 1 MHz. 5MB/s average throughput out of the available 4MB/s are currently sustained by the e-fpga configuration interface. System performance is evaluated for an image processing application (facial recognition) and a speech recognition application. More than 2 specific instructions were designed as C/assemblycallable functions, automatically translated to RTL, then synthesized and mapped to the e-fpga. Figure shows two examples of specific microprocessor extensions. On the righthand side, an 8-issue, 8b, L2 calculation accounts for 23 8b arithmetic operations and 6 64b operations requiring about 1k ASIC equivalent gates. On the left-hand side, a datapath for an optimized fixed-point calculation of the square root accounts for 12 32b operations for about 2k ASIC equivalent gates. The overall performance improvements for the face recognition tasks are shown in Fig Execution time is compared for 32b RISC with basic DSP extensions (MAC, zero-overhead loops, etc) and the same processor enhanced with application-specific instructions. Measured speed-ups range from 1.8x to 1.6x (on the mostdemanding task), with an overall improvement of 8.5x. Notice that switching between algorithm stages requires only one reconfiguration of the e-fpga. Reconfiguration time is negligible. The speedup factors take into account the possible multi-cycle clock penalty due to processor-fpga synchronization in case instruction extensions are slower than the processor clock. Energy efficiency figures are depicted in Fig As the average power consumption of the system extended with the e-fpga is slightly higher (1-15%), the energy reduction for executing each of the tasks on its specific HW configuration (power-delay product improvement) results in an overall reduction of 6.7x. Only one task showed slightly worse total execution energy, while showing benefits on execution speed. Last column of Fig reports the energy-delay improvement of each specific HW configuration compared to the general-purpose counterpart. Energy required for e-fpga reconfiguration is always negligible. Measurements show the best energy efficiency in the range of several MOPS/mW at a 1.8V supply. It lies between conventional ASIP/DSP and dedicated configurable hardware implementations [2]. The full-chip is implemented in a.18µm 2P 6M CMOS embedded Flash technology, chip area is 7mm 2, technology and device characteristics are summarized in Fig A chip micrograph is shown in Fig Acknowledgments The authors thank all the colleagues of NVM-DP Dept., A. Maurelli, F. Piazza and L. Fumagalli. References [1] Young-Don Bae et al., A Single-Chip Programmable Platform Base on A Multithreaded Processor and Configurable Logic Clusters, ISSCC Digest of Technical Papers, pp , Feb. 22. [2] Zhang et al., A 1V Heterogeneous Reconfigurable Processor IC for Baseband Wireless Applications, ISSCC Digest of Technical Papers, pp 68-69,488, Feb IEEE International Solid-State Circuits Conference /3/$ IEEE

2 ISSCC 23 / February 19, 23 / Salon 1-6 / 4:45 PM Extensible Microprocessor Processor INTERFACE (PIF) 64 bit PIF BUS PIF/AHB BRIDGE 48 KB SRAM 64 bit AHB BUS Memory RAM ROM/FLASH ADC Power Block DFT PMA module module 1 module 2 module 3 2 Instruction Extension BUS General Purpose I/O Lines Interrupt Manager Interrupt Instruction Extension Master/Slave AHB Embedded FPGA General Purpose I/O Programmable General Purpose I/O DMA FPGA Programming Dual Buffer General Purpose Registers FP CP DP Flash Memory 1KB Dual Buffer 64 bit APB BUS PC Parallel PC Parallel AHB/APB Bridge I2C Master I2C BUS 128 bit DP CP FP Data Code FPGA µp interface 8 bit µp Figure 2.7.1: System architecture. Figure 2.7.2: Flash memory architecture. Microprocessor Register File Processor & AHB Bridge 64 bit AHB Bus 64 bit AHB CP 64 bit CP 64 bit AHB DP 64 bit DP 512 Bytes Page Buffer 2x64 bit + 1x Flash Memory s 6x4 128 bit Flash Memory Crossbar Flash Memory Controller Logic 4x16384x128 bit Memory Module 64 bit AHB AHB DMA FP FPGA PI Register 63 4 Segments x 4 Segments Pipeline Register Result Register 64 bit Aligned Address 64 bit Load µprocessor Load Unit 8 Issue/8-bit L2 Distance Root Reg. + 1 > << 1 Result Register >> Remainder Reg. Number Reg. << 2 >> 3 >> Fixed Point square root Figure 2.7.3: System memory hierarchy. Figure 2.7.4: Added DSP instructions examples. Process TECHNOLOGY AND DEVICE CHARACTERISTICS.18µm 2P 6M CMOS Tunneling oxide: 1nm Flash cell size:.35µm 2 Flash Memory (4x) SRAM memory Chip size 8.4x8.4mm 2 e-fpga size 8.2mm 2 Customizable I/O 256Kb x 9 Sectors Word: 128b Program Throughput: 1MB/s Typ. Read Rate: 4MB/s I$: 8kB (64b wide) D$: 8kB (64b wide) Buffers: 4x256B (8b wide) 24 general-purpose inputs 24 general-purpose outputs (tristate) 8 general-purpose bidirs Power supply V (I/O), V (core) Figure 2.7.5: Benchmarks at 1 MHz. Figure 2.7.6: Chip characteristics. 23 IEEE International Solid-State Circuits Conference /3/$ IEEE

3 2 Figure 2.7.7: Chip micrograph. 23 IEEE International Solid-State Circuits Conference /3/$ IEEE

4 Extensible Microprocessor Processor INTERFACE (PIF) 64 bit PIF BUS PIF/AHB BRIDGE 48 KB SRAM Memory RAM ROM/FLASH 64 bit AHB BUS Interrupt Manager Master/Slave AHB DMA FP CP DP Flash Memory AHB/APB Bridge Instruction Extension BUS Interrupt Instruction Extension Embedded FPGA General Purpose I/O FPGA Programming Dual Buffer 1KB Dual Buffer 64 bit APB BUS General Purpose I/O Lines Programmable General Purpose I/O General Purpose Registers PC Parallel PC Parallel I2C Master I2C BUS Figure 2.7.1: System architecture. 23 IEEE International Solid-State Circuits Conference /3/$ IEEE

5 ADC Power Block DFT PMA module module 1 module 2 module bit DP CP FP Data Code FPGA µp interface 8 bit µp Figure 2.7.2: Flash memory architecture. 23 IEEE International Solid-State Circuits Conference /3/$ IEEE

6 Microprocessor Register File Processor & AHB Bridge 64 bit AHB Bus FPGA PI 64 bit AHB 64 bit AHB CP 64 bit CP 64 bit AHB DP 64 bit DP 512 Bytes Page Buffer AHB DMA FP 2x64 bit + 1x Flash Memory s 6x4 128 bit Flash Memory Crossbar Flash Memory Controller Logic 4x16384x128 bit Memory Module Figure 2.7.3: System memory hierarchy. 23 IEEE International Solid-State Circuits Conference /3/$ IEEE

7 Register Root Reg. Remainder Reg. Number Reg. 64 bit Aligned Address 64 bit Load µprocessor Load Unit + 1 >> 1 << 2 >> 3 >> 2 4 Segments 4 Segments + - > - x 63 Pipeline Register Result Register 8 Issue/8-bit L2 Distance << 1 Result Register Fixed Point square root Figure 2.7.4: Added DSP instructions examples. 23 IEEE International Solid-State Circuits Conference /3/$ IEEE

8 Figure 2.7.5: Benchmarks at 1 MHz. 23 IEEE International Solid-State Circuits Conference /3/$ IEEE

9 Process TECHNOLOGY AND DEVICE CHARACTERISTICS.18µm 2P 6M CMOS Tunneling oxide: 1nm Flash cell size:.35µm 2 Flash Memory (4x) SRAM memory 256Kb x 9 Sectors Word: 128b Program Throughput: 1MB/s Typ. Read Rate: 4MB/s I$: 8kB (64b wide) D$: 8kB (64b wide) Buffers: 4x256B (8b wide) Chip size 8.4x8.4mm 2 e-fpga size 8.2mm 2 Customizable I/O Power supply 24 general-purpose inputs 24 general-purpose outputs (tristate) 8 general-purpose bidirs V (I/O), V (core) Figure 2.7.6: Chip characteristics. 23 IEEE International Solid-State Circuits Conference /3/$ IEEE

10 Figure 2.7.7: Chip micrograph. 23 IEEE International Solid-State Circuits Conference /3/$ IEEE