LVTTL/TTL-to-Differential LVPECL/PECL Translators
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1 9-2377; Rev 0; 4/02 LVTTL/TTL-to-Differential LVPECL/PECL General Description The LVTTL/TTL-to-differential LVPECL/PECL translators are designed for highspeed communication signal and clock driver applications. The MAX9370/ are dual LVTTL/TTL-to-LVPECL/PECL translators that operate in excess of GHz. The MAX937 is a single translator. The MAX9370/MAX937 operate over a wide 3.0V to 5.25V supply range, allowing high-performance clock or data distribution in systems with a nominal 3.3V or 5.0V supply. The is designed to operate from 3.0V to 3.6V. The devices default to output high if the input is disconnected. They feature low 270ps propagation delay. The employ industry-standard flow-through pinouts. These devices are specified for operation from -40 C to +85 C, and are offered in space-saving, 8-pin SOT23, µmax, and SO packages. Precision Clock/Data Level Translation Central Office Clock Distribution DSLAM/DLC Base Station Mass Storage Applications Pin Configurations/Functional Diagrams appears at end of data sheet. Features Guaranteed GHz Operating Frequency at 600mV Differential Output 270ps Propagation Delay 0ps Output-to-Output Skew (MAX9370/) Wide Supply Range: 3.0V to 5.25V (MAX9370/MAX937) ESD Protection > 2kV (Human Body Model) Output High with Input Open Available in Small 8-Pin SOT23, µmax, and SO Packages Improved Upgrades to MC00EL22, MC00EPT20, MC00EPT22 Ordering Information PART TEMP RANGE PIN-PACKAGE MAX9370EKA-T* -40 C to +85 C 8 SOT23-8 MAX9370EUA* -40 C to +85 C 8 µmax MAX9370ESA -40 C to +85 C 8 SO MAX937EKA-T* -40 C to +85 C 8 SOT23-8 MAX937EUA* -40 C to +85 C 8 µmax MAX937ESA -40 C to +85 C 8 SO EKA-T* -40 C to +85 C 8 SOT23-8 EUA* -40 C to +85 C 8 µmax ESA -40 C to +85 C 8 SO *Future product contact factory for availability. Typical Operating Circuit MAX9370 MAX937 Q_ Z 0 = 50Ω PECL/LVPECL RECEIVER TTL/LVTTL INPUT D Q_ Z 0 = 50Ω 50Ω 50Ω 2.0V Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at
2 ABSOLUTE MAXIMUM RATINGS V CC to GND (MAX9370/MAX937) V to +5.5V V CC to GND () V to +4.0V D_ to GND V to (V CC + 0.3V) Q_, Q_ to GND V to (V CC + 0.3V) Continuous Output Current...50mA Surge Output Current...00mA Junction-to-Ambient Thermal Resistance in Still Air 8-Pin SOT C/W 8-Pin µmax C/W 8-Pin SO C/W Junction-to-Ambient Thermal Resistance with 500LFPM Airflow 8-Pin SOT C/W 8-Pin µmax C/W 8-Pin SO C/W Junction-to-Case Thermal Resistance 8-Pin SOT C/W 8-Pin µmax C/W 8-Pin SO C/W Continuous Power Dissipation (T A = +70 C) 8-Pin SO (derate 5.9mW/ C above +70 C)...470mW 8-Pin µmax (derate 4.5mW/ C above +70 C)...362mW 8-Pin SOT23 (derate 8.9mW/ C above +70 C)...74mW Operating Temperature Range C to +85 C Junction Temperature C Storage Temperature Range C to +50 C Soldering Temperature (0s) C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (V CC = 3.0V to 5.25V for MAX9370/MAX937, V CC = 3.0V to 3.6V for, outputs terminated with 50Ω ±% to 2.0V. Typical values are at V CC = 3.3V, V IH = 2.4V, V IL = 0.4V, unless otherwise noted.) (Notes, 2, 3) PARAMETER SYMBOL CONDITIONS LVTTL INPUTS (D_) Input High Input Low Input Low Current Input High Current Input Clamp -40 C +25 C +85 C MIN TYP MAX MIN TYP MAX MIN TYP MAX V IH V V IL V I IL V D = 0.5V µa I IH V D = 2.7V V D = V CC, MAX9370/ MAX937 V D = V CC, LVPECL/PECL OUTPUTS (Q_, Q_) Output High Output Low V OH V OL I IL or I IH = 8mA V MAX9370 MAX937/ MAX9370 MAX937/ UNITS µa V V 2
3 DC ELECTRICAL CHARACTERISTICS (continued) (V CC = 3.0V to 5.25V for MAX9370/MAX937, V CC = 3.0V to 3.6V for, outputs terminated with 50Ω ±% to 2.0V. Typical values are at V CC = 3.3V, V IH = 2.4V, V IL = 0.4V, unless otherwise noted.) (Notes, 2, 3) PA R A M ET ER SYMBOL CONDITIONS Differential Output Swing (V OH - V OL ) SUPPLY CURRENT Power-Supply Current (Note 4) -40 C +25 C +85 C MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS mv I CC MAX9370/ MAX AC ELECTRICAL CHARACTERISTICS (V CC = 3.0V to 5.25V for MAX9370/MAX937, V CC = 3.0V to 3.6V for, outputs terminated with 50Ω ±% to 2.0V, input frequency.0ghz, input transition time = 25ps (20% to 80%), V IH = 2.0V, V IL = 0.8V. Typical values are at V CC = 3.3V, V IH = 2.4V, V IL = 0.4V, unless otherwise noted.) (Note 5) PARAMETER SYMBOL CONDITIONS Maximum Toggle Frequency Input-to- Output Propagation Delay Output-to- Output Skew Output Rise/ Fall Time Added Deterministic Jitter Added Random Jitter f MAX V OH - V OL 600mV -40 C +25 C +85 C MIN TYP MAX MIN TYP MAX MIN TYP MAX ma UNITS GHz t PLH, t PHL Figure ps t SKQQ MAX9370/ (Note 6) ps t R, t F Figure ps t DJ Gbps PRBS pattern (Note 7) t RJ GHz clock (Note 7) ps (P-P) ps (RMS) Note : Measurements are made with the device in thermal equilibrium. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 3: DC parameters are production tested at T A = +25 C. DC limits are guaranteed by design and characterization over the full operating temperature range. Note 4: All pins are open except V CC and GND. Note 5: Guaranteed by design and characterization. Limits are set to ±6 sigma. Note 6: Measured between outputs of the same part at the signal crossing points under identical conditions for a same-edge transition. Note 7: Device jitter added to the input signal. 3
4 Typical Operating Characteristics (MAX937, V CC = 3.3V, V IH = 2.4V, V IL = 0.4V, outputs terminated with 50Ω to 2V, input transition time = 25ps (20% to 80%), T A = +25 C, unless otherwise noted.) SUPPLY CURRENT (ma) SUPPLY CURRENT vs. TEMPERATURE ALL INPUTS AND OUTPUTS ARE OPEN MAX9370/ MAX TEMPERATURE ( C) MAX9370 toc0 DIFFERENTIAL OUTPUT VOLTAGE (mv) PROPAGATION DELAY (ps) DIFFERENTIAL OUTPUT VOLTAGE (V OH - V OL ) vs. FREQUENCY FREQUENCY (GHz) PROPAGATION DELAY vs. TEMPERATURE MAX9370 toc02 MAX9370 toc04 TRANSITION TIME (ps) TRANSITION TIME vs. TEMPERATURE FALLING EDGE RISING EDGE TEMPERATURE ( C) f = 00MHz MAX9370 toc TEMPERATURE ( C) 4
5 SO µmax PIN SOT23 NAME Pin Description for the MAX9370/ FUNCTION 8 Q0 Noninverting Differential LVPECL/PECL Output 0. Typically terminate with 50Ω resistor to 2V. 2 7 Q0 Inverting Differential LVPECL/PECL Output 0. Typically terminate with 50Ω resistor to 2V. 3 6 Q Noninverting Differential LVPECL/PECL Output. Typically terminate with 50Ω resistor to 2V. 4 5 Q Inverting Differential LVPECL/PECL Output. Typically terminate with 50Ω resistor to 2V. 5 2 GND Ground. Provide a low-impedance connection to ground plane. 6 4 D LVTTL/TTL Input. LVTTL/TTL input for translator corresponding to output Q and Q. 7 3 D0 LVTTL/TTL Input 0. LVTTL/TTL input for translator corresponding to output Q0 and Q0. 8 V CC Positive Supply. Bypass V CC to GND with 0.µF and 0.0µF ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. SO µmax PIN SOT23 NAME, 4, 6 4, 5, 8 No Connection. No internal connection. Pin Description for the MAX937 FUNCTION 2 7 Q Noninverting Differential LVPECL/PECL Output. Typically terminate with 50Ω resistor to 2V. 3 6 Q Inverting Differential LVPECL/PECL Output. Typically terminate with 50Ω resistor to 2V. 5 2 GND Ground. Provide a low-impedance connection to ground plane. 7 3 D LVTTL/TTL Input 8 V CC Positive Supply. Bypass V CC to GND with 0.µF and 0.0µF ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. Detailed Description The LVTTL/TTL-to-differential LVPECL/PECL translators are designed for highspeed communication signal and clock driver applications. The MAX9370/ are dual LVTTLto-LVPECL/PECL translators that operate in excess of GHz. The MAX937 is a single translator. The MAX9370/MAX937 operate over a wide 3.0V to 5.25V supply range, allowing high-performance clock or data distribution in systems with a nominal 3.3V or 5.0V supply. The is optimized for 3.0V to 3.6V operation. These devices feature low 270ps propagation delay and 40ps peak-to-peak deterministic jitter. Inputs and Outputs The inputs accept standard LVTTL/TTL levels. The input has pullup circuitry that drives the outputs to a differential high if the inputs are open. The outputs are differential LVPECL/PECL levels. Applications Information Output Termination Terminate outputs with 50Ω to 2V or use an equivalent Thevenin termination. Use the same terminate on each output for the lowest output-to-output skew. When a single-ended signal is taken from a differential output, terminate both outputs. For example, if Q is used as a single-ended output, terminate both Q and Q. 5
6 Ensure that the output currents do not exceed the continuous safe output current limit or surge output current limit as specified in the Absolute Maximum Ratings table. Under all operating conditions, the device s total thermal limits should be observed. Supply Bypassing Bypass V CC to GND with high-frequency surface-mount ceramic 0.µF and 0.0µF capacitors in parallel and as close to the device as possible, with the 0.0µF capacitor closest to the device. Use multiple parallel vias to minimize parasitic inductance. D_ 50% t PLH PC Board Traces Input and output trace characteristics affect the performance of the. Connect each differential output to a 50Ω characteristic impedance trace. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50Ω characteristic impedance through connectors and across cables. Reduce skew within a differential pair by matching the electrical length of the traces. TRANSISTOR COUNT: 358 PROCESS: Bipolar 50% t PHL Chip Information V IH V IL Q_ Q_ V OH - V OL V OH V OL 80% V OH - V OL 80% 0V (DIFFERENTIAL) Q_ - Q_ 20% V OH - V OL 20% t R t F Figure. Input-to-Output Propagation Delay and Transition Timing Diagram 6
7 Q Q Q0 Q0 Q MAX937 SO/µMAX MAX9370/ Pin Configurations/Functional Diagrams 8 V CC V CC MAX D GND 2 7 Q 6 5 GND D Q SOT23 MAX9370/ 8 V CC V CC 8 Q0 7 D0 GND 2 7 Q0 6 D D0 3 6 Q Q 4 5 GND D 4 5 Q SO/µMAX SOT23 7
8 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to SOT23, 8L.EPS 0.6±0. 0.6±0. 8 ÿ 0.50±0. D E H 4X S BOTTOM VIEW 8 DIM A A INCHES MIN MAX BSC A b c D e E 0.6 H 0.88 L 0.06 α 0 S BSC MILLIMETERS MIN MAX BSC BSC 8LUMAXD.EPS TOP VIEW A2 A A e b c L α FRONT VIEW SIDE VIEW PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, 8L umax/usop APPROVAL DOCUMENT CONTROL NO. REV J 8
9 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to 9LUCSP, 3x3.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 20 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
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Rev. 4 24 February 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an octal positive-edge triggered D-type flip-flop. The device features clock (CP)
±15kV ESD-Protected, 1µA, 250kbps, 3.3V/5V, Dual RS-232 Transceivers with Internal Capacitors
19-1473; Rev 2; 8/4 ±15k ESD-Protected, 1µA, 25kbps, 3.3/5, Dual General Description The are EIA/TIA-232 and.28/.24 communications interfaces with automatic shutdown/ wake-up features, high data-rate capabilities,
74LS193 Synchronous 4-Bit Binary Counter with Dual Clock
74LS193 Synchronous 4-Bit Binary Counter with Dual Clock General Description The DM74LS193 circuit is a synchronous up/down 4-bit binary counter. Synchronous operation is provided by having all flip-flops
High Speed, Low Cost, Triple Op Amp ADA4861-3
High Speed, Low Cost, Triple Op Amp ADA486-3 FEATURES High speed 73 MHz, 3 db bandwidth 625 V/μs slew rate 3 ns settling time to.5% Wide supply range: 5 V to 2 V Low power: 6 ma/amplifier. db flatness:
Precision, Unity-Gain Differential Amplifier AMP03
a FEATURES High CMRR: db Typ Low Nonlinearity:.% Max Low Distortion:.% Typ Wide Bandwidth: MHz Typ Fast Slew Rate: 9.5 V/ s Typ Fast Settling (.%): s Typ Low Cost APPLICATIONS Summing Amplifiers Instrumentation
CA723, CA723C. Voltage Regulators Adjustable from 2V to 37V at Output Currents Up to 150mA without External Pass Transistors. Features.
CA73, CA73C Data Sheet April 1999 File Number 788. Voltage Regulators Adjustable from V to 37V at Output Currents Up to 1mA without External Pass Transistors The CA73 and CA73C are silicon monolithic integrated
Symbol Parameters Units Frequency Min. Typ. Max. 850 MHz 14.8 16.3 17.8
Product Description Sirenza Microdevices SGC-689Z is a high performance SiGe HBT MMIC amplifier utilizing a Darlington configuration with a patented active-bias network. The active bias network provides
MM74HC174 Hex D-Type Flip-Flops with Clear
Hex D-Type Flip-Flops with Clear General Description The MM74HC174 edge triggered flip-flops utilize advanced silicon-gate CMOS technology to implement D-type flipflops. They possess high noise immunity,
LM117 LM317A LM317 3-Terminal Adjustable Regulator
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DM74LS193 Synchronous 4-Bit Binary Counter with Dual Clock
September 1986 Revised March 2000 DM74LS193 Synchronous 4-Bit Binary Counter with Dual Clock General Description The DM74LS193 circuit is a synchronous up/down 4-bit binary counter. Synchronous operation
74F257A Quad 2-line to 1-line selector/multiplexer, non-inverting (3-State)
INTEGRATED CIRCUITS Quad 2-line to 1-line selector/multiplexer, non-inverting (3-State) 1995 Mar 31 IC15 Data Handbook Philips Semiconductors Quad 2-line to 1-line selector/multiplexer, non-inverting (3-State)
VITESSE SEMICONDUCTOR CORPORATION. 16:1 Multiplexer. Timing Generator. CMU x16
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74F74 Dual D-Type Positive Edge-Triggered Flip-Flop
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74HC165; 74HCT165. 8-bit parallel-in/serial out shift register
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ABRIDGED DATA SHEET EVALUATION KIT AVAILABLE
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LM386 Low Voltage Audio Power Amplifier
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MM74HC4538 Dual Retriggerable Monostable Multivibrator
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74HC138; 74HCT138. 3-to-8 line decoder/demultiplexer; inverting
Rev. 6 28 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive
Data Sheet. HFBR-0600Z Series SERCOS Fiber Optic Transmitters and Receivers
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74HC4040; 74HCT4040. 12-stage binary ripple counter
Rev. 5 3 February 2016 Product data sheet 1. General description 2. Features and benefits 3. Applications 4. Ordering information The is a with a clock input (CP), an overriding asynchronous master reset
ICL232. +5V Powered, Dual RS-232 Transmitter/Receiver. Description. Features. Ordering Information. Applications. Functional Diagram.
ICL August V Powered, Dual RS Transmitter/Receiver Features Meets All RSC and V. Specifications Requires Only Single V Power Supply Onboard Voltage Doubler/Inverter Low Power Consumption Drivers ±V Output
HCF4056B BCD TO 7 SEGMENT DECODER /DRIVER WITH STROBED LATCH FUNCTION
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PS323. Precision, Single-Supply SPST Analog Switch. Features. Description. Block Diagram, Pin Configuration, and Truth Table. Applications PS323 PS323
Features ÎÎLow On-Resistance (33-ohm typ.) Minimizes Distortion and Error Voltages ÎÎLow Glitching Reduces Step Errors in Sample-and-Holds. Charge Injection, 2pC typ. ÎÎSingle-Supply Operation (+2.5V to
Low-power configurable multiple function gate
Rev. 7 10 September 2014 Product data sheet 1. General description The provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the
MAX14759/MAX14761/MAX14763 Above- and Below-the-Rails Low On-Resistance Analog Switches
19-651; Rev ; 9/11 /MX14761/ General Description The /MX14761/ analog switches are capable of passing bipolar signals that are beyond their supply rails. These devices operate from a single +3.V to +5.5V
74HC107; 74HCT107. Dual JK flip-flop with reset; negative-edge trigger
Rev. 5 30 November 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual negative edge triggered JK flip-flop featuring individual J and K inputs,
74HC02; 74HCT02. 1. General description. 2. Features and benefits. Ordering information. Quad 2-input NOR gate
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PART. MAX5420CEUA -40 C to +85 C 8 µmax 0.5% MAX5421CEUB -40 C to +85 C 10 µmax 0.5% Maxim Integrated Products 1
9-223; Rev 2; 2/5 Digitally Programmable Precision General Description The MX542 and MX542 are digitally programmable precision voltage dividers optimized for use in digitally programmable gain amplifier
30V Internal Switch LCD Bias Supply
19-1666; Rev 1; 1/3 3V Internal Switch LCD Bias Supply General Description The boost converter contains a.5a internal switch in a tiny 6-pin SOT23 package. The IC operates from a +2.4V to +5.5V supply
CMOS Switched-Capacitor Voltage Converters ADM660/ADM8660
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Rev. 7 29 February 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a. It decodes four binary weighted address inputs (A0 to A3) to sixteen mutually
DM74LS05 Hex Inverters with Open-Collector Outputs
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3-to-8 line decoder, demultiplexer with address latches
Rev. 7 29 January 2016 Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The is specified in compliance with JEDEC
DALLAS DS1233 Econo Reset. BOTTOM VIEW TO-92 PACKAGE See Mech. Drawings Section on Website
5V EconoReset www.maxim-ic.com FEATURES Automatically restarts microprocessor after power failure Monitors pushbutton for external override Internal circuitry debounces pushbutton switch Maintains reset
Features. Ordering Information. * Underbar marking may not be to scale. Part Identification
MIC86 Teeny Ultra Low Power Op Amp General Description The MIC86 is a rail-to-rail output, input common-mode to ground, operational amplifier in Teeny SC7 packaging. The MIC86 provides 4kHz gain-bandwidth
Maxim Integrated Products 1
19-542; Rev 1; 5/6 Stereo Volume Control General Description The dual, 4kΩ logarithmic taper volume control features a debounced up/down interface for use with a simple rotary encoder without using a microcontroller
www.jameco.com 1-800-831-4242
Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. LF411 Low Offset, Low Drift JFET Input Operational Amplifier General Description
CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset
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