LVTTL/TTL/CMOS-to-Differential LVECL/ ECL Translators
|
|
|
- Arlene Rich
- 7 years ago
- Views:
Transcription
1 ; Rev 2; 12/08 EVALUATION KIT AVAILABLE LVTTL/TTL/CMOS-to-Differential LVECL/ General Description The are low-skew, single LVTTL/ TTL/CMOS-to-differential LVECL/ECL translators designed for high-speed signal and clock driver applications. For interfacing to LVTTL/TTL/CMOS input signals, these devices operate over a 3.0V to 5.5V supply range, allowing high-performance clock or data distribution. For interfacing to differential LVECL/ECL output signals, these devices operate from a V to -5.5V supply. The MAX9360 is a 3.3V LVTTL/CMOS-to-LVECL/ECL translator that operates at a typical speed of 3GHz. The MAX9361 is a 5V TTL/CMOS-to-LVECL/ECL translator that operates at a typical speed of 1.3GHz. Both devices can be used to drive either LVECL devices or standard ECL devices with a negative supply range of V to -5.5V. The devices default to high if the input is disconnected, and feature ultra-low propagation delay: 440ps for the MAX9360, 810ps for the MAX9361. Clock/Data-Level Translation Applications Features Output High with Input Open V to -5.5V LVECL/ECL Operation ESD Protection > 2kV (Human Body Model) 3.0V to 3.6V LVTTL/CMOS Operation (MAX9360) Improved Second Source of the MC100EPT24 Low 13.8mA (typ) I EE Supply Current 440ps (typ) Propagation Delay > 300mV Output at 1GHz 4.5V to 5.5V TTL Operation (MAX9361) Improved Second Source of the MC100ELT24 Low 6.6mA (typ) I EE Supply Current 600ps (typ) Propagation Delay > 300mV Output at 250MHz PART Ordering Information TEMP RANGE PIN- PACKAGE TOP MARK MAX9360EKA-T -40 C to +85 C 8 SOT23 AAJI MAX9360ESA -40 C to +85 C 8 SO MAX9361EKA-T -40 C to +85 C 8 SOT23 AAJJ MAX9361ESA -40 C to +85 C 8 SO Pin Configurations TOP VIEW D 1 8 GND V EE 1 8 V CC V EE 2 7 D 2 7 N.C. 3 6 N.C. 3 6 N.C. 4 MAX9360/ MAX V CC N.C. 4 MAX9360/ MAX GND SOT23 SO Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim s website at
2 ABSOLUTE MAXIMUM RATINGS V CC to GND V to +6V V EE to GND...-6V to +0.3V D to GND V to (V CC + 0.3V) Continuous Output Current...50mA Surge Output Current...100mA Junction-to-Ambient Thermal Resistance in Still Air 8-Pin SOT C/W 8-Pin SO C/W Junction-to-Ambient Thermal Resistance with 500LFPM Airflow 8-Pin SOT C/W 8-Pin SO C/W Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS MAX9360 Junction-to-Case Thermal Resistance 8-Pin SOT C/W 8-Pin SO C/mW Continuous Power Dissipation (T A = +70 C) 8-Pin SOT23 (derate 8.9mW/ C above +70 C)...714mW 8-Pin SO (derate 5.9mW/ C above +70 C)...470mW Operating Temperature Range C to +85 C Junction Temperature C Storage Temperature Range C to +150 C ESD Protection Human Body Model (D,, )...> 2kV Soldering Temperature (10s) C (V CC = 3.0V to 3.6V, V EE = V to -5.5V, V GND = 0, outputs terminated with 50Ω ±1% to -2.0V. Typical values are at V CC = 3.3V, V IH = 2.0V, V IL = 0.8V, unless otherwise noted.) (Notes 1, 2, 3) PARAMETER SYMBOL CONDITIONS LVTTL INPUT (D) 0 C (SOT23) +25 C +85 C -40 C (SO) MIN TYP MAX MIN TYP MAX MIN TYP MAX V IN = 2.7V Input High Current I IH V IN = V CC UNITS µa Input Low Current I IL V IN = 0.5V µa Input Clamp Voltage V IK I IN = -18mA V Input High Voltage V IH V Input Low Voltage V IL V LVECL/ECL OUTPUTS (, ) Output High Voltage V OH V Output Low Voltage V OL V Differential Output Swing (V OH - V OL ) V OH - V OL mv Power-Supply Current Internal Chip Current I CC (Note 4) ma I EE (Note 4) ma 2
3 DC ELECTRICAL CHARACTERISTICS MAX9361 (V CC = 4.5V to 5.5V, V EE = V to -5.5V, V GND = 0, outputs terminated with 50Ω ±1% to -2.0V. Typical values are at V CC = 5V, V IH = 2.0V, V IL = 0.8V, unless otherwise noted.) (Notes 1, 2, 3) PARAMETER SYMBOL CONDITIONS TTL INPUT (D) -40 C (SO) +25 C +85 C MIN TYP MAX MIN TYP MAX MIN TYP MAX V IN = 2.7V Input High Current I IH V IN = V CC Input Low Current I IL V IN = 0.5V µa Input Clamp Voltage V IK I IN = -18mA V Input High Voltage V IH V Input Low Voltage V IL V LVECL/ECL OUTPUTS (, ) Output High Voltage V OH V Output Low Voltage V OL V Differential Output Swing (V OH - V OL ) POWER SUPPLY UNITS V OH - V OL mv µa Power-Supply Current Internal Chip Current I CC (Note 4) ma I EE (Note 4) ma 3
4 AC ELECTRICAL CHARACTERISTICS MAX9360 (V CC = 3.0V to 3.6V, V EE = V to -5.5V, V GND = 0, outputs terminated with 50Ω ±1% to -2.0V, input frequency = 1.0GHz, input transition time = 125ps (20% to 80%). Typical values are at V CC = 3.3V, V IH = 2.0V, V IL = 0.8V, unless otherwise noted.) (Note 5) PARAMETER SYMBOL CONDITIONS Maximum Toggle Frequency Input-to-Output Propagation Delay Output Rise/Fall Time Added Deterministic Jitter Added Random Jitter 0 C (SOT23) +25 C +85 C -40 C (SO) MIN TYP MAX MIN TYP MAX MIN TYP MAX V OH - V OL 300mV f MAX V OH - V OL 500mV t PLHD, t PHLD Figure ps t R, t F Figure ps t DJ t RJ 2Gbps PRBS pattern (Note 6) 1.0GHz clock pattern (Note 6) UNITS GHz ps (P-P) ps (RMS) AC ELECTRICAL CHARACTERISTICS MAX9361 (V CC = 4.5V to 5.5V, V EE = V to -5.5V, V GND = 0, outputs terminated with 50Ω ±1% to -2.0V, input frequency = 100MHz, input transition time = 125ps (20% to 80%). Typical values are at V CC = 5.0V, V IH = 2.0V, V IL = 0.8V, unless otherwise noted.) (Note 5) PARAMETER SYMBOL CONDITIONS Maximum Toggle Frequency Input-to-Output Propagation Delay Output Rise/Fall Time -40 C +25 C +85 C MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS V OH - V OL 300mV f MAX V OH - V OL 500mV t PLHD, t PHLD Figure ps t R, t F Figure ps MHz Added Deterministic Jitter t DJ 200Mbps PRBS pattern (Note 6) ps (P-P) Added Random Jitter t RJ 100MHz clock pattern (Note 6) ps (RMS) Note 1: Measurements are made with the device in thermal equilibrium. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 3: DC parameters are production tested at +25 C. DC limits are guaranteed by design and characterization over the full operating temperature range. Note 4: All pins are open except V CC, V EE, and GND. Note 5: Guaranteed by design and characterization. Limits are set to ±6 sigma. Note 6: Device jitter added to the input signal. 4
5 Typical Operating Characteristics (MAX9360: V CC = 3.3V and V EE = -5V, V IH = 2.0V, V IL = 0.8V, T A = +25 C, outputs terminated with 50Ω to -2V, input frequency = 1GHz, input transition time = 125ps (20% to 80%), unless otherwise noted.) SUPPLY CURRENT (ma) SUPPLY CURRENT vs. TEMPERATURE I EE I CC TEMPERATURE ( C) MAX9360 toc01 OUTPUT AMPLITUDE (mv) OUTPUT AMPLITUDE vs. FREUENCY FREUENCY (MHz) MAX9360 toc02 TRANSITION TIME (ps) TRANSITION TIME vs. TEMPERATURE t R t F MAX9360 toc03 PROPAGATION DELAY (ps) PROPAGATION DELAY vs. TEMPERATURE t PLHD 425 t PHLD MAX9360 toc TEMPERATURE ( C) TEMPERATURE ( C) 5
6 SO PIN SOT23 NAME FUNCTION Pin Description 1 2 V EE Place the capacitors as close as possible to the device with the smaller value capacitor Negative Supply Voltage. Bypass V EE to GND with 0.1µF and 0.01µF ceramic capacitors. closest to the device. 2 1 D LVTTL/CMOS Input for MAX9360. TTL/CMOS input for MAX , 4 3, 4 N.C. No Connect. Connect to GND. 5 8 GND Ground 6 7 Inverting Differential LVECL/ECL Output. Typically terminate with 50Ω resistor to -2V. 7 6 Noninverting Differential LVECL/ECL Output. Typically terminate with 50Ω resistor to -2V. 8 5 V CC Place the capacitors as close as possible to the device with the smaller value capacitor Positive Supply Voltage. Bypass V CC to GND with 0.1µF and 0.01µF ceramic capacitors. closest to the device. V IH 50% 50% D t PLH t PHL V IL V OH SINGLE-ENDED WAVEFORMS V OH - V OL V OL 80% V OH - V OL 80% 0 (DIFFERENTIAL) DIFFERENTIAL WAVEFORM - 20% V OH - V OL 20% t R t F Figure 1. Input-to-Output Propagation Delay and Transition Timing Diagram 6
7 Detailed Description The are low-skew, single LVTTL/ CMOS/TTL-to-differential LVECL/ECL translators designed for high-speed signal and clock driver applications. For interfacing to LVTTL/TTL/CMOS input signals, these devices operate over a 3.0V to 5.5V supply range, allowing high-performance clock or data distribution in systems with a nominal 3.3V or 5.0V supply. For interfacing to differential LVECL/ECL output signals, these devices operate from a V to -5.5V supply. The MAX9360 is a 3.3V LVTTL/CMOS-to-LVECL/ECL translator that operates at typical speeds of 3GHz. The MAX9361 is a 5V TTL/CMOS-to-LVECL/ECL translator that operates at typical speeds of 1.3GHz. Both devices can be used to drive either LVECL devices or standard ECL devices with a negative supply range of V to -5.5V. Input The inputs accept standard LVTTL/ TTL/CMOS levels. The input has pullup circuitry that drives the outputs to a differential high if the inputs are open. Differential Output Output levels are referenced to GND and are considered ECL or LVECL, depending on the level of the V EE supply. With GND connected to zero and V EE at -4.2V to -5.5V, the outputs are ECL. The outputs are LVECL when GND is connected to zero and V EE is at V to -3.8V. Applications Information Supply Bypassing Bypass V CC and V EE to ground with high-frequency surface-mount ceramic 0.1µF and 0.01µF capacitors in parallel as close as possible to the device, with the 0.01µF value capacitor closest to the device. Use multiple parallel vias for low inductance. Traces Input and output trace characteristics affect the performance of the. Connect each signal of a differential output to a 50Ω characteristic impedance trace. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50Ω characteristic impedance through connectors and across cables. Reduce skew within a differential pair by matching the electrical length of the traces. On the MAX9360, if the input edge rate approaches the electrical length of the interconnect, then controlledimpedance transmission lines should be used for the input traces. Output Termination Terminate outputs through 50Ω to -2V or use an equivalent Thevenin termination. Terminate both outputs and use the same termination on each for the lowest outputto-output skew. When a single-ended signal is taken from a differential output, terminate both outputs. For example, if is used as a single-ended output, terminate both and. Ensure that the output currents do not exceed the continuous safe output current limit or surge output current limit as specified in the Absolute Maximum Ratings table. Under all operating conditions, the device s total thermal limits should be observed. PROCESS: Bipolar Chip Information Package Information For the latest package outline information and land patterns, go to PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 8 SOT23 K SO S
8 REVISION NUMBER REVISION DATE DESCRIPTION Revision History PAGES CHANGED 0 1/02 Initial release 1 7/ /08 Removed incorrect temperature range specified in the data sheet. 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
V CC TOP VIEW. f SSO = 20MHz to 134MHz (DITHERED)
19-013; Rev 1; 10/11 0MHz to 13MHz Spread-Spectrum General Description The is a spread-spectrum clock modulator IC that reduces EMI in high clock-frequency-based, digital electronic equipment. Using an
Push-Pull FET Driver with Integrated Oscillator and Clock Output
19-3662; Rev 1; 5/7 Push-Pull FET Driver with Integrated Oscillator General Description The is a +4.5V to +15V push-pull, current-fed topology driver subsystem with an integrated oscillator for use in
Spread-Spectrum Crystal Multiplier DS1080L. Features
Rev 1; 3/0 Spread-Spectrum Crystal Multiplier General Description The is a low-jitter, crystal-based clock generator with an integrated phase-locked loop (PLL) to generate spread-spectrum clock outputs
Cold-Junction-Compensated K-Thermocoupleto-Digital Converter (0 C to +1024 C)
19-2235; Rev 1; 3/02 Cold-Junction-Compensated K-Thermocoupleto-Digital General Description The performs cold-junction compensation and digitizes the signal from a type-k thermocouple. The data is output
EVALUATION KIT AVAILABLE Broadband, Two-Output, Low-Noise Amplifier for TV Tuner Applications MAX2130. Maxim Integrated Products 1
9-86; Rev ; 8/ EVALUATION KIT AVAILABLE Broadband, Two-Output, Low-Noise General Description The broadband, low-distortion, low-noise, two-output amplifier performs preamp, loop-out, and buffer functions
MC10SX1190. Fibre Channel Coaxial Cable Driver and Loop Resiliency Circuit
Fibre Channel Coaxial Cable Driver and Loop Resiliency Circuit Description The MC10SX1190 is a differential receiver, differential transmitter specifically designed to drive coaxial cables. It incorporates
MAX14760/MAX14762/MAX14764 Above- and Below-the-Rails Low-Leakage Analog Switches
19-652; Rev 1; 8/12 EVALUATION KIT AVAILABLE MAX1476// General Description The MAX1476// analog switches are capable of passing bipolar signals that are beyond their supply rails. These devices operate
1 TO 4 CLOCK BUFFER ICS551. Description. Features. Block Diagram DATASHEET
DATASHEET 1 TO 4 CLOCK BUFFER ICS551 Description The ICS551 is a low cost, high-speed single input to four output clock buffer. Part of IDT s ClockBlocks TM family, this is our lowest cost, small clock
Quad, Rail-to-Rail, Fault-Protected, SPST Analog Switches
19-2418; Rev ; 4/2 Quad, Rail-to-Rail, Fault-Protected, General Description The are quad, single-pole/single-throw (SPST), fault-protected analog switches. They are pin compatible with the industry-standard
ICS514 LOCO PLL CLOCK GENERATOR. Description. Features. Block Diagram DATASHEET
DATASHEET ICS514 Description The ICS514 LOCO TM is the most cost effective way to generate a high-quality, high-frequency clock output from a 14.31818 MHz crystal or clock input. The name LOCO stands for
INTEGRATED CIRCUITS. 74LVC08A Quad 2-input AND gate. Product specification IC24 Data Handbook. 1997 Jun 30
INTEGRATED CIRCUITS IC24 Data Handbook 1997 Jun 30 FEATURES Wide supply voltage range of 1.2 V to 3.6 V In accordance with JEDEC standard no. 8-1A Inputs accept voltages up to 5.5 V CMOS low power consumption
MADR-009269-0001TR. Single Driver for GaAs FET or PIN Diode Switches and Attenuators Rev. V1. Functional Schematic. Features.
Features High Voltage CMOS Technology Complementary Outputs Positive Voltage Control CMOS device using TTL input levels Low Power Dissipation Low Cost Plastic SOIC-8 Package 100% Matte Tin Plating over
On/Off Controller with Debounce and
19-4128; Rev ; 5/8 On/Off Controller with Debounce and General Description The is a pushbutton on/off controller with a single switch debouncer and built-in latch. It accepts a noisy input from a mechanical
ICS650-44 SPREAD SPECTRUM CLOCK SYNTHESIZER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS650-44 Description The ICS650-44 is a spread spectrum clock synthesizer intended for video projector and digital TV applications. It generates three copies of an EMI optimized 50 MHz clock
10/100/1000 Base-T Ethernet LAN Switch
19-377; Rev 2; 8/7 1/1/1 Base-T Ethernet LAN Switch General Description The MAX89/MAX891/MAX892 high-speed analog switches meet the needs of 1/1/1 Base-T applications. These devices switch the signals
The 74LVC1G11 provides a single 3-input AND gate.
Rev. 8 17 September 2015 Product data sheet 1. General description The provides a single 3-input AND gate. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
DG2302. High-Speed, Low r ON, SPST Analog Switch. Vishay Siliconix. (1-Bit Bus Switch with Level-Shifter) RoHS* COMPLIANT DESCRIPTION FEATURES
High-Speed, Low r ON, SPST Analog Switch (1-Bit Bus Switch with Level-Shifter) DG2302 DESCRIPTION The DG2302 is a high-speed, 1-bit, low power, TTLcompatible bus switch. Using sub-micron CMOS technology,
MADR-009443-0001TR. Quad Driver for GaAs FET or PIN Diode Switches and Attenuators. Functional Schematic. Features. Description. Pin Configuration 2
Features Functional Schematic High Voltage CMOS Technology Four Channel Positive Voltage Control CMOS device using TTL input levels Low Power Dissipation Low Cost 4x4 mm, 20-lead PQFN Package 100% Matte
MADR-009190-0001TR. Quad Driver for GaAs FET or PIN Diode Switches and Attenuators Rev. 4. Functional Schematic. Features.
Features High Voltage CMOS Technology Four Channel Positive Voltage Control CMOS device using TTL input levels Low Power Dissipation Low Cost Lead-Free SOIC-16 Plastic Package Halogen-Free Green Mold Compound
High-Speed, Low r ON, SPST Analog Switch (1-Bit Bus Switch)
High-Speed, Low r ON, SPST Analog Switch (1-Bit Bus Switch) DG2301 ishay Siliconix DESCRIPTION The DG2301 is a high-speed, 1-bit, low power, TTLcompatible bus switch. Using sub-micron CMOS technology,
2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX ICS557-06. Features
DATASHEET 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX ICS557-06 Description The ICS557-06 is a two to four differential clock mux designed for use in PCI-Express applications. The device selects one of the
Features. Modulation Frequency (khz) VDD. PLL Clock Synthesizer with Spread Spectrum Circuitry GND
DATASHEET IDT5P50901/2/3/4 Description The IDT5P50901/2/3/4 is a family of 1.8V low power, spread spectrum clock generators capable of reducing EMI radiation from an input clock. Spread spectrum technique
VITESSE SEMICONDUCTOR CORPORATION. 16:1 Multiplexer. Timing Generator. CMU x16
Features 16:1 2.488 Gb/s Multiplexer Integrated PLL for Clock Generation - No External Components 16-bit Wide, Single-ended, ECL 100K Compatible Parallel Data Interface 155.52 MHz Reference Clock Frequency
TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER. Features
DATASHEET ICS280 Description The ICS280 field programmable spread spectrum clock synthesizer generates up to four high-quality, high-frequency clock outputs including multiple reference clocks from a low-frequency
ICS650-01 SYSTEM PERIPHERAL CLOCK SOURCE. Description. Features. Block Diagram DATASHEET
DATASHEET ICS650-01 Description The ICS650-01 is a low-cost, low-jitter, high-performance clock synthesizer for system peripheral applications. Using analog/digital Phase-Locked Loop (PLL) techniques,
High-Speed, 5 V, 0.1 F CMOS RS-232 Driver/Receivers ADM202/ADM203
a FEATURES kb Transmission Rate ADM: Small (. F) Charge Pump Capacitors ADM3: No External Capacitors Required Single V Power Supply Meets EIA-3-E and V. Specifications Two Drivers and Two Receivers On-Board
8-bit binary counter with output register; 3-state
Rev. 3 24 February 2016 Product data sheet 1. General description The is an 8-bit binary counter with a storage register and 3-state outputs. The storage register has parallel (Q0 to Q7) outputs. The binary
+5 V Powered RS-232/RS-422 Transceiver AD7306
a FEATURES RS- and RS- on One Chip Single + V Supply. F Capacitors Short Circuit Protection Excellent Noise Immunity Low Power BiCMOS Technology High Speed, Low Skew RS- Operation C to + C Operations APPLICATIONS
R EXT THERMISTOR. Maxim Integrated Products 1
19-2219; Rev 0; 2/02 Thermistor-to-Digital Converter General Description The converts an external thermistor s temperature-dependent resistance directly into digital form. The thermistor and an external
74HC238; 74HCT238. 3-to-8 line decoder/demultiplexer
Rev. 4 27 January 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive
it4036f 120-ps Wideband Phase Delay Description Features Device Diagram Timing Diagram
Description The it436f is an ultra-wideband phase delay with an ECL topology to ensure high-speed operation that accepts either single-ended or differential data input. Its high output voltage, excellent
Low-Cost, Micropower, SC70/SOT23-8, Microphone Preamplifiers with Complete Shutdown
9-9; Rev ; 4/ Low-Cost, Micropower, SC7/SOT23-8, Microphone General Description The are micropower op amps optimized for use as microphone preamplifiers. They provide the ideal combination of an optimized
3-to-8 line decoder, demultiplexer with address latches
Rev. 7 29 January 2016 Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The is specified in compliance with JEDEC
DS1220Y 16k Nonvolatile SRAM
19-5579; Rev 10/10 NOT RECOENDED FOR NEW DESIGNS 16k Nonvolatile SRAM www.maxim-ic.com FEATURES 10 years minimum data retention in the absence of external power Data is automatically protected during power
ICS379. Quad PLL with VCXO Quick Turn Clock. Description. Features. Block Diagram
Quad PLL with VCXO Quick Turn Clock Description The ICS379 QTClock TM generates up to 9 high quality, high frequency clock outputs including a reference from a low frequency pullable crystal. It is designed
74HC377; 74HCT377. 1. General description. 2. Features and benefits. 3. Ordering information
Rev. 4 24 February 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an octal positive-edge triggered D-type flip-flop. The device features clock (CP)
74HC138; 74HCT138. 3-to-8 line decoder/demultiplexer; inverting
Rev. 6 28 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive
3-input EXCLUSIVE-OR gate. The 74LVC1G386 provides a 3-input EXCLUSIVE-OR function.
Rev. 02 3 September 2007 Product data sheet 1. General description The provides a 3-input EXCLUSIVE-OR function. The input can be driven from either 3.3 or 5 V devices. This feature allows the use of these
74HC4040; 74HCT4040. 12-stage binary ripple counter
Rev. 5 3 February 2016 Product data sheet 1. General description 2. Features and benefits 3. Applications 4. Ordering information The is a with a clock input (CP), an overriding asynchronous master reset
Low-power configurable multiple function gate
Rev. 7 10 September 2014 Product data sheet 1. General description The provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the
74HC154; 74HCT154. 4-to-16 line decoder/demultiplexer
Rev. 7 29 February 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a. It decodes four binary weighted address inputs (A0 to A3) to sixteen mutually
74HC165; 74HCT165. 8-bit parallel-in/serial out shift register
Rev. 4 28 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Applications 4. Ordering information The is an 8-bit serial or parallel-in/serial-out shift register. The device
Features INVERTING. 0.6mA NONINVERTING INVERTING. 0.6mA NONINVERTING
MIC442/442/4428 Dual 1.A-Peak Low-Side MOSFET Driver General Description The MIC442/442/4428 family are highly-reliable dual lowside MOSFET drivers fabricated on a BiCMOS/DMOS process for low power consumption
74F257A Quad 2-line to 1-line selector/multiplexer, non-inverting (3-State)
INTEGRATED CIRCUITS Quad 2-line to 1-line selector/multiplexer, non-inverting (3-State) 1995 Mar 31 IC15 Data Handbook Philips Semiconductors Quad 2-line to 1-line selector/multiplexer, non-inverting (3-State)
74HC107; 74HCT107. Dual JK flip-flop with reset; negative-edge trigger
Rev. 5 30 November 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual negative edge triggered JK flip-flop featuring individual J and K inputs,
74HC02; 74HCT02. 1. General description. 2. Features and benefits. Ordering information. Quad 2-input NOR gate
Rev. 5 26 November 2015 Product data sheet 1. General description 2. Features and benefits The is a quad 2-input NOR gate. Inputs include clamp diodes. This enables the use of current limiting resistors
Data Sheet. HFBR-0600Z Series SERCOS Fiber Optic Transmitters and Receivers
HFBR-0600Z Series SERCOS Fiber Optic Transmitters and Receivers Data Sheet SERCOS SERCOS is a SErial Realtime COmmunication System, a standard digital interface for communication between controls and drives
4 OUTPUT PCIE GEN1/2 SYNTHESIZER IDT5V41186
DATASHEET IDT5V41186 Recommended Applications 4 Output synthesizer for PCIe Gen1/2 General Description The IDT5V41186 is a PCIe Gen2 compliant spread-spectrum-capable clock generator. The device has 4
MC100LVEP34. 2.5V / 3.3V ECL 2, 4, 8 Clock Generation Chip
2.5V / 3.3V ECL 2, 4, 8 Clock Generation Chip The MC00LVEP34 is a low skew 2, 4, 8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous
74HC574; 74HCT574. Octal D-type flip-flop; positive edge-trigger; 3-state
Rev. 7 4 March 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device
2/4, 4/5/6 CLOCK GENERATION CHIP
2/4, 4/5/6 CLOCK GENERATION CHIP FEATURES 3.3V and 5V power supply option 50ps output-to-output skew 50% duty cycle outputs Synchronous enable/disable Master Reset for synchronization Internal 75KΩ input
High-Speed, Low-Power, 3V/5V, Rail-to-Rail, Single-Supply Comparators MAX941/MAX942/ MAX944. General Description. Features. Ordering Information
General Description The MAX941/MAX94/ are single/dual/quad highspeed comparators optimized for systems powered from a 3V or 5V supply. These devices combine high speed, low power, and rail-to-rail inputs.
INTEGRATED CIRCUITS. 74F153 Dual 4-line to 1-line multiplexer. Product specification 1996 Jan 05 IC15 Data Handbook
INTEGRATED CIRCUITS 1996 Jan 05 IC15 Data Handbook FEATURES Non-inverting outputs Separate enable for each section Common select inputs See 74F253 for 3-State version PIN CONFIGURATION Ea 1 S1 2 I3a 3
74HCU04. 1. General description. 2. Features and benefits. 3. Ordering information. Hex unbuffered inverter
Rev. 7 8 December 2015 Product data sheet 1. General description The is a hex unbuffered inverter. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to
74HC175; 74HCT175. Quad D-type flip-flop with reset; positive-edge trigger
Rev. 5 29 January 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad positive-edge triggered D-type flip-flop with individual data inputs (Dn)
MM74HC273 Octal D-Type Flip-Flops with Clear
MM74HC273 Octal D-Type Flip-Flops with Clear General Description The MM74HC273 edge triggered flip-flops utilize advanced silicon-gate CMOS technology to implement D-type flipflops. They possess high noise
DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control
August 1986 Revised February 1999 DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control General Description The DM74LS191 circuit is a synchronous, reversible, up/ down counter. Synchronous operation
AAT3520/2/4 MicroPower Microprocessor Reset Circuit
General Description Features PowerManager The AAT3520 series of PowerManager products is part of AnalogicTech's Total Power Management IC (TPMIC ) product family. These microprocessor reset circuits are
11. High-Speed Differential Interfaces in Cyclone II Devices
11. High-Speed Differential Interfaces in Cyclone II Devices CII51011-2.2 Introduction From high-speed backplane applications to high-end switch boxes, low-voltage differential signaling (LVDS) is the
SPREAD SPECTRUM CLOCK GENERATOR. Features
DATASHEET ICS7152 Description The ICS7152-01, -02, -11, and -12 are clock generators for EMI (Electro Magnetic Interference) reduction (see below for frequency ranges and multiplier ratios). Spectral peaks
74HC573; 74HCT573. 1. General description. 2. Features and benefits. Octal D-type transparent latch; 3-state
Rev. 7 4 March 2016 Product data sheet 1. General description The is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE
MIC4451/4452. General Description. Features. Applications. Functional Diagram V S. 12A-Peak Low-Side MOSFET Driver. Bipolar/CMOS/DMOS Process
12A-Peak Low-Side MOSFET Driver Bipolar/CMOS/DMOS Process General Description MIC4451 and MIC4452 CMOS MOSFET drivers are robust, efficient, and easy to use. The MIC4451 is an inverting driver, while the
MM74HC174 Hex D-Type Flip-Flops with Clear
Hex D-Type Flip-Flops with Clear General Description The MM74HC174 edge triggered flip-flops utilize advanced silicon-gate CMOS technology to implement D-type flipflops. They possess high noise immunity,
74HC74; 74HCT74. 1. General description. 2. Features and benefits. 3. Ordering information
Rev. 5 3 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual
EVALUATION KIT AVAILABLE Single-Chip Global Positioning System Receiver Front-End BIAS CBIAS GND GND RFIN GND GND IFSEL
19-3469; Rev 2; 4/08 EVALUATION KIT AVAILABLE Single-Chip Global Positioning System General Description The complete single-chip global positioning system (GPS) RF front-end utilizes many innovative and
1-of-4 decoder/demultiplexer
Rev. 6 1 April 2016 Product data sheet 1. General description 2. Features and benefits 3. Applications The contains two 1-of-4 decoders/demultiplexers. Each has two address inputs (na0 and na1, an active
High-Bandwidth, T1/E1, SPST Analog Switches
19-3951; Rev 2; 1/7 High-Bandwidth,, SPST Analog Switches General Description The high-bandwidth, low-on-resistance, quad-spst analog switches are designed to serve as integrated protection switches for
74HC393; 74HCT393. Dual 4-bit binary ripple counter
Rev. 6 3 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The 74HC393; 7474HCT393 is a dual 4-stage binary ripple counter. Each counter features
HEF4011B. 1. General description. 2. Features and benefits. 3. Ordering information. 4. Functional diagram. Quad 2-input NAND gate
Rev. 6 10 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad 2-input NAND gate. The outputs are fully buffered for the highest noise
DM9368 7-Segment Decoder/Driver/Latch with Constant Current Source Outputs
DM9368 7-Segment Decoder/Driver/Latch with Constant Current Source Outputs General Description The DM9368 is a 7-segment decoder driver incorporating input latches and constant current output circuits
HEF4021B. 1. General description. 2. Features and benefits. 3. Ordering information. 8-bit static shift register
Rev. 10 21 March 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an (parallel-to-serial converter) with a synchronous serial data input (DS), a clock
MM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop
3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT373 octal D-type latches and MM74HCT374 Octal D-type flip flops advanced silicongate CMOS technology, which provides
AP331A XX G - 7. Lead Free G : Green. Packaging (Note 2)
Features General Description Wide supply Voltage range: 2.0V to 36V Single or dual supplies: ±1.0V to ±18V Very low supply current drain (0.4mA) independent of supply voltage Low input biasing current:
MAX14759/MAX14761/MAX14763 Above- and Below-the-Rails Low On-Resistance Analog Switches
19-651; Rev ; 9/11 /MX14761/ General Description The /MX14761/ analog switches are capable of passing bipolar signals that are beyond their supply rails. These devices operate from a single +3.V to +5.5V
The 74LVC1G04 provides one inverting buffer.
Rev. 12 6 ugust 2012 Product data sheet 1. General description The provides one inverting buffer. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in
MM74HC4538 Dual Retriggerable Monostable Multivibrator
MM74HC4538 Dual Retriggerable Monostable Multivibrator General Description The MM74HC4538 high speed monostable multivibrator (one shots) is implemented in advanced silicon-gate CMOS technology. They feature
4-bit binary full adder with fast carry CIN + (A1 + B1) + 2(A2 + B2) + 4(A3 + B3) + 8(A4 + B4) = = S1 + 2S2 + 4S3 + 8S4 + 16COUT
Rev. 03 11 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The is specified in compliance
AND8090/D. AC Characteristics of ECL Devices APPLICATION NOTE
AC Characteristics of ECL Devices APPLICATION NOTE APPLICATION NOTE USAGE This application note provides a general overview of the AC characteristics that are specified on the ON Semiconductor data sheets
INTEGRATED CIRCUITS. 74F74 Dual D-type flip-flop. Product specification Supercedes data of 1990 Oct 23 IC15 Data Handbook.
INTEGRATED CIRCUITS Supercedes data of 1990 Oct 23 IC15 Data Handbook 1996 Mar 12 FEATURE Industrial temperature range available ( 40 C to +85 C) DESCRIPTION The is a dual positive edge-triggered D-type
NB6LQ572. 2.5V / 3.3V Differential 4:1 Mux w/input Equalizer to 1:2 LVPECL Clock/Data Fanout / Translator
2.5V / 3.3V Differential 4:1 Mux w/input Equalizer to 1:2 LVPECL Clock/Data Fanout / Translator Multi Level Inputs w/ Internal Termination The NB6L572 is a high performance differential 4:1 Clock/Data
74HC595; 74HCT595. 1. General description. 2. Features and benefits. 3. Applications
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Rev. 8 25 February 2016 Product data sheet 1. General description The is an 8-bit serial-in/serial or parallel-out shift
MM74HC14 Hex Inverting Schmitt Trigger
MM74HC14 Hex Inverting Schmitt Trigger General Description The MM74HC14 utilizes advanced silicon-gate CMOS technology to achieve the low power dissipation and high noise immunity of standard CMOS, as
74AC138 74ACT138 1-of-8 Decoder/Demultiplexer
1-of-8 Decoder/Demultiplexer General Description The AC/ACT138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The
Quad 2-input NAND Schmitt trigger
Rev. 9 15 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Applications The is a quad two-input NAND gate. Each input has a Schmitt trigger circuit. The gate switches
AAT4280 Slew Rate Controlled Load Switch
General Description Features SmartSwitch The AAT4280 SmartSwitch is a P-channel MOSFET power switch designed for high-side load switching applications. The P-channel MOSFET device has a typical R DS(ON)
3.3V, 2.7Gbps SDH/SONET LASER DRIVER WITH AUTOMATIC POWER CONTROL
3.3V, 2.7Gbps SH/SONET LASER RIVER WITH AUTOMATIC POWER CONTROL FEATURES ESCRIPTION Single 3.3V power supply Up to 2.7Gbps operation Rise/Fall times: < 75ps Independent programmable laser modulation and
ZL40221 Precision 2:6 LVDS Fanout Buffer with Glitchfree Input Reference Switching and On-Chip Input Termination Data Sheet
Features Inputs/Outputs Accepts two differential or single-ended inputs LVPECL, LVDS, CML, HCSL, LVCMOS Glitch-free switching of references On-chip input termination and biasing for AC coupled inputs Six
74HC595; 74HCT595. 1. General description. 2. Features and benefits. 3. Applications
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Rev. 7 26 January 2015 Product data sheet 1. General description The are high-speed Si-gate CMOS devices and are pin
High Accuracy, Ultralow IQ, 1 A, anycap Low Dropout Regulator ADP3338
High Accuracy, Ultralow IQ, 1 A, anycap Low Dropout Regulator ADP3338 FEATURES High accuracy over line and load: ±.8% @ 25 C, ±1.4% over temperature Ultralow dropout voltage: 19 mv (typ) @ 1 A Requires
DATA SHEET. TDA1518BQ 24 W BTL or 2 x 12 watt stereo car radio power amplifier INTEGRATED CIRCUITS
INTEGRATED CIRCUITS DATA SHEET File under Integrated Circuits, IC01 July 1994 GENERAL DESCRIPTION The is an integrated class-b output amplifier in a 13-lead single-in-line (SIL) plastic power package.
Product Specification PE9304
PE9304 Product Description The PE9304 is a high-performance UltraCMOS prescaler with a fixed divide ratio of 2. Its operating frequency range is 1000 7000 MHz. The PE9304 operates on a nominal 3V supply
±15kV ESD-Protected, 1µA, 250kbps, 3.3V/5V, Dual RS-232 Transceivers with Internal Capacitors
19-1473; Rev 2; 8/4 ±15k ESD-Protected, 1µA, 25kbps, 3.3/5, Dual General Description The are EIA/TIA-232 and.28/.24 communications interfaces with automatic shutdown/ wake-up features, high data-rate capabilities,
High Accuracy, Ultralow IQ, 1.5 A, anycap Low Dropout Regulator ADP3339
Data Sheet High Accuracy, Ultralow IQ,.5 A, anycap Low Dropout Regulator FEATURES FUNCTIONAL BLOCK DIAGRAM High accuracy over line and load: ±.9% at 5 C, ±.5% over temperature Ultralow dropout voltage:
Triple single-pole double-throw analog switch
Rev. 12 25 March 2016 Product data sheet 1. General description 2. Features and benefits 3. Applications 4. Ordering information The is a triple single-pole double-throw (SPDT) analog switch, suitable
ICL232. +5V Powered, Dual RS-232 Transmitter/Receiver. Description. Features. Ordering Information. Applications. Functional Diagram.
ICL August V Powered, Dual RS Transmitter/Receiver Features Meets All RSC and V. Specifications Requires Only Single V Power Supply Onboard Voltage Doubler/Inverter Low Power Consumption Drivers ±V Output
Link-65 MHz, +3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz
DS90C383A/DS90CF383A +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz +3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz 1.0 General Description The DS90C383A/DS90CF383A
74HC123; 74HCT123. Dual retriggerable monostable multivibrator with reset
Rev. 9 19 January 2015 Product data sheet 1. General description The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with
Hex buffer with open-drain outputs
Rev. 5 27 October 20 Product data sheet. General description The provides six non-inverting buffers. The outputs are open-drain and can be connected to other open-drain outputs to implement active-low
Features. Ordering Information. * Underbar marking may not be to scale. Part Identification
MIC86 Teeny Ultra Low Power Op Amp General Description The MIC86 is a rail-to-rail output, input common-mode to ground, operational amplifier in Teeny SC7 packaging. The MIC86 provides 4kHz gain-bandwidth
DALLAS DS1233 Econo Reset. BOTTOM VIEW TO-92 PACKAGE See Mech. Drawings Section on Website
5V EconoReset www.maxim-ic.com FEATURES Automatically restarts microprocessor after power failure Monitors pushbutton for external override Internal circuitry debounces pushbutton switch Maintains reset