LDO Regulator Stability and Ceramic Capacitors

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1 LDO Regulator Stability and Ceramic Capacitors Chester Simpson Power Management Group National Semiconductor Most LDO (low dropout) regulators work perfectly with Tantalum output capacitors, but using ceramic capacitors can cause stability problems. This is becoming more common now because multilayer ceramic capacitors with values as high as 22 µf are readily available in surface mount components whose size and cost are more attractive than the Tantalum capacitors traditionally used in these applications. However, if ceramics are used on the output of a typical LDO regulator, it may become marginally stable or oscillate continuously. This article explains LDO stability related to the output capacitor and why ceramics can have this effect. The LDO regulator The low-dropout (LDO) regulator uses a single PNP transistor as a voltage-controlled current source (or P-FET if it is a CMOS LDO) which supplies load current as required to hold the output at the nominal regulated value (see Figure 1). The output voltage is sampled through a resistive divider, and this signal is used by the error amplifier and driver circuits to control the Figure 1. Typical LDO Regulator drive to the PNP (or P-FET). The big advantage of the LDO is that the minimum input-to-output voltage differential required to maintain regulation (called the dropout voltage) can be anywhere from a few hundred millivolts to tens of millivolts. The feedback signal used by the control loop experiences changes in both gain and phase as it goes through the loop, and the amount of phase shift which has occurred at the unity gain (0 db) frequency determines stability (or instability). Gain and phase plots The stability of the LDO regulator will be analyzed using a Bode Plot (Figure 2), which shows both loop gain and phase shift. Loop gain (expressed in db) is a measure of the voltage gain that a feedback signal will experience as it travels through the feedback loop. Phase shift (expressed in degrees) is defined as the total amount of phase change that the feedback signal experiences as it goes through the loop. If a phase shift of -180 is reached at the unity gain frequency, instability occurs. Phase margin is defined as the difference (in degrees) between the phase shift value and Phase margin values between 5 and 25 are usually considered marginally stable, and will typically exhibit ringing during output transients. A pole is defined as a point where the slope of the gain curve changes by -20 db/decade (with reference to the slope of the curve prior to the pole). The phase shift introduced by a single pole is frequency dependent, varying from 0 to -90 (with a phase shift of -45 at the pole frequency). NOTE: since a single pole can add only -90 of total phase shift, at least two poles are needed to reach -180 (where instability can occur). A zero is defined as a point where the gain changes by +20 db/decade (with respect to the slope prior to the zero). The phase shift introduced by a zero varies from 0 to +90, with a +45 shift occurring at the frequency of the zero. The most important thing to observe about a zero is that its effects on gain and phase are exactly the opposite of a pole. This is why zeroes are intentionally added to the feedback loops of LDO regulators: they can cancel out the effect of one of the low-frequency poles that would cause instability if left uncompensated. Compensating a typical LDO Because the LDO uses a PNP (or P-FET) pass transistor, any capacitor connected from the output to ground will form a pole and a zero due to its interaction with the output resistance. The frequency of the pole (which will be designated P L for load pole) is found using: f (PL ) = 1 / (2π X R LOAD X C OUT ) For the example in Figure 2, an output capacitance of 10 µf and load resistance of 60 is assumed which places PL at 260 Hz. Figure 2. Typical LDO Bode Plot International IC 99 Conference Proceedings 11

2 Since P L varies directly with load resistance, it is necessary to add a fixed-frequency compensation pole, designated Pcomp, to the error amplifier for loop compensation. In a typical LDO, the frequency of Pcomp is set between 500 Hz and 1k Hz. Since two uncompensated poles will cause a total phase shift of -180 (and oscillations), it is necessary to add a zero to the control loop to generate positive phase shift so that adequate phase margin will be present at the 0 db frequency. This zero can be derived from the ESR (equivalent series resistance) of the output capacitor, and the frequency of the zero is given by: F ZERO = 1 / (2π X C OUT X ESR) The example in Figure 2 assumes that the 10 µf output capacitor has an ESR of about 1 (a typical value for a solid Tantalum capacitor) which places F ZERO at 16 khz. The Bode plot also shows a high-frequency pole P HF at about 500 khz, which would be typical for the PNP power stage in an LDO. The plot of phase margin shows that without the zero, PL and Pcomp would reduce the phase margin to zero at the 0 db crossover frequency, resulting in oscillations. However, the positive phase shift provided by the zero increases the phase margin to 70, which is very stable. This example clearly illustrates that the typical LDO requires the zero provided by the output capacitor to be stable, and this zero must lie in the correct range of frequency to be effective. The typical LDO regulator is designed to work with ESR values in the range of about 0.1 to about 10. This range is almost perfectly centered around the typical values for Tantalum capacitors, but large ceramic capacitors have ESR values in the range of 10-15m, which is too low for most LDO s. Assuming a 10µF ceramic output capacitor is used with an ESR of 10m?, the zero will be moved from 16 khz to 1.6 MHz. Returning to the example in Figure 2, moving the zero to 1.6 MHz effectively removes it from the plot, returning the phase margin to zero (explaining why most LDO s can t handle ceramic output capacitors). However, it is possible to build an LDO that does work with ceramics: the LP2985 is a 150 ma LDO which was developed specifically to be used with ceramic output capacitors. To accomplish this, the zero which was moved to a very high frequency by using ceramics was replaced by another zero which is built into the IC by adding an R-C network around the control amplifier. The added zero was placed at the optimum frequency for loop stability. Since the LP2985 does not need the zero from COUT, the stable range of ESR values for the output capacitor ranges from 0 to about 0.5 (allowing the use of ceramics). The reason there is an upper limit on stable ESR is that since a zero is already built into the LP2985 control amplifier, adding another one in the same frequency range would increase loop bandwidth sufficiently to cause instability from the phase shift resulting from very high frequency poles not shown in the example. Bypass capacitors Many circuit designers routinely use bypass capacitors (values in the range of.001 µf to 0.1 µf) on the VCC pins of IC s as good design practice for bypassing noise and ensuring a clean supply voltage. In digital logic circuits, this practice is so common that these capacitors are often left off the schematic and automatically added at PC board layout. It should be advised that LDO regulators can suffer reduced phase margin and even oscillate if such capacitors are placed on their output for a reason that is so subtle it invariably escapes even the most experienced analog designers. As an LDO will typically have a capacitor of 2.2 µf - 10 µf connected to the output, it seems impossible that connecting a small capacitor in parallel with it could have an effect on stability. The reason it does is because any capacitor connected from the LDO output to ground forms both a pole and a zero when it interacts with the load resistance (Figure 3). Figure 3. Decoupling Capacitor Pole can Cancel Out Phase Gain of ESR Zero. If the bypass capacitor is the right size, it will form a pole near the frequency of the zero that is essential to stabilize the loop. This pole will cancel out most or all of the phase gain provided by the zero, which leaves the LDO marginally stable or oscillating. The same effect can occur on LDO s with internal compensation, as the externally added pole will cancel out the zero regardless of its source. The exact value of capacitance that will make the LDO unstable will depend primarily on the LDO s loop bandwidth. Very wideband LDO s (like the LP298X family) have unity-gain bandwidths of several megahertz. A capacitor of about.01 µf (which puts a pole in the khz range) should be avoided. The best way to avoid this problem altogether is not to use discrete capacitors on the output whose value is in the range of.001 µf to 0.1 µf. The type of capacitor which seems to be most prone to cause this effect is ceramic, as they are very high Q (low internal losses) and that makes them prone to resonate. One technique which can be used to shield the LDO from the phase shift of the bypass capacitor is to intentionally put a long PC board trace between the LDO output and the bypass capacitor. Putting impedance between the LDO output and the capacitor reduces the tendency to oscillate. This may not be effective in multilayer boards with dedicated planes for ground and VCC. In such cases, the effective impedance across a 10 cm length of copper plane can be as low as a few milli Ohms, which would not significantly reduce the effect of the bypass capacitor. 12 International IC 99 Conference Proceedings

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