3 rd Year DSD Coursework Single-Component Sequential Baseline JPEG Decoder

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1 3 rd Year DSD Coursework Single-Component Sequential Baseline JPEG Decoder Task Design a sequential baseline JPEG decoder implemented on the Xilinx Vertex II Pro FPGA. Test and demonstrate the design on the Xilinx XUP Virtex II Pro Development System. Baseline JPEG is the minimum required functionality required by the JPEG specification. Decoding such a file requires 3 main operations. Entropy (Huffman) decoding Dequantisation Inverse Discrete Cosine Transform In order to simplify the problem you will be required to decode a specific single-component (greyscale) image. This means that the Huffman and quantisation tables will be constant and can be hardwired in your designs. JPEG theory Encoding Each component (colour) of the image is divided into blocks of 8x8 pixels. For a non-interleaved image these are arranged as a raster scan (left to right, top to bottom) as shown below. The discrete cosine transform (similar to the discrete Fourier transform) is performed on each block. This involves fi level shifting each value by subtracting 128. Then the forward DCT is performed. This results in an 8x8 block where the value in the top left position is considerably larger than the rest (the DC coefficient), and the values towards the bottom right hand corner become less.

2 The next stage is quantisation. This is a lossy stage; i.e. information is lost and irretrievable as a result of this stage, resulting in (hopefully subtle) differences between the original and compressed JPEG images. In this stage each element of the 8x8 blocks from the DCT are divided by the corresponding element of an 8x8 quantisation matrix and rounded to the nearest integer. This results in many of the smaller values of the block going to zero. Next the individual blocks are entropy encoded using Huffman coding. For this the 64 quantised DCT coefficients are arranged in the zigzag pattern shown below. The fi (DC) element is encoded using the DC Huffman table, the remaining elements using the AC Huffman table. JPEG has a special Huffman code for the end of a block which means all remaining values are zero. Decoding The reverse of these procedures are used for decoding JPEGs: Looking up Huffman codes from a Huffman tables and reordering the data will result in blocks of quantised DCT coefficients. These are multiplied by values from a quantisation table to give the DCT coefficients. The original values are then calculated using the following equation, and by adding 128. ( 2x + 1) u ( 2y + 1) s xy = CuCvSvu cos 4 u= 0 v= 0 16 where C u, C v = 1/ 2 for u, v = 0 C, u v = 1 otherwise S vu value of source block pixel (v, u) s xy value of destination block pixel (x, y) π vπ cos 16

3 Provided Skeleton implementation JPEG file to decode o This file is a single-component image of 640x480 pixels Excel file with the Huffman and Quantisation tables for the above JPEG The JPEG standard Skeleton Implementation When the board is configured a software program runs automatically on one of the PowerPCs of the FPGA. This program reads the JPEG from the flash card and streams it to the JPEG decoder block s input FIFO. FPGA Flash Memory Display System ACE On-chip Peripheral Bus VGA Display Buffer PowerPC SDRAM Device Control Register Bus Processor Local Bus JPEG Decoder The JPEG decoder block is where the processing occurs, and you must implement it. Three Xilinx ISE schematic files have been provided for you to work with. Of note are the, and _en signals at the input

4 and output of the Huffman and IDCT blocks. is set high to request data, and goes high when data is available from the input FIFO, and you must set _en high the clock cycle before data becomes available at the output of the IDCT block for it to be written to the output FIFO. of the IDCT block should be set high in order to request data. The signal should be propagated through the blocks to the output of the Huffman block where is requests data from the FIFO. The and are all 64-bits wide. Huffman Dequantisation IDCT _en _en _en _in _in The software then reads the data from the output FIFO and stores it into the development boards SDRAM. Once the image has been fully decoded, the display is activated, and the VGA display buffer reads the display data from the SDRAM and outputs it to the display. Deliverables You are expected to work in pairs. This means that the task should be divided somewhere down the middle, with one person perhaps working on the Huffman and quantisation (both table look-ups) and another on the IDCT. A report (one per group) detailing your design. Tools To build the design and generate bit-streams you must use Xilinx Platform Studio. You will most probably be using Xilinx Project Navigator to create your designs. I have generated schematic templates for the three stages of the JPEG decoder, with get instantiated in the overall design. In order for your designs to be used in XPS they must be VHDL. If you are using schematic files in your design you must convert them to VHDL to test them in your design. To do this call the command "sch2vhdl.exe - family virtex2p IDCT.sch" (or huffman.sch or dequantisation.sch) from the directory where the schematics are stored.

5 Getting Started and Hints on Implementation Open the Project Navigator project from \jpeg_256mb\pcores\jpeg_dec_v1_00_a\devl\projnav\jpeg_dec.ise Open the schematic template files from \jpeg_256mb\pcores\jpeg_dec_v1_00_a\hdl\vhdl these are the files you must edit You must convert these schematic files to VHDL as stated above Huffman Use a table lookup. The tables can be found in the file tables.xls provided. Details of the algorithm you must implement are in the JPEG standard from page 104 onwards. Dequantisation This is the easiest block to implement. Use dedicated multipliers to multiply each 8-bit input by the value form the dequantisation table. Store the table in block RAMs. Use counters to keep track of which value you are operating on. The multipliers in the Virtex II Pro are 18x18-bit so you can probably conserve multipliers by using each to perform 2 multiplications. Perform 8 in parallel in order to process all 64-bits at once. IDCT Your design should buffer an 8x8 block of data at a time (i.e. keep high until a block has been received). Pre-compute the cosine terms of the IDCT for table look-up, paying particular attention to repeating values to reduce the size of the table. Use the dedicated multipliers. Parallelise the design as much as possible.

Video-Conferencing System

Video-Conferencing System Evan Broder and C. Christoher Post Introductory Digital Systems Laboratory November 2, 2007 Abstract The goal of this project is to create a video/audio conferencing system. Video