Writing C-programs to verify a SoC design. Sven Andersson Zoocad Consulting

Transcription

1 Writing C-programs to verify a SoC design Sven Andersson

2 Agenda Presentation / Introduction Why using C programs for RTL verification Major obstacles to overcome Chipotle C program based test language environment Verification environment Xtensa LX5 customizable DPU Verilog test bench Simulation commands Running a simulation using Mongoose Platforms supported Conclusion Demonstration

3 Presenting Myself 1950 Born 1969 Studied Electrical Engineering at Royal Institute of Engineering 1974 Got my first job as a component engineer at LM Ericsson 1990 Joined the ASIC design group at Ericsson 1992 Verilog training course 1992 My first RTL design (JTAG controller) 1993 First version of the Mongoose program 2006 Started my own company ( ) 2013 Specified the Chipotle test language

4 Introduction Every SoC design has one or more processor core(s) When testing the SoC the embedded processor will execute a program Programs are normally written in the C language The C program can easily by converted to a program memory load module The load module can be loaded to the memory model before RTL simulation starts Only the processor clock and reset must be provided to start the RTL simulation To make it useful for system verification we have to find a way to control input signals and measure output signals in our SoC This is what this presentation is all about

5 Why Using C Programs for RTL Verification A lot more people know how to write C programs compared to Verilog or SystemVerilog code The C language is easy to understand and has a lot of built-in functions C compilers are very efficient and generate compact program code The whole simulation can be controlled from one place C programs makes debugging the design simpler By adding special instruction the hardware setup can be controlled Simulation time is saved because we don't have to compile and elaborate the RTL test bench for every simulation run

6 Major Obstacles to Overcome Converting the compiled c-program to a Verilog load module Detecting end of program execution Printing to a console or a log file Generating pseudo-random data Controlling the c-program from the verilog testbench Controlling the verilog testbench from the c-program Finding out if the program execution hangs

7 Chipotle Test Language Environment An extension to the normal C programming language to support RTL debug and verification The Verilog test bench will recognize these macros and implement the specified function A special print macro supports printing from the C program to the Verilog test bench logfile or console Lots of statistics can be generated during a simulation run Pseudo-random data generation is supported 64, 32, 16 and 8 bit data formats can be used Different test modes are supported (debug, waveform dumps, regression testing)

8 SoC Verification Timelines

9 Verification Flow Diagram

10 Xtensa LX5 Digital Processing Unit Small, low-power 32-bit base architecture Configurable over a wide range of pre-verified options Extendable with designer-defined instructions, register files, and I/O Local memory configurable up to 8MB Dual load/stores up to 512 bits wide IEEE 754 compliant double-precision floating point unit Coresight compatible interface for debug and trace

11 Verilog Test Bench

12 Simulation Control Commands writecontrol(sim_control,simulation_time) writecontrol(sim_control, END_OF_TEST) writecontrol(sim_control,display_statistics) writecontrol(sim_control,start_measure) writecontrol(sim_control,stop_measure) writecontrol(sim_control,inc_fail_counter) writecontrol(sim_control,inc_pass_counter)

13 Simulation Hardware Control Commands writecontrol(enable_interrupt,0x2) writecontrol(enable_test,gpio) writecontrol(drive_gpio_in,0xabcd) writecontrol(check_gpio_out,0x1234) writecontrol(enable_counter,0xff) writecontrol(clear_counter,0x33)

14 Supporting C Functions printdate(date_value) printtime(time_value) waitcycles(clock_cycles) generaterandomdata(seed) printtextstring( text ) convertbinarytodec( ) printbinary(value)

15 C-program Example for (i=0; I < NUMBER_OF_GPIO_REGISTERS; i++) { expectedvalue = (int32_t)generaterandomdata32(&seedvalue); registervalue = readdata(gpio_base_address+i*4); #ifdef ENABLE_PRINT writecontrol(write_result_hex,gpio_base_address+i*4); writecontrol(display_result_hex,registervalue); #endif if (registervalue!= expectedvalue) writecontrol(sim_control,inc_fail_counter); else writecontrol(sim_control,inc_pass_counter); }

16 Mongoose Simulation Environment Mongoose is a control center for running RTL simulations It supports Cadence Incisive, Synopsys VCS and Mentor Graphics Questa It uses a graphical user interface to handle the simulation flow (compilation, elaboration and simulation) The whole setup can easily be scripted Includes full support for C program compilation and load module generation Waveform data from all nodes in the RTL design can easily be generated Can also be used for regression testing

17 Mongoose startup window

18 Mongoose Processor Program Compilation

19 Processor Platforms Supported Xtensa LX5 (Tensilica) OpenRISC 1200 (OpenCores) MicroBlaze (Xilinx) Nios II (Altera)

20 Conclusion By extending C programs with special test macros a complete hardware verification test suite can be built By adding a print macro full test reports can be generated External test generators and test recorders can be controlled from the C-program Pseudo-random data generation is fully supported It is a perfect debugging environment Incremental setup C program based test setup can not fully replace a SystemVerilog test bench but it is a very good complement It gives us a jump start. It is ready to run long before the SystemVerilog test bench is ready. Simplicity

21 More Reading and Watching ChipotleTestLanuage.pdf