LPDDR3 and Wide I/O DRAM:
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1 LPDDR3 and Wide I/O DRAM: Interface Changes that give PC-Like Memory Performance to Mobile Devices Marc Greenberg, Director, Product Marketing - Memcon 2012 San Jose Sept 18, 2012
2 Agenda What is PC-like Memory Performance? Common PC memory configurations Low-power Alternatives Comparative Metrics How did LPDDR3 evolve? How did Wide I/O evolve? Future low-power memory direction Cadence Design Systems, Inc. All rights reserved.
3 What is PC-Like Memory Performance? Computer Type Price Range Memory implementation by manufacturer* Number of bits in DRAM interface / Interface data rate Company 1 Company 2 Company 3 Company 4 Company 5 Tablet / Small $300-$550 64/800** 128/800** 128/1333** 128/800** Thin & Light $700-$700 64/ / /1333** 64/1333** Entry Laptop $450-$500 64/1333** 128/ /1333** 128/1333 Power Laptop $1250-$ /1600** 128/ / /1333** 128/1600 Entry Desktop $275-$330 64/ / / /1333 Power Desktop $1200-$ / / / / /1600 * Computers selected are the author s opinion of indicative computers within the price range by a survey of websites of five large computer manufacturers in September 2012 and do not necessarily indicate the best, lowest cost, or most representative computer in the price range from each manufacturer ** Exact specification not available on manufacturer website; this number is estimated Cadence Design Systems, Inc. All rights reserved.
4 Common PC Memory Configurations Company 1 Company 2 Company 3 Company 4 Company Cadence Design Systems, Inc. All rights reserved.
5 Common PC Memory Configurations All the Top PC manufacturers have a machine in the 100Gbit/s range today Company 1 Company 2 Company 3 Company 4 Company Cadence Design Systems, Inc. All rights reserved.
6 Common PC Memory Configurations The majority of computing jobs are now in the Gbit/sec range Company 1 Company 2 Company 3 Company 4 Company Cadence Design Systems, Inc. All rights reserved.
7 Common PC Memory Configurations Longer-term, mobile devices are going to be expected to perform like gaming PCs of today Company 1 Company 2 Company 3 Company 4 Company Cadence Design Systems, Inc. All rights reserved.
8 Mobile Devices become like our PCs Mobile devices are becoming like our PC devices 0.9+ Megapixel (approximately 1280*720) or better resolution now common in high-end smartphones 300+ pixels per inch 3+ Megapixel (approximately 2000*1600) tablets appearing The 22 LCD monitor on my desk is only 1680*1050 Consumers beginning to expect mobile entertainment experience to be like their wired entertainment experience 4K Video (8+ Megapixels *2160) and 3D are coming A small number of 4K TVs already for sale A 10 tablet with 480 pixels per inch could display 4K video Approximately 25-50Gbit/s of video traffic to DRAM for video decode High-end desktop graphics cards capable of 4K operation have Gbit/s of memory bandwidth Cadence Design Systems, Inc. All rights reserved.
9 Common PC Memory Configurations Company 1 Company 2 Company 3 Company 4 Company Cadence Design Systems, Inc. All rights reserved.
10 Common PC Memory Configurations Current Generation Current Generation Smartphone Next Generation Next Generation Smartphone Company 1 Company 2 Company 3 Company 4 Company Cadence Design Systems, Inc. All rights reserved.
11 Low Power Memory - Today Next Generation Current Generation Current Generation Now Next Generation In design now Shipping Concept Phase Shipping Cadence Design Systems, Inc. All rights reserved.
12 Low Power Memory - Today Next Generation Current Generation Current Generation Now Next Generation In design now Shipping Concept Phase Shipping Cadence Design Systems, Inc. All rights reserved.
13 Low 250 Power Memory - Today Current Generation Next Generation Next Generation Next Generation Current Generation Current Generation Current Generation Now Next Generation In design now Shipping Concept Phase Shipping Cadence Design Systems, Inc. All rights reserved.
14 Low 250 Power Memory - Today Next Generation Current Generation Next Generation Current Generation Now In design now Shipping Concept Phase Shipping Cadence Design Systems, Inc. All rights reserved.
15 Low 250 Power Memory - Today DDR3L now appearing in some tablets Next Generation bit LPDDR2-800 Current Generation 64bit LPDDR bit LPDDR bit Current Generation LPDDR bit LPDDR2-800 Now Next Generation In design now Shipping Concept Phase Shipping Cadence Design Systems, Inc. All rights reserved.
16 Low 250 Power Memory Future - Parallel DDR3L now appearing in some tablets 128bit LPDDR bit DDR-3200 Possible Future Standard Next Generation 64-bit Possible LPDDR3 speed extension bit LPDDR bit LPDDR Current Generation Next Generation 64bit LPDDR bit LPDDR bit LPDDR bit Current Generation LPDDR bit LPDDR2-800 Now In design now Shipping Concept Phase Shipping Cadence Design Systems, Inc. All rights reserved.
17 Low Power DRAM Typical Features Low Voltage Low I/O Capacitance Unterminated I/Os Typically X16 or X32 data width per die Often contained in multi-die packages No DLL Fast low-power entry and exit Very low standby (self-refresh) power Temperature Compensated Self-Refresh mode Deep Power Down mode Partial Array Self-Refresh Cadence Design Systems, Inc. All rights reserved.
18 Low Power LPDDR vs Low Voltage DDR3L DDR3L is a lower-voltage version of PC DRAM Appearing in many laptops and some tablets Attribute LPDDR2/LPDDR3 DDR3L Target Market Mobile Devices Laptop, Desktop, Server IO Specification 1.2V HSUL 1.35V SSTL Command/Addressing 10 pin DDR bus ~22 pin SDR bus Target system Point-to-point DIMM Max I/O Capacitance 2.5pF/1.8pF 2.5pF Max Frequency 1066MTs/1600MT/s 1600MT/s Typical Idle Power* 103mW 115mW Typical self-refresh Power* 5mW 16mW * Comparison of two 2Gbit DDR-800 X16 parts from the same manufacturer Cadence Design Systems, Inc. All rights reserved.
19 LPDDR2 and LPDDR3 (PoP) Package-on-Package (PoP) offers low power and area Compared to packaged parts on PCB, PoP can reduce power, area, and volume Short paths with relatively good signal integrity properties Saves PCB area by using vertical direction May lead to thermal issues if die underneath is generating heat Example cross-section - Not to scale Upper die (for example, DRAM) Flipchip bumps to upper package PCB Upper package PCB Package balls connect upper and lower PCBs Lower die (for example, CPU or app processor) Lower Package PCB with landing pads on top Package balls System PCB Cadence Design Systems, Inc. All rights reserved.
20 LPDDR2 to LPDDR3 transition During the standardization of LPDDR2, the frequency limit of High Speed Unterminated Logic (HSUL) device with no DLL retiming was believed to be 1066MT/s per pin Three main innovations allowed the LPDDR3 standard to go to 1600MT/s with a possible extension to 2133MT/s I/O Capacitance directly affects the maximum frequency LPDDR3 I/O Capacitance was reduced compared to LPDDR2 allowing more speed with less power Signal Integrity Issues Addition of (optional) On-Die Termination (ODT) to LPDDR3 allows more speed but at higher power Interface Training New training modes added Cadence Design Systems, Inc. All rights reserved.
21 How to get from LPDDR2 to LPDDR3 LPDDR2 LPDDR3 Specification release 2009 Specification release May 2012 DDR-1066 (533MHz) DDR-1600 (800MHz) 50% increase 1.2v HSUL Unterminated I/Os Read training I/O Capacitance 2.5pF Low Power consumption 1.2v HSUL I/O with optional On-Die Termination (ODT) Read training, Command/Address (CA) training and Write Leveling I/O Capacitance 1.8pF Expected to be less per bit from lower I/O capacitance and more advanced process Cadence Design Systems, Inc. All rights reserved.
22 Understanding LPDDR3 and Wide I/O Attribute LPDDR3 Wide I/O Specification Release May 2012 December 2011 Bandwidth per die 51.2Gbit/s (X32) 102.4Gbit/s Bandwidth per package 102.4Gbit/s (64-bit dual-channel) 102.4Gbit/s Dies per package Up to 4 (in theory) Up to 4 (in theory) System configurations General Compatibility PoP or normal PCB interconnect Improved, Evolutionary Technology Backwards compatible with LPDDR2 Silicon Interposer or direct chip-to-chip New, Revolutionary Technology May be forwards compatible with future standards Cadence Design Systems, Inc. All rights reserved.
23 Understanding LPDDR3 and Wide I/O LPDDR3 Wide I/O Utilizing existing packaging techniques like Package on Package (PoP) in Can be used in chip-on-board applications (beginning to appear in some tablets) Use a very large number of slow, lower power pins for high bandwidth Utilizing new Through Silicon Via (TSV) wafer processing Package-on-Package Through-Silicon Via Cadence Design Systems, Inc. All rights reserved.
24 Wide I/O DRAM Bandwidth Possible Future non-mobile 2Tbit/s bandwidth? Possible Future non-mobile bit channels? Total 512bits to DRAM? 1066MHz DDR (2133MT/s)? 1Tbit/s bandwidth? JESD229 Standard bit channels Total 512bits to DRAM 200MHz SDR 100Gbit/s bandwidth Possible Future Standard bit channels bits to DRAM? 266MHz DDR? Gbit/s bandwidth? Possible time of introduction Cadence Design Systems, Inc. All rights reserved.
25 Using Through Silicon Vias (TSV) for DRAM Bump pitches represent minimum practical pitch Refer to JEDEC Standard for Wide-IO diameter and pitch Cadence Design Systems, Inc. All rights reserved.
26 General Benefits of TSVs Improved ~10X Improved ~6X Improved ~200X Improved ~6X PCB or PoP Silicon Interposer Direct C2C stacking Number of connections Capacitance per connection Average Connection Length Relative power (proportional to f, c, # connections) Cadence Design Systems, Inc. All rights reserved.
27 Wide-IO DRAM Controller and PHY Challenges Merge existing and new technology New testing requirements Verification PHY I/Os Solutions Start with high performance, low power base architecture Re-add SDR support Add new Wide-IO feature support Create DFI extensions for Controller-PHY connection Extend BIST engine to test for new classes of error introduced by TSV Create memory model of Wide-IO device Extend verification environment for Wide-IO Lightweight PHY, or PHY suitable for characterization? Next generation: probably needs PHY again Need appropriate IOs ESD? Cadence Design Systems, Inc. All rights reserved.
28 What are the challenges? Manufacturing Wide-IO DRAM and assembly: Test Memory Wafer after production using FC bumps Thin the wafer to ~50-100um thickness Form TSVs and fill with metal Requires elevated temperatures extra anneal step Apply backside metal and bumps No opportunity to test here Backside metal bump pitch too fine for most tester heads Handle dies while avoiding mechanical damage They are now the approximate aspect ratio of a postage stamp Attach dies (and interposers, if present) together Does it still work? Cadence Design Systems, Inc. All rights reserved.
29 What are the Wide-IO challenges? Thermal Issues: Where does the heat go? Some new tablets placing LPDDR2 DRAM on opposite side of board from CPU instead of PoP Ecosystem Issues: New Technology How many parties involved in stack production? How are responsibilities divided? How are liabilities divided? Cadence Design Systems, Inc. All rights reserved.
30 SoC Construction LPDDR3: - PoP Ballout dictates SoC Construction - Command and data separated 5-15mm on the SoC? Wide I/O: - TSV Ballout dictates SoC Construction - Each channel contained within 2.5mm Channel A Data CPU CPU Memory Controller CPU Channel A Data CPU Memory Controller Channel A Channel D CPU Memory Controller Channel B Channel C CPU Memory Controller Memory Controller Channel A Cmd CPU CPU Note: Only one channel shown - Extra pipeline flop stages required to transmit data edge to edge; adds latency and power - May be possible to reach all IOs within channel without pipelining Cadence Design Systems, Inc. All rights reserved.
31 System Power Comparison Attribute LPDDR3 2Channel Wide I/O Peak Bandwidth 102Gbit/s 102Gbit/s Core power Predicted to be similar for both technologies I/O Voltage 1.2V 1.2V I/O Capacitance 1.8pF 0.5pF Full-bandwidth, all chip I/ O Power (1/2 f c v 2 ) 64*0.5*1600*cv 2 = 512*0.5*200*cv 2 = 51200cv cv 2 First-order approximation: the difference in IO power is proportional to c Powerdown, Self-Refresh and DPD capability One power state for each channel, one channel per die, 1-2 channels per system 4 channels per die SoC Power PHY may require DLL/PLL DLL/PLL not required Cadence Design Systems, Inc. All rights reserved.
32 Wide-IO Maturity and Ecosystem Silicon Interposer dies on stand at DAC in June 2012 Cadence Wide-IO DRAM Controller Includes expanded MBIST tests for Wide-IO Deployed on two projects Proven in silicon First IP solution to market first deliveries in November 2010 Cadence Wide-IO PHY Deployed on one project first delivery August 2011 Cadence Wide-IO Memory Models (Verification IP) Foundry Reference Flows contain Cadence 3D-IC support Cadence Design Systems, Inc. All rights reserved.
33 Low 250 Power Memory Future Wide I/O DDR3L now appearing in some tablets 128bit Dual-Die LPDDR Wide I/O? Possible Future Standard 64bit DDR-3200 Possible Future Standard Next Generation 64-bit Possible LPDDR3 speed extension bit LPDDR bit Wide LPDDR I/O 1 (SDR) Current Generation Next Generation 64bit LPDDR bit LPDDR bit LPDDR bit Current Generation LPDDR bit LPDDR2-800 Now In design now Shipping Concept Phase Shipping Cadence Design Systems, Inc. All rights reserved.
34 Low 250 Power Memory Future Wide I/O bit Dual-Die LPDDR Wide I/O? Possible Future Standard 150 DDR3L now appearing in some tablets Next Generation bit LPDDR bit Wide LPDDR I/O 1 (SDR) Current Generation Next Generation 64bit LPDDR bit LPDDR bit Current Generation LPDDR bit LPDDR2-800 Now In design now Shipping Concept Phase Shipping Cadence Design Systems, Inc. All rights reserved.
35 Low 250 Power Memory Future Coexistence DDR3L now appearing in some tablets 128bit LPDDR Possible Future Standard 64bit DDR-3200 Possible Future Standard Next Generation 64-bit Possible LPDDR3 speed extension bit LPDDR2-800 LPDDR3 Wide I/O Current Generation Next Generation 64bit LPDDR bit LPDDR bit LPDDR bit Current Generation LPDDR bit LPDDR2-800 Now In design now Shipping Concept Phase Shipping Cadence Design Systems, Inc. All rights reserved.
36 Conclusion The mobile memory future contains both LPDDR and Wide I/O LPDDR3: Evolutionary and proven, but more power Wide I/O: New and exciting, with less power Cadence Memory Solutions include: LPDDR3/LPDDR2/DDR4/DDR3 Controller and PHY Wide I/O Controller and PHY Flash Controller and PHY Memory Models Verification IP Signal Integrity Reference Designs Design, Verification, Physical Verification, and Test tools for TSV-based chip designs Cadence Design Systems, Inc. All rights reserved.
37 Cadence Design Systems, Inc. All rights reserved.
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