Architecture des Ordinateurs I

Transcription

1 Architecture des Ordinateurs I Instruction Set Architectures Paolo.Ienne@epfl.ch EPFL I&C LAP

2 Reminder: New Language Assembly Instructions 0 mov $r1, 0x # $r1 data 1 mov $r2, 0 # $r2 result 2 mov $r3, 1 # $r3 mask 3 mov $r4, 0 # $r4 count 4 loop: and $r5, $r1, $r3 # $r5 = $r1 & $r3 5 add $r2, $r2, $r5 # $r2 = $r2 + $r5 6 srl $r1, $r1, 1 # $r1 = $r1 >> 1 7 add $r4, $r4, 1 # $r4 = $r bne $r4, 32, loop # $r4!= 32 loop 9 fin: Flow Control Registers 2

3 Reminder: Assembly Language & Machine Code Assembly Language Machine Code mov $r1, 0x x mov $r2, x mov $r3, x mov $r4, x loop: and $r5, $r1, $r3 04 0x add $r2, $r2, $r5 05 0x srl $r1, $r1, x add $r4, $r4, x bne $r4, 32, loop 08 0x???????? fin: Problem? Programmer or Compiler Instruction ti Memory 3

4 Reminder: From C (or Java, ) to Machine Code Fig gure: Patter rson & Henn nessy, M K 1998 ArchOr rd focus What is typically written by programmers The last version readable to humans The only version of the program that the processor can understand 4

5 Reminder: Simple General Processor Data Memory Register File ALU Control Logic PC + 1 Instruction Memory 5

6 Reminder: Five Components of a Computer Processor Interfaces Control Out Memory Datapath In 6

7 What s inside a Processor? (I) Functional Units to perform computations Basic ALUs Integer multipliers, dividers, etc. Floating-point g p units General purpose registers Tiny, very fast, very high bandwidth data memory internal to the processor (usually words in a file or group) Integer and Floating Point (to represent real numbers) register files 7

8 What s inside a Processor? (II) Special registers Program g counter (PC) or instruction address register Stack Pointer (SP) see later Flags g not all processors, see later Other registers depending on the specific processor Data connections among these elements Control logic to sequence the operation of these elements 8

9 Reminder: Instruction Set Architecture (ISA) All that one needs to know to program the processor Instructions the processors can execute Registers available, size, etc. Binary encoding of the instructions No (direct) details on the way the processor is built, some indirect impact Interface between HW and SW Example: IA-32/x86 is a very common ISA introduced d by Intel 8086, 80286, 80386, Pentium s (Intel) and Athlon (AMD) are processors conforming to this ISA 9

10 Outline Lesson ISA I Basic structure of Assembly Languages Addressing modes Instruction encoding Lesson ISA II Memory organization i Jumps and Branches Procedures and the stack Summary of ISA classifications 10

11 Example: MIPS Assembly Instructions add a, b, c type of operation (mnemonic) result destination (mnemonic) lw a, addr source operands a = b + c; a = mem[addr]; j addr addresses (data, next instruction) 11 goto addr;

12 Diversion: What is MIPS? ISA of the first commercial Reduced Instruction- Set Computer (RISC), introduced by Hennessy in the early 1980s Used to be one of the high-end workstation processors, but now mostly embeddeds ds We will use MIPS for most examples in ArchOrd Very regular, easy to understand Used in COD Free simulators available for many platforms ftp://ftp.cs.wisc.edu/pub/spim/ p p p 12

13 Diversion: What is Nios II? Simple RISC embedded processor by Altera targeted to their FPGAs ISA very similar il to MIPS, identical in many simple cases A simplified Nios II is the processor that will be implemented in the labs of ArchOrd Very regular, easy to understand Very similar to MIPS, used in most of the examples Compatible with full-fledged versions available from Altera 13

14 Typical Arithmetic and Logic Operations Arithmetic Add Subtract Multiply (often) Divide (sometimes) No big surprises here Logic And (bitwise) Or (bitwise) i Shift Logical Arithmetic Rotate Not (bitwise) Xor o (bitwise) 14

15 Machine Instructions Are Very Regular and Primitive Fixed number of operands (usually 1 or 2) If one needs more, it must be done sequentially, e.g., add a, b, c add a, a, d a = b + c + d + e; add a, a, e Limited combinations of operands, e.g., Max one immediate Some registers for some particular purposes/operations In many recent ISAs, memory operands cannot be specified in arithmetic operations ( load/store architectures) lw a, 1234 sub a, b, a a = b - mem[1234]; 15

16 Instruction Operands Data memory Processor registers Immediate values (= program memory, constants) Peripherals ( pseudo-memory ) ArchOrd II add $s0, $s1, 10 lw $s2, 1234 $s0 = $s1 + 10; $s2 = mem[1234]; 16

17 Registers MIPS has 32 general purpose registers, almost all identical: $0, $1, $2, $30, and$31 They also have other names ($a0, $a1, $t0, $t1, $k2 ) ) $0 (also called $zero) cannot be written and always contains 0 (zero) Other processors have more specialised registers e.g., 80386: AX/EAX Accumulator CX/ECX Count register DX/EDX Data register BX/EBX Base address register SI/ESI Source Index register DI/EDI Destination Index register Etc. 17

18 Outline Lesson ISA I Basic structure of Assembly Languages Addressing modes Instruction encoding Lesson ISA II Memory organization i Jumps and Branches Procedures and the stack Summary of ISA classifications 18

19 Simple Example of General Processor Control Datapath 19

20 How to Fetch the Operands? Addressing Modes (I) Register add $s0, $s1, $s2 s0 = s1 + s2; Immediate (~30%, excl. reg. addressing) add $s0, $s1, 123 s0 = s ; Direct or Absolute add $s0, $s1, (1234) Register Indirect (~10%, excl. reg. addressing) add $s0, $s1, ($s2) s0 = s1 + mem[1234]; s0 = s1 + mem[s2]; Displacement or Relative (~40%, excl. reg. addressing) add $s0, $s1, 123($s2) s0 = s1 + mem[s ]; 20 Syntax here is MIPS-like but these are not all MIPS instructions!

21 Example: Immediate add a, b,

22 Example: Register Indirect add a, b, ($s2) 22

23 How to Fetch the Operands? Addressing Modes (II) Base or Indexed add $s0, $s1, $i5($s2) Auto-increment or -decrement add $s0, $s1, ($s2+) s0 = s1 + mem[s2 + i5]; s0 = s1 + mem[s2]; s2 = s2 + size(s2); PC-Relative add $s0, $s1, 123($pc) s0 = s1 + mem[pc + 123]; Syntax here is MIPS-like but these are not all MIPS instructions! 23

24 Remarks on Addressing Modes (I): Minor Syntactic Issues Mnemonics, register names and syntax (e.g. use of () s) vary widely across assembly languages of different ISA/processors Sometimes different flavours of an operation depending d on the addressing modes sub $s0, $s1, $s2 subi $s0, $s1, 1234 Pseudoinstructions translate new instructions into existing ISA instructions mov $s0, $s1 addi $s0, $s1, 0 or mov $s0, $s1 add $s0, $s1, $zero 24

25 Remarks on Addressing Modes (II): Restrictions on the Availability Typically, more than one addressing mode at once in many operations addi $s0, $s1, 1234 Some processors support richer addressing modes, some much less Some assembly languages have implicit destinations (e.g., x86) hence destination must be one of the operands ADD R1, R2 add $s1, $s1, $s2 Only a very limited combination of sources and destinations is generally possible Availability of addressing modes is a major characteristic of an ISA! 25

26 Addressing Modes Map on Physical Processor Resources For instance, very seldom ISAs support more than one immediate and/or one memory access per instruction An ISA does not define (only) a semantic but (implicitly) cty) a minimal set of resources for the processor! An addressing mode somehow maps on a set of physical resources (buses, muxes, gates) in the processors and resources are limited Guess why the following is not available in MIPS add $s0, (1234), ($s1) 26

27 Example: Displacement add a, b, 123($s2) 27

28 MIPS Loads and Stores: A Load-Store Architecture In MIPS, only two classes of instructions access the data memory: Store and Load sw $s1, 123($s2) mem[s ] = s1; lw $s1, 123($s2) s1 = mem[s ]; All other instructions use registers (i.e., load variables in registers first and store destination registers after) Other (usually older) architectures do not have this restriction but fast implementations are more difficult to build 28

29 Outline Lesson ISA I Basic structure of Assembly Languages Addressing modes Instruction encoding Lesson ISA II Memory organization i Jumps and Branches Procedures and the stack Summary of ISA classifications 29

30 MIPS Instruction Encoding: Assembly Language Machine Code Fields 30

31 MIPS Instruction Encoding: Example Remember: instructions are encoded as numbers! (as anything else in a computer ) 31

32 Example on Instruction Encoding Determine the instruction format for each instruction of the following MIPS program: The binary values of each field of the instruction. The hexadecimal value of the instruction. begin: addi $t0, $zero, 0 addi $t1, $zero, h h loop: slt $t2, $a0, $t1 bne $t2, $zero, finish add $t0, $t0, $t1 addi $t1, $t1, 2 j loop A h h h h h finish: add $v0, $t0, $zero h 32

33 MIPS Instruction Encoding add rd, rs, rt sub rd, rs, rt addirt, rs, imm slt rd, rs, rt 0 rs rt rd 0 0x rs rt rd 0 0x rs rt imm rs rt rd 0 0x2a (R-Type) (R-Type) (I-Type) (R-Type) j target 2 target (J-Type) 6 26 bne rs, rt, label 5 rs rt offset (I-Type) beq rs, rt, offset rs rt offset (I-Type) lw rt, offset(rs) 0x23 rs rt offset (I-Type) sw rt, offset(rs) 0x2B rs rt offset (I-Type) Reference: COD, p. A-53 and following 33

34 MIPS Register Naming MIPS registers are referred with other names which reflect some conventional use (see later): Name Number $zero 0 $v0 $v1 2 3 $a0 $a3 4 7 $t0 $t $s0 $s Reference: COD, p. A-23 34

35 Example 1 addi $t1, $zero, 1 => I-Format addi: Opcode = (6-Bits) $t1: Register argument #2 = (5-Bits) $zero: Register argument #1 = (5-Bits) 1: Immediate value = (16-Bits) Opcode Register Register Immediate argument #1 argument # b => h 35

36 Example 2 slt $t2, $a0, $t1 => R-Format slt: Defines 2 fields of the instruction: Opcode = (6-Bits) Function Code = (6-Bits) $t2: Register argument #3 = (5-Bits) $a0: Register argument #1 = (5-Bits) $t1: Register argument #2 = (5-Bits) Opcode Register argument #1 Register argument #2 Register argument #3 Shift Amount Function Code b => Ah 36

37 Instruction Encoding: Typical x86 Instruction Formats Note: much less regular! 1 instruction: from 1 to 17 bytes! How many bits to encode the operation field in this figure? Why do you think this could be a problem? Patterson & Hennessy y, MK

38 Exercise on Instruction Encoding Determine the instruction format for each instruction of the following MIPS program: The binary values of each field of the instruction. The hexadecimal value of the instruction. loop: lw $v1, 0($a0) addi $v0, $v0, 1 sw $v1, 0($a1) addi $a0, $a0, 1 addi $a1, $a1, 1 bne $v1, $zero, loop 38

39 A Correct 1-Counter Program 0 lw $t0, 0($zero) # $t0 data 1 add $t1, $zero, $zero # $t1 = 0 (result) 2 addi $t2, $zero, 1 # $t2 = 1 (mask) 3 addi $t3, $zero, 32 # $t3 = 32 (count) 4 loop: and $t4, $t0, $t2 # $t4 = $t0 & $t2 5 add $t1, $t1, $t4 # $t1 = $t1 + $t4 6 srl $t0, $t0, 1 # $t0 = $t0 >> 1 7 addi $t3, $t3, -1 # $t3 = $t3-1 8 bne $t3, $zero, loop # $t3!= 0 loop 9 fin: sw $t1, 10($zero) # $t1 count Memory 0: data 9: 10: result 39

40 Summary ISA is a contract between programmers and hardware designers Programs are stored in memory as sequences of numbers representing machine instructions (machine code) Mnemonic instructions (assembly language) are associated with these numbers for readability Machine instructions are very simple: only few basic operations, limited number of operands, some rather simple schemes to access operands Typically, simpler ISAs mean simpler (and faster) hardware Within real programs, even the simplest tasks may require several (hundreds, thousands, ) machine instructions 40

41 Exercises Understanding and using assembly language: COD 2 nd ed.: 3.1, 3.2, 3.6 Mapping i high-level h l language on MIPS: COD 2 nd ed.: 3.4, 3.5 Encoding and relevant limitations: COD 2 nd ed.: 3.7, 3.12 Use of control flow instructions COD 2 nd ed.: 3.9 Generality of processors COD 2 nd ed.: 3.29, (fun!) 41

42 Outline Lesson ISA I Basic structure of Assembly Languages Addressing modes Instruction encoding Lesson ISA II Memory organization i Jumps and Branches Procedures and the stack Summary of ISA classifications 42

43 Memory Organization: Bytes, Words, Half-Words, Double-Words Historically, memory organized in bytes Byte is always 8 bits, Word is typically the natural size of the processor, or 32 bits (= 4 bytes) in many cases Often processors need (or have better performance with) alignment, e.g., accessing 32-bit words only on addresses which are multiple of four. 43

44 8-bit, 16-bit, 32-bit, 64-bit Processors ISAs (and not processors) are typically classed depending on their natural word size Typically the size of the integer registers or the largest integer handled in arithmetic and logic instructions Implementations may use internally smaller ALUs (e.g., for cheap implementations of the ISA) Larger word sizes can be better on some applications (avoid performing operations in smaller pieces) but inefficient on others (e.g., to manipulate ASCII characters coded on 8 bits) 44

45 8-bit, 16-bit, 32-bit, 64-bit Processors: A Little of History The first widespread microprocessors (6502, 6809, 8080, 8085, Z80) were all 8-bit hence the organization of memory in bytes 8086 was a 16-bit ISA and has been successively extended to 32-bit (Intel 80x86) 68k was a 32-bit ISA but was first implemented at 16- (MC68000) and 8-bit, and afterwards at 32-bit (MC68020) Most processors in PCs and workstations are 32-bit (all Intel low-end Pentiums, Motorola and IBM PowerPC, ) 64-bit processors are used mostly in servers (Sun UltraSparc, IBM Power6, Intel Itanium, high-end AMD and Intel, ) 45

46 Big Endian and Little Endian Processors When storing a multibyte word on several bytes, one has two choices: store the most or least significant part of the word in byte with the first (lowest) address: sw , (1000) Address Data Little Endians e.g., x86, DEC3100, Nios II Address Data Big Endians e.g., 68k, PowerPC, Sparc 46

47 Example: Accessing Array Elements in Assembly Language Array A of integers (32-bit): A[i] = A[i] + b; Assume A $s0, i $s1, and b $s2 Compute the actual byte displacement, add to the base array, load the value, perform the add, and store back: add $t1, $s1, $s1 # t1 = 2 * s1 add $t1, $t1, $t1 # t1 = 4 * s1 add $t1, $s0, $t1 # t1 = s0 + 4 * s1 lw $t0, 0($t1) # t0 = mem[s0 + 4 * s1] add $t0, $t0, $s2 # t0 = t0 + s2 sw $t0, 0($t1) # mem[s0 + 4 * s1] = t0 47

48 Spilling Registers Register files are an extremely fast but extremely small memory to hold frequently used values Any practical program has much more variables ab than physical registers s in the processor In practice, registers are reused for many variables and variables not needed at a given time or used infrequently are spilled to memory to free resources Compilers usually take care of spilling 48

49 Outline Lesson ISA I Basic structure of Assembly Languages Addressing modes Instruction encoding Lesson ISA II Memory organization i Jumps and Branches Procedures and the stack Summary of ISA classifications 49

50 Programs Are Never Straight Sequences of Instructions One needs to make decisions for instance: To repeat a given part of program a fixed number of times To execute different pieces of code depending on some intermediate result or piece of data Essential feature for the generality of a processor! 50

51 Jumps and Branches Jumps are unconditional changes in the flow (as goto in C) j 1234 (think of li $pc, 1234 ) ) Branches are conditional changes in the flow (used to implement the equivalent of if, for, while, etc. C constructs) beq $s1, $s2, 1234 if (s1 == s2) {goto 1234;} 51

52 MIPS Approach to Conditions: Instructions which Test Registers Branch instructions compare two registers for equality or inequality beq $s1, $s2, 1234 bne $s1, $s2, 5678 Set on instructions prepare boolean information in registers for more general branches slt $t0, $s1, $s2 # if (s1 < s2) {t0 = 1;} # else {t0 = 0;} bne $t0, $zero, 3456 # if (t0!= 0) {goto 3456;} if (s1 < s2) {goto 3456;} 52

53 Intel, Motorola, et al. Approach: Flags or Condition Codes (I) For each ALU operation (e.g., ADD A, B), some boolean information is always stored in the bits (flags) of a special register Result is zero? Sets or resets Z Result is positive? Sets or resets P Operation caused an overflow? Sets or resets C Additional operations only to prepare p flags without modifying registers (e.g., CMP A, B) 53

54 Intel, Motorola, et al. Approach: Flags or Condition Codes (II) Special branch instruction for each flag: JZ or JE Jump if zero or if equal JNZ or JNE Jump if nonzero or if not equal JP Jump if positive JN Jump if negative JC Jump if carry (or if overflow) JNC Jump if no carry 54

55 Outline Lesson ISA I Basic structure of Assembly Languages Addressing modes Instruction encoding Lesson ISA II Memory organization i Jumps and Branches Procedures and the stack Summary of ISA classifications 55

56 A Special Kind of Jump: Procedures and Functions One wants to do several things 1. Prepare parameters somewhere 2. Transfer control (jump) to the procedure 3. Free resources (e.g., save used registers) 4. Perform task 5. Prepare result somewhere 6. Return to calling program flow 56

57 Simple Approach to Transfer Control to and from a Procedure Multiple calling points, thus need to store during a call the return address somewhere e.g., in a special register ($ra in MIPS, ra in Nios II) jal : jr $ra # equivalent to something like: # add $ra, $pc, 4 and j 1234 # rest of the program, pointed by $ra # code of the procedure # return to caller Nios II is practically identical, but jal is called call and jr $ra must be done with ret (the op codes are as in many processors but here with a slightly different semantic than most, where call and ret use the stack see a few slides below for an example) 57

58 Simple Approach to Pass Parameters to and from a Function Define conventional register ($a0-$a3 and $v0- $v1 in MIPS, r4-r7 and r2-r3 in Nios II) jal 1234 # call function 1234 # return values are in $v0 and $v1 1234: sub $s0, $a0, $a1 # use parameters in $a0 to $a3 # rest of function code add $v0, $s1, $s2 # produce results in $v0 and $v1 jr $ra # return to caller 58

59 Several Problems with this Approach What if I need to send more than four parameters? What t if I need to return more than two values? What if I need to call a procedure/function from inside another procedure/function? And also: if I need to free registers, where do I store temporarily their values (remember: I need to hand back the machine to the caller in exactly the state I found it!) 59

60 Stacks: A Last-in First-out Queue for Temporary Storage Place (push) and retrieve (pop) data from a free area of memory, and use a register (stack pointer) to keep track of usage By historical habit, the queue is filled from higher h addresses toward lower ones $sp $sp xxxx Push on little-endian endian 1003 xxxx machine 60

61 Example: Function Call Saving Parameters on the Stack (I) Recursive function (factorial): int fact (int n) /* fact(5) = 5 * 4 * 3 * 2 * 1 */ /* = 5 * fact(4) */ { if (n <= 1) return 1; else return (n * fact(n 1)); }; 61

62 Example: Function Call Saving Parameters on the Stack (II) fact: addi $sp, $sp, -8 # make space on stack for 2 items sw $ra, 4($sp) # push return address (from ra) sw $a0, 0($sp) # push n (from a0) sgti $t0, $a0, 1 # if (n > 1) bne $t0, $zero, rec # goto recs; # else addi $v0, $zero, 1 # v0 = 1; (value to return) addi $sp, $sp, 8 # hand back stack space (no pop) jr $ra # return to caller rec: addi $a0, $a0, -1 # a0 = n 1; rcall: jal fact # v0 = fact(n 1); lw $a0, 0($sp) # pop n (into a0) lw $ra, 4($sp) # pop return address (into ra) addi $sp, $sp, 8 # hand back stack space mul $v0, $a0, $v0 # v0 = n * fact(n 1)); (ret val) jr $ra # return to caller 62

63 Example: Function Call Saving Parameters on the Stack (III) Each call adds two 32-bit words on the stack addi $a0, $zero, 5 # a0 = 5; mycall: jal fact # call fact(5); $sp $sp rcall $sp xxxx 1000 mycall xxxx 1000 mycall xxxx Before call During first call During second call 63

64 Stacks Are Extremely Useful and Used Very Often MIPS and Nios II treat $sp as a rather normal register Other architectures have special instructions to manipulate the stack e.g., x86: PUSH EAX POP EAX CALL 1234 RET # something like: # SUB SP, 4 # MOVE (SP), EAX # something like: # MOVE EAX, (SP) # ADD SP, 4 # something like: # PUSH PC + 4 # JUMP 1234 # something like: # POP PC 64

65 Spilling Registers Costs Time MIPS (and Nios II) use conventions in register usage to reduce spilling and avoid using the stack in simple cases: Registers $t0-$t9 (or r8-r15 in Nios II) need not be preserved by a called procedure Registers $s0-$s7 (or r16-r23 in Nios II) must be preserved by a called procedure, which should save them on the stack if it needs them MIPS (and Nios II) have general purpose registers, but several software conventions (known to the compiler) on how to use them 65

66 Outline Lesson ISA I Basic structure of Assembly Languages Addressing modes Instruction encoding Lesson ISA II Memory organization i Jumps and Branches Procedures and the stack Summary of ISA classifications 66

67 Typical ISA Classifications (I) 1. CISC vs. RISC architectures There is no precise definition Approximately the following statements hold: CISC RISC There are relatively few registers, often not functionally equivalent Instruction encoding is complex and instructions have a variable size There are many sorts and rather complex addressing modes The execution pattern is very variable (some instructions take very few cycles cles while some take tens of cycles) Most Intel processors (IA-32, that is 80x86 and Pentium I/II/III/IV) / / are CISC 67 More in ArchOrd II There are 2 N (almost) completely equivalent registers (typically 32-64) Instruction encoding is very regular and there are only 1 or 2 instruction sizes They are all load/store architectures The execution pattern is very regular (e.g., all instructions take 5 cycles) cles) MIPS, Alpha, Sparc, and most recent ISAs are RISC

68 Typical ISA Classifications (II) 2. Load/Store architectures Load/store architectures only access memory with load and store instructions; arithmetic and logic instructions operate exclusively on the registers Practically all modern architectures are load/store Some people identify RISC with load/store 3. 8-, 16-, 32-, 64-bit architectures Approximately, indicates the number of bits in the registers, the precision of the ALU, etc. It is a particular form of parallelism: to multiply 64-bit data on a32bit 32-bit ISA, one needs four 32-bit multiplications and some additions; on a 64-bit ISA, a single multiplication suffices The number of bits increase with time and technology improvements 68

69 Typical ISA Classifications (III) 4. Harvard vs. Unified architectures All common general-purpose ISAs are Unified Most modern processors are actually implemented as Harvard architectures, but this is completely hidden to the programmer (i.e., the ISA is Unified) ArchOrd II Harvard Architecture Unified Architecture Instruction Memory Data Memory Unified Memory ima imd dma dmd A D Processor Processor 69

70 Example of Assembly Code to Understand The following code describes a function that can be called by a main program: fct: addi $sp, $sp, -4 sw $s0, 0($sp) add $s0, $zero, $zero L1: add $t0, $a0, $s0 lb $t1, 0($t0) addi $s0, $s0, 1 bne $t1, $zero, L1 addi $s0, $s0, -1 add $v0, $s0, $zero lw $s0, 0($sp) addi $sp, $sp, 4 jr $ra 70

71 Questions on the Previous Example Describe in one sentence what this code does Write a comment for each line Draw the stack before, during and after the function call. Show the progression of the Stack Pointer register ($sp) Represent an array of data in the memory and assign to it an arbitrary position in memory. Give the value of $a0 that will be passed to the function and the value returned in $v0 What can one say about $t0 and $t1? What is the purpose of the following instruction? addi $s0, $s0, -1 71

72 References and Where to Learn More Reference: COD, 4 th ed., Chapter 2 To learn more: MIPS ISA (very simple): COD, 4 th ed., Appendix E.3 Intel IA-32/x86 ISA (rich and complex): Miller, An Assembly Language Introduction to Computer Architecture; Using the Intel Pentium, 1999 Sparc ISA: Weaver and Germond, The Sparc Architecture Manual Version 9 A survey of RISC Architectures: COD, 4 th ed., Appendix E 72

73 Summary Memory organization somehow clumsy due to historical reasons, and different approaches in different processors Jumps and branches to modify the program flow; different approaches to test conditions Subroutines and functions: the idea of stack as simple dynamic storage on demand Again: within real programs, even the simplest tasks require several machine instructions, because in assembly language all bookkeeping is explicit 73

74 Nios II Summary Basic Instructions Instructions expressing basic arithmetic and logic operations only operate on registers and at most one 16-bit constant (load/store architecture) No unsigned operations add sub and or xor sll rol rd, rs, rt rd, rs, rt rd, rs, rt rd, rs, rt rd, rs, rt rd, rs, rt rd, rs, rt and many others addi andi ori xori slli roli rt, rs, const rt, rs, const rt, rs, const rt, rs, const rt, rs, const rt, rs, const and many others To load an immediate 16-bit value in the upper half of a register movhi rd, const 74

75 Nios II Summary Memory Access Instructions accessing memory do not perform any computation (load/store architecture) ldw stw rt, offset(rs) rt, offset(rs) Addresses must be aligned, that is they must be multiples of 4 Accesses can also be made to bytes and need not to be aligned ldb stb rt, offset(rs) rt, offset(rs) Addresses contain bytes, and four consecutive addresses contain a 32-bit word. Nios II is little endian and the most significant byte is stored at the highest address 75

76 Nios II Summary Branches, Tests, and Calls There exist a jump instruction and branches jmp rs beq rs, rt, addr blt rs, rt, addr Comparison instructions ti are used for more complex branches cmpge rd, rs, rt cmpgeu rd, rs, rt cmpgei rt, rs, const Procedure calls use the special call or callr instructions call addr ret 76

77 Nios II Summary Register Conventions Registers are usually perfectly equivalent but some usage conventions are defined A few are really somehow different, such as zero or ra (implicit destination of call and source of ret) zero (r0) Constant 0 at (r1) Assembler temporary r2-r3 Function return values r4-r7 Function arguments r8-r15 Temporaries r16-r23 Saved temporaries sp (r27) Stack Pointer ra (r31) Return address and a few more 77

78 MIPS Summary Basic Instructions Instructions expressing basic arithmetic and logic operations only operate on registers and at most one 16-bit constant (load/store architecture) Most operations exist also in a unsigned version (surprisingly ) i add addu sub subu and or xor rd, rs, rt rd, rs, rt rd, rs, rt rd, rs, rt rd, rs, rt rd, rs, rt rd, rs, rt and many others addi rt, rs, const addiu rt, rs, const subi rt, rs, const andi rt, rs, const ori rt, rs, const xori rt, rs, const sll rt, rs, const and many others To load an immediate 16-bit value in the upper half of a register lui rd, const 78 NOT A LOAD! (despite the unfortunate Ienne name) 2007

79 MIPS Summary Memory Access Instructions accessing memory do not perform any computation (load/store architecture) lw sw rt, offset(rs) rt, offset(rs) Addresses must be aligned, that is they must be multiples of 4 Accesses can also be made to bytes and need not to be aligned lb sb rt, offset(rs) rt, offset(rs) Addresses contain bytes, and four consecutive addresses contain a 32-bit word. The way y( (order) these 4 bytes are taken to form the word depends whether the processor is little-endian or big-endian 79

80 MIPS Summary Branches, Tests, and Calls There exist a jump instruction and basic branches j beq bne addr rs, rt, addr rs, rt, addr More complex branches are implemented using set instructions ti slt rd, rs, rt sltu rd, rs, rt slti rt, rs, const Procedure calls use the special jump-and-link instruction jal addr jr $ra 80

81 MIPS Summary Register Conventions Registers are usually perfectly equivalent but some usage conventions are defined A few are really somehow different, such as $zero or $ra (implicit destination of jal) $zero Constant 0 $v0-$v1 Function return values $a0-$a3 Function arguments $t0-$t9$ Temporaries $s0-$s7 Saved temporaries $k0-$k1 Reserved for kernel $sp Stack pointer $ra Return address and a few more 81