Development Board EPC9004 Quick Start Guide. 200 V Half-Bridge with Gate Drive, Using EPC2012

Transcription

1 Development oard EPC900 Quick Start Guide 00 V Half-ridge with Gate Drive, Using EPC0

2 DESCRIPTION The EPC900 development board is a 00 V maximum device voltage, maximum output current, half bridge with onboard gate drives, featuring the EPC0 enhancement mode (egan ) field effect transistor (FET). The purpose of this development board is to simplify the evaluation process of the EPC0 egan FET by including all the critical components on a single board that can be easily connected into any existing converter. The EPC900 development board is x. and contains not only two EPC0 egan FET in a half bridge configuration using two Texas Instruments UCC7 gate drivers as well as supply and bypass capacitors. The board contains all critical components and layout for optimal switching performance. There are also various probe points to facilitate simple waveform measurement and efficiency calculation. complete block diagram of the circuit is given in Figure. For more information on the EPC0 egan FET please refer to the datasheet available from EPC at The datasheet should be read in conjunction with this quick start guide. Table : Performance Summary (T = C) SYMOL PRMETER CONDITIONS MIN MX UNITS V DD Gate Drive Input Supply Range 7 V V IN us Input Voltage Range 0 V V OUT Switch Node Output Voltage 00 V I OUT Switch Node Output Current * V PWM PWM Logic Input Voltage Threshold Input High. V Input Low 0. V Minimum High State Input Pulse Width VPWM rise and fall time < 0ns 00 ns Minimum Low State Input Pulse Width VPWM rise and fall time < 0ns 00# ns * ssumes inductive load, maximum current depends on die temperature actual maximum current with be subject to switching frequency, bus voltage and thermals. # Dependent on time needed to refresh high side bootstrap supply voltage.

3 Quick Start Procedure Development board EPC900 is easy to set up to evaluate the performance of the EPC0 egan FET. Refer to Figure for proper connect and measurement setup and follow the procedure below:. With power off, connect the input power supply bus to +V IN (J, J) and ground / return to V IN (J7, J8).. With power off, connect the switch node of the half bridge V OUT (J, J) to your circuit as required.. With power off, connect the gate drive input to +V DD (J, Pin-) and ground return to V DD (J, Pin-).. With power off, connect the input PWM control signal to PWM (J, Pin-) and ground return to any of the remaining J pins.. Turn on the gate drive supply make sure the supply is between 7 V and V range.. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 00 V on V OUT ). 7. Turn on the controller / PWM input source and probe switching node to see switching operation. 8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior, efficiency and other parameters. 9. For shutdown, please follow steps in reverse. NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure for proper scope probe technique. THERML CONSIDERTIONS The EPC900 development board showcases the EPC0 egan FET. lthough the electrical performance surpasses that for traditional Si devices, their relatively smaller size does magnify the thermal management requirements. The EPC900 is intended for bench evaluation with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these devices, but care must be taken to not exceed the absolute maximum die temperature of C. NOTE. The EPC900 development board does not have any current or thermal protection on board.

4 V DD V OUT Gate Drive Supply Level Shift, Logic and Dead-time djust UCC7 Gate driver regulator UCC7 Gate driver regulator Half-ridge with ypass V IN V OUT 7 V V V DD Supply + Gate Drive Supply (Note Polarity) + + <0 V V IN V Switch Node V IN Supply (For Efficiency Measurement) External Circuit I IN Figure : lock Diagram of EPC900 Development oard PWM Input EPC EFFICIENT POWER CONVERSION Figure : Proper Connection and Measurement Setup Do not use probe ground lead Ground probe against TP Figure : Waveforms for V IN = 0 V to V/ (00kHz) uck converter CH: VPWM Input voltage CH: (I OUT) Switch node current CH: (V OUT) Switch node voltage EPC EFFICIENT POWER CONVERSION Figure : Proper Measurement of Switch Node V OUT Minimize loop Place probe in large via at OUT

5 Table : ill of Material Item Qty Reference Part Description Manufacturer / Part # C, C, C0, C Capacitor, uf, 0%, V, XR Murata, GRM88RE0KD C, C7 Capacitor, 00pF, %, 0V, NP0 TDK, C08C0GH0J C, C7 Capacitor, 0.uF, 0%, 0V, X7R TDK, CX7REM C8, C9, C, C Capacitor, 0.uF, 0%, V, X7R TDK, C00X7RCK D, D Schottky Diode, 0V Diodes Inc., SDM0U0-7 D Diode, 00V Diodes Inc.,VWS-7-F 7 J Connector pins of Tyco, J Connector pins of Tyco, J, J, J, J, J7, J8 Connector FCI, 80-HLF 0 Q, Q egan FET EPC, EPC0 R Resistor, 0.0K, %, /8W Stackpole, RMCF00FT0K0 R, R, R Resistor, 0 Ohm, /8W Stackpole, RMCF00FT00R0 R, R Diode, 0V Diodes Inc.,S0LP-7 R Resistor, 00 Ohm, %, /8W Stackpole, RMCF00FT00R R Resistor, 90 Ohm, %, /8W Stackpole, RMCF00FT90R TP, TP Test Point Keystone Elect, 0 7 TP Connector /0th of Tyco, U I.C., Logic Fairchild, NC7SZ00LX 9 U I.C., Isolator Silicon Laboratories, Si80 0 U I.C., Logic Fairchild, NC7SZ08LX U, U7 I.C., Gate driver Texas Instruments, UCC7 0 C, C capacitor 0 P, P Potentiometer 0 R, R resistor 0 U I.C.

6 7 - Vdc J CON C0 uf, V D V TP Keystone 0 J CON C J CON J9 CON PWM PWM R Zero R 0k R U GND NC7SZ00LX VDD Y R Zero U GND NC7SZ08LX P C uf, V VDD D Y SDM0U0 R 90 Ohm VCC C7 00p C uf, V P D SDM0U0 R 00 Ohm C uf, V C 00p U Si80 U R Zero C uf, V C8 0.uF, V C9 0.uF, V U VDD UCC7 U7 VDD UCC7 REG REG VREF VSS VREF VSS 7 7 C 0.uF, V R S0LP VCC C 0.uF, V R S0LP SW OUT Q EPC0 J CON J CON Q EPC0 C 0.uF, 0V C R C7 0.uF, 0V J CON TP CON J7 CON 0V Max GND C TP Keystone 0 J8 CON D 00V Half-ridge with Gate Drive, using EPC0 Rev.0 D

7 Contact us: Renee Yawger WW Marketing Office: Mobile: Stephen Tsang Sales, sia Mobile: hasy Nair Global FE Support Office: Mobile: Peter Cheng FE Support, sia Mobile: EPC Products are distributed exclusively through Digi-Key. Development oard / Demonstration oard Notification The EPC900 board is intended for product evaluation purposes only and is not intended for commercial use. s an evaluation tool, it is not designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. s board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 00% RoHS compliant. No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. EPC reserves the right at any time, without notice, to change said circuitry and specifications.