Laboratory Exercise 1

Transcription

1 Laboratory Exercie Switche, Light, and Multiplexer The purpoe of thi exercie i to learn how to connect iple input and output device to an FPGA chip and ipleent a circuit that ue thee device. We will ue the witche SW 9 on the DE-SoC board a input to the circuit. We will ue light eitting diode (LED) and 7-egent diplay a output device. Part I The DE-SoC, DE-CV, and DE-5 board provide the following witche and light: Board Nuber of Switche Nae of Switche Nuber of Light Nae of Light DE-CV SW 9 LEDR 9 DE-SoC SW 9 LEDR 9 DE-5 8 SW 7 8 LEDR 7 Table : DE-erie board peripheral The witche can be ued for input, and the light can be ued a output device. Figure how a iple Verilog odule that ue thee witche and how their tate on the LED. Since there are ultiple witche and light it i convenient to repreent the a vector in the VHDL code, a hown. We have ued a ingle aignent tateent for all LEDR output, which i equivalent to the individual aignent: LEDR(9) <= SW(9); LEDR(8) <= SW(8);... LEDR() <= SW(); The DE-erie board have hardwired connection between it FPGA chip and the witche and light. To ue the witche and light it i neceary to include in your Quartu II project the correct pin aignent, which are given in your board uer anual. For exaple, the DE-SoC anual pecifie that SW i connected to the FPGA pin AB and LEDR i connected to pin V6. A good way to ake the required pin aignent i to iport into the Quartu II oftware the pin aignent file for your board, which i provided on the Univerity Progra ection of Altera web ite. The procedure for aking pin aignent i decribed in the tutorial Quartu II Introduction uing Verilog Deign, which i alo available fro Altera. It i iportant to realize that the pin aignent in the file are ueful only if the pin nae that appear in thee file are exactly the ae a the port nae ued in your Verilog odule. The file ue the nae SW[]... SW[n - ] and LEDR[]... LEDR[n - ], where n i the nuber of light and witche your board ha. Thi i the reaon that we have ued thee nae in Figure.

2 LIBRARY ieee; USE ieee.td_logic_6.all; - - Siple odule that connect the SW witche to the LEDR light ENTITY part IS PORT ( SW : IN STD_LOGIC_VECTOR(9 DOWNTO ); LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO )); - - red LED END part; ARCHITECTURE Behavior OF part IS BEGIN LEDR <= SW; END Behavior Figure : VHDL code that ue the DE-SoC and DE-CV board witche and light. (Part a) LIBRARY ieee; USE ieee.td_logic_6.all; - - Siple odule that connect the SW witche to the LEDR light ENTITY part IS PORT ( SW : IN STD_LOGIC_VECTOR(7 DOWNTO ); LEDR : OUT STD_LOGIC_VECTOR(7 DOWNTO )); - - red LED END part; ARCHITECTURE Behavior OF part IS BEGIN LEDR <= SW; END Behavior Figure. VHDL code that ue the DE-5 board witche and light. (Part b) Perfor the following tep to ipleent a circuit correponding to the code in Figure on the DE-erie board.. Create a new Quartu II project for your circuit. Select the target chip, that correpond to your DE-erie board. Refer to Table for a lit of device.. Create a VHDL entity for the code in Figure and include it in your project. 3. Include in your project the required pin aignent for your DE-erie board, a dicued above. Copile the project.. Download the copiled circuit into the FPGA chip by uing the Quartu II Prograer tool (the procedure for uing the Prograer tool i decribed in the tutorial Quartu II Introduction). Tet the functionality of the circuit by toggling the witche and oberving the LED. Board DE-CV DE-SoC DE-5 Device Nae Cyclone IVE 5CEBAF3C7 Cyclone V SoC 5CSEMA5F3C6 Cyclone IVE EPCE5F9C7 Table : DE-erie FPGA device nae

3 Part II Figure a how a u-of-product circuit that ipleent a -to- ultiplexer with a elect input. If = the ultiplexer output i equal to the input x, and if = the output i equal to y. Part b of the figure give a truth table for thi ultiplexer, and part c how it circuit ybol. x y a) Circuit x y x y b) Truth table c) Sybol Figure : A -to- ultiplexer. The ultiplexer can be decribed by the following VHDL tateent: <= (NOT () AND x) OR ( AND y); You are to write a VHDL entity that include four aignent tateent like the one hown above to decribe the circuit given in Figure 3a. Thi circuit ha two four-bit input, X and Y, and produce the four-bit output M. If = then M = X, while if = then M = Y. We refer to thi circuit a a four-bit wide -to- ultiplexer. It ha the circuit ybol hown in Figure 3b, in which X, Y, and M are depicted a four-bit wire. x 3 y 3 3 x y X Y M x y a) Circuit b) Sybol Figure 3: A four-bit wide -to- ultiplexer. 3

4 Perfor the tep lited below.. Create a new Quartu II project for your circuit.. Include your VHDL file for the four-bit wide -to- ultiplexer in your project. Ue witch SW 9 a the input, witche SW 3 a the X input and SW 7 a the Y input. Diplay the value of the input on LEDR 9, connect the output M to LEDR 3, and connect the unued LEDR light to the contant value. 3. Include in your project the required pin aignent for your DE-erie board. A dicued in Part I, thee aignent enure that the port of your Verilog code will ue the pin on the FPGA chip that are connected to the SW witche and LEDR light.. Copile the project, and then download the reulting circuit into the FPGA chip. Tet the functionality of the four-bit wide -to- ultiplexer by toggling the witche and oberving the LED. Part III In Figure we howed a -to- ultiplexer that elect between the two input x and y. For thi part conider a circuit in which the output ha to be elected fro three input u, v, and w. Part a of Figure how how we can build the required 3-to- ultiplexer by uing two -to- ultiplexer. The circuit ue a -bit elect input and ipleent the truth table hown in Figure b. A circuit ybol for thi ultiplexer i given in part c of the figure. Recall fro Figure 3 that a four-bit wide -to- ultiplexer can be built by uing four intance of a -to- ultiplexer. Figure 5 applie thi concept to define a two-bit wide 3-to- ultiplexer. It contain two intance of the circuit in Figure a. u v w a) Circuit u v w w u v w b) Truth table c) Sybol Figure : A 3-to- ultiplexer.

5 U V W M Figure 5: A two-bit wide 3-to- ultiplexer. Perfor the following tep to ipleent the two-bit wide 3-to- ultiplexer.. Create a new Quartu II project for your circuit.. Create a VHDL entity for the two-bit wide 3-to- ultiplexer. Connect it elect input to witche SW 9 8, and ue witche SW 5 to provide the three -bit input U to W. Connect the output M to the red light LEDR. 3. Include in your project the required pin aignent for your DE-erie board. Copile the project.. Download the copiled circuit into the FPGA chip. Tet the functionality of the two-bit wide 3-to- ultiplexer by toggling the witche and oberving the LED. Enure that each of the input U to W can be properly elected a the output M. Part IV The objective of thi part i to diplay a character on a 7-egent diplay. The pecific character diplayed depend on a two-bit input. Figure 6 how a 7-egent decoder odule that ha the two-bit input c c. Thi decoder produce even output that are ued to diplay a character on a 7-egent diplay. Table 3 lit the character that hould be diplayed for each valuation of c c for your DE-erie board. Three character are included plu the blank character, which i elected for code. The even egent in the diplay are identified by the indice to 6 hown in the figure. Each egent i illuinated by driving it to the logic value. You are to write a Verilog odule that ipleent logic function that repreent circuit needed to activate each of the even egent. Ue only iple VHDL aignent tateent in your code to pecify each logic function uing a Boolean expreion. c c 7-egent decoder Figure 6: A 7-egent decoder. c c DE-CV Character DE-SoC Character DE-5 Character d d d E E E Table 3: Character code for the DE-erie board. 5

6 Perfor the following tep:. Create a new Quartu II project for your circuit.. Create a VHDL entity for the 7-egent decoder. Connect the c c input to witche SW, and connect the output of the decoder to the HEX diplay on your DE-erie board. The egent in thi diplay are called HEX, HEX,..., HEX 6, correponding to Figure 6. You hould declare the 7-bit port HEX : OUT STD_LOGIC_VECTOR( TO 6); in your VHDL code o that the nae of thee output atch the correponding nae in your board uer anual and pin aignent file. 3. After aking the required pin aignent, copile the project.. Download the copiled circuit into the FPGA chip. Tet the functionality of the circuit by toggling the SW witche and oberving the 7-egent diplay. Part V Conider the circuit hown in Figure 7. It ue a two-bit wide 3-to- ultiplexer to enable the election of three character that are diplayed on a 7-egent diplay. Uing the 7-egent decoder fro Part IV thi circuit can diplay the character d, E, blank and,, or depending on your DE-erie board. The character code are et according to Table 3 by uing the witche SW 5, and a pecific character i elected for diplay by etting the witche SW 9 8. An outline of the Verilog code that repreent thi circuit i provided in Figure 8. Note that we have ued the circuit fro Part III and IV a ubcircuit in thi code. You are to extend the code in Figure 8 o that it ue three 7-egent diplay rather than jut one. You will need to ue three intance of each of the ubcircuit. The purpoe of your circuit i to diplay any word on the three 7-egent diplay that i copoed of the character in Table 3, and be able to rotate thi word in a circular fahion acro the diplay when the witche SW 9 8 are toggled. A an exaple, if the diplayed word i de, then your circuit hould produce the output pattern illutrated in Table. SW 9 SW 8 SW 5 SW 3 SW 7-egent decoder Figure 7: A circuit that can elect and diplay one of three character. SW 9 8 Character d E E d d E Table : Rotating the word de on three diplay. 6

7 LIBRARY ieee; USE ieee.td_logic_6.all; ENTITY part5 IS PORT ( SW : IN STD_LOGIC_VECTOR(9 DOWNTO ); LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO )); HEX : OUT STD_LOGIC_VECTOR( TO 6) ); END part5; ARCHITECTURE Behavior OF part5 IS COMPONENT ux_bit_3to PORT ( S, U, V, W : IN STD_LOGIC_VECTOR( DOWNTO ); M : OUT STD_LOGIC_VECTOR( DOWNTO )); END COMPONENT; COMPONENT char_7eg PORT ( C : IN STD_LOGIC_VECTOR( DOWNTO ); Diplay : OUT STD_LOGIC_VECTOR( TO 6)); END COMPONENT; SIGNAL M : STD_LOGIC_VECTOR( DOWNTO ); BEGIN U: ux_bit_3to PORT MAP (SW(9 DOWNTO 8), SW(5 DOWNTO ), SW(3 DOWNTO ), SW( DOWNTO ), M); H: char_7eg PORT MAP (M, HEX);... END Behavior; LIBRARY ieee; USE ieee.td_logic_6.all; - - ipleent a -bit wide 3-to- ultiplexer ENTITY ux_bit_3to IS PORT ( S, U, V, W : IN STD_LOGIC_VECTOR( DOWNTO ); M : OUT STD_LOGIC_VECTOR( DOWNTO )); END ux_bit_3to; ARCHITECTURE Behavior OF ux_bit_3to IS... code not hown END Behavior; LIBRARY ieee; USE ieee.td_logic_6.all; ENTITY char_7eg IS PORT ( C : IN STD_LOGIC_VECTOR( DOWNTO ); Diplay : OUT STD_LOGIC_VECTOR( TO 6)); END char_7eg; ARCHITECTURE Behavior OF char_7eg IS... code not hown END Behavior; Figure 8: VHDL code for the circuit in Figure 7 7

8 Perfor the following tep.. Create a new Quartu II project for your circuit.. Include your VHDL entity in the Quartu II project. Connect the witche SW 9 8 to the elect input of each of the three intance of the two-bit wide 3-to- ultiplexer. Alo connect SW 5 to each intance of the ultiplexer a required to produce the pattern of character hown in Table. Connect the SW witche to the red light LEDR, and connect the output of the three ultiplexer to the 7-egent diplay HEX, HEX, and HEX. 3. Include the required pin aignent for your DE-erie board for all witche, LED, and 7-egent diplay. Copile the project.. Download the copiled circuit into the FPGA chip. Tet the functionality of the circuit by etting the proper character code on the witche SW 5 and then toggling SW 9 8 to oberve the rotation of the character. Part VI Extend your deign fro Part V o that i ue all 7-egent diplay on your DE-erie board. board. Your circuit need to diplay a three letter word on three diplay while the ret of the diplay how a blank. The letter in the word are elected by three two-bit input a hown in Table 3. Alo ipleent rotation of thi word fro right-to-left a hown in Table 5 and Table 6. To do thi, you will need to connect two-bit wide 6-to- ultiplexer to each of ix 7-egent diplay decoder for the DE-CV and DE-SoC. For the DE-5, you will need to connect two-bit wide 8-to- ultiplexer to each of the eight 7-egent diplay decoder. You will need to ue three elect line for each of the ultiplexer: connect the elect line to witche SW 9 7. SW 9 7 Character pattern d E d E d E d E E d d E Table 5: Rotating the word de on ix diplay. SW 9 7 Perfor the following tep: Character pattern d E d E d E d E d E d E E d d E Table 6: Rotating the word de on eight diplay.. Create a new Quartu II project for your circuit.. Include your VHDL entity in the Quartu II project. Connect the witche SW 9 7 to the elect input of each intance of the ultiplexer in your circuit. Alo connect SW 5 to each intance of the ultiplexer a required to produce the pattern of character hown in Table 5 or Table 6 depending on your DE-erie 8

9 board. (Hint: for oe input of the ultiplexer you will want to elect the blank character.) Connect the output of your ultiplexer to the 7-egent diplay HEX5,..., HEX of the DE-CV and DE-SoC or HEX7,..., HEX for the DE Include the required pin aignent for your DE-erie board for all witche, LED, and 7-egent diplay. Copile the project.. Download the copiled circuit into the FPGA chip. Tet the functionality of the circuit by etting the proper character code on the witche SW 5 and then toggling SW 9 7 to oberve the rotation of the character. Copyright c 5 Altera Corporation. 9