EELE 262 Logic Circuits Lab Lab #7 Combinational Logic Design with VHDL (7-Segment Display Decoder)

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1 Lab #7 Combinational Logic Design with VHDL (7-Segment Display Decoder) Objective The objective of this lab is to learn how to implement combinational logic using VHDL and implement the circuitry on an FPGA. This lab will also cover interfacing between an FPGA platform and a breadboard. Outcomes After completing this lab you should be able to: Create a combinational logic design in VHDL and use the Altera Quartus II design environment to create an FPGA design using the modern digital design flow (e.g., HDL, synthesis, technology mapping, place and route, pin assignments, bitstream creation). Design a 4-input decoder circuit to drive symbols on a common-anode 7-segment display. Pre-Lab A) Download the data sheet for the Kingbright SA03-11HDB 7-segment display from the course website and put it in your lab notebook. You only need the first 2 pages. B) You will be provided a 7-segment display, 100ohm resistors, jumper wires and pins that will allow you to connect a DE0-nano FPGA platform pins to your breadboard. Place the 7-segment display on your breadboard and wire up the circuitry that will allow the DE0-nano board to drive it. The following figures show the schematic for your breadboard and a picture of how to place the circuitry on your breadboard. You will connect the DE0-nano board to your breadboard once you come to lab. (breadboard schematic for pre-lab) (example breadboard wiring) C) Fill out the following truth table for the 7-segment display. You are going to create a decoder that will take in a 4-bit code from the DIP switches on the DE0-nano board and drive the equivalent HEX character on the 7-segment display on your breadboard. The DIP switches produce a logic 0 when ON. In order to convert this to positive logic, we will place inverters on the FPGA. You can fill out the table based on positive logic coming from the switches (e.g., 0000 = 0, 1111 = F). The 7-segment display is a common anode configuration (see circuit diagram in datasheet). That means that you provide a power supply voltage to the entire display (e.g., the common anode). In order to turn on one of the LED segments, you pull its pin LOW by driving a logic 0 to the individual segment pin. If you drive the segment pin HIGH, it will turn the LED off. In the following truth table, enter the decoder output values considering this commonanode structure (e.g., if you want the LED segment ON, enter a 0, if you want it OFF, enter a 1. The first entry is given for you to get you started.

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3 Lab Work & Demonstration The first part of this lab will consist of walking through a tutorial in order to create an FPGA design that will drive the 4-bit input code from the DIP switches to the LEDs on the DE0-nano board. The design will consists of 4 inverters in order to convert the switches to positive logic. The second part of this lab will be to design the 7-segment display decoder in VHDL, connect the DE0-nano board to your breadboard, and test your design. The following figure shows the block diagram of the circuits you will be using: 1) Creating an FPGA Design for the DE0-nano that drives the Switches to the LEDs through inverters. A) Connect the DE0-nano board located in the lab to your breadboard as in the above pictures. B) Log into the lab computers using your MSU domain account. C) Create a folder for today s lab. If you wish, you can work on the desktop for now and then copy over to your own drive when finished. Name the folder something descriptive such as Lab07_7segment. D) Start the Altera Quartus II design tool - Start All Programs Altera 12.1 Build 177 (Web Edition) Quartus II 12.1 Quartus II 12.1 The following window will appear (it might take a minute). 3

4 E) Create a new project using the Project Wizard File New Project Wizard The following Window will appear (i): Click Next In the next window (ii), browse to the folder you created and choose Select Folder. Enter top as the name of the project and top-level design entity. i ii Click Next The next screen (iii) allows you to add existing VHDL files. We will create a new file later. Click Next In the next window (iv), choose the FPGA device. The DE0-nano board contains a Cyclone IV E, EP4CE22F17C6. Choose the Cyclone IV E as the Device Family and Select the EP4CE22F17C6 as the device. 4

5 iii iv Click Next on the next screen (v) and Finish on the last screen (vi). v vi F) Create a new VHDL design file called top.vhd File New VHDL File OK. A blank text file will appear. We need to first save this as top.vhd File Save As. The file name should default to top.vhd, verify it is named correctly and click Save 5

6 G) Enter the VHDL entity for the system. The entity contains all of the ports for the system. Based on the block diagram provided above, the ports are: Inputs: SW (3 downto 0) This is the 4-bit vector for the DIP switches Outputs: LED (3 downto 0) This is the 4-bit vector for the LEDs (0,1,2,3) on the DE0-nano Segment_a Segment_b Segment_c Segment_d Segment_e Segment_f Segment_g These lines will drive the LED segments of the 7-segment display. They go to the GPIO_0 header on the DE0-nano board. These pins are connected to your breadboard using jumper wires. Type in the following entity definition in your top.vhd file: entity top is port (SW : in BIT_VECTOR (3 downto 0); LED : out BIT_VECTOR (3 downto 0); Segment_a : out BIT; Segment_b : out BIT; Segment_c : out BIT; Segment_d : out BIT; Segment_e : out BIT; Segment_f : out BIT; Segment_g : out BIT); end entity; 6

7 H) Create the VHDL architecture for the system. Enter the architecture for the design. The architecture is where you describe the functionality of the system. Type in the following: architecture top_arch of top is signal SWn : BIT_VECTOR (3 downto 0); begin SWn <= not SW; LED <= SWn; end architecture; In this VHDL, we create an internal signal vector called SWn. This will be the name of the internal vector that holds the inverted values of the DIP switches. We will need an internal signal vector name when we do the 7-segment decoder circuit in part 2. After the begin statement is where we design the functionality of the system. The line SWn <= not SW describes 4 inverters connected between the 4-bits of SW and the 4-bits of SWn. The line LED <= SWn connects the internal nodes to the output ports that are driving the LEDs on the DE0 nano board. At this point, compile your design to make sure there are no syntax errors. You can compile by either using the pull-down menus (Processing Start Compilation) or by double clicking on the Compile Design task in the Flow window on the left side of the Quartus window. If you experience compile errors, fix them and recompile until you are successful. 7

8 I) Assign the pins of the FPGA We now need to tell Quartus where the ports of our entity should be connected to the pins of the FPGA. Launch the Pin Planner tool using the pull-down menus (Assignments Pin Planner). You will see a graphical depiction of the FPGA pins. At the bottom, you will see all of the ports that you defined in your entity. For each port, double click in the Location box and enter the following pin locations: SW[0], PIN_M1 SW[1], PIN_T8 SW[2], PIN_B9 SW[3], PIN_M15 LED[0], PIN_A15 LED[1], PIN_A13 LED[2], PIN_B13 LED[3], PIN_A11 Segment_a, PIN_D3 Segment_b, PIN_C3 Segment_c, PIN_A3 Segment_d, PIN_B4 Segment_e, PIN_B5 Segment_f, PIN_D5 Segment_g, PIN_A6 Once done, close the Pin Planner window (it will save automatically). Now recompile your design. 8

9 J) Program the FPGA We are now going to download our design to the FPGA. Connect the DE0-nano board to the computer using the retractable USB cable. In the Flow window of Quartus, double click on Program Device (Open Programmer). Click the Start button in the programmer window: K) Test your design You should now see the values of the DIP switches being displayed on the LEDS. Verify operation of your design by toggling each of the 4 DIP switches. The 4 LEDs should be lit when the switch is set to ON. You will need to use a toothpick or something similar to change the switch values. TA will check off 9

10 2) Design the 7-segment Display Decoder: A) Enter VHDL to implement the decoder We are going to implement the 7-segment decoder using a selected signal assignment. This is a convenient way to describe large combinational logic circuits. The selected signal assignment is simpler if we first define an internal signal vector that we can make our output assignments to. We will call this internal signal vector DISPLAY. Once done, we will assign the individual bits of DISPLAY to the output pins Segment_a, Segment_b, etc Enter the following signal definition before the begin statement in your top.vhd: signal DISPLAY : BIT_VECTOR (6 downto 0); Now enter the selected signal assignment for the decoder. This will go below your assignments to the LEDs: with (SWn) select DISPLAY <= " " when "0000", " " when "0001", " " when "0010", " " when "0011", " " when "0100", " " when "0101", " " when "0110", " " when "0111", " " when "1000", " " when "1001", " " when "1010", " " when "1011", " " when "1100", " " when "1101", " " when "1110", " " when "1111"; Finally, assign the individual bits of DISPLAY to the output ports to drive the segments: Segment_a <= DISPLAY(6); Segment_b <= DISPLAY(5); Segment_c <= DISPLAY(4); Segment_d <= DISPLAY(3); Segment_e <= DISPLAY(2); Segment_f <= DISPLAY(1); Segment_g <= DISPLAY(0); Your final architecture will look like this: (Note: comments are indicated with - - and will appear green in Quartus.) 10

11 Lab Grading B) Recompile your design. Fix any compile errors you have. C) Download your program to the FPGA. D) Test your design. Verify that each of the 16 HEX codes are successfully displayed for each 4-bit input code on the DIP switches. TA will check off Pre-Lab / 10 Lab Demo (step 1) / 45 Lab Demo (step 2) / 45 Total /