5 MEMORY. Overview. Figure 5-0. Table 5-0. Listing 5-0.

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1 5 MEMORY Figure 5-0. Table 5-0. Listing 5-0. Overview Each DSP core in the ADSP-2192 contains large internal memory. This chapter describes the DSP s memory and how to use it. The two DSP cores also have shared memory and memory mapped registers. For information on using the shared memory, see Dual DSP Cores on page 6-1. There are 140K words of internal memory on the ADSP Within this space, the P0 DSP core has 80K words of SRAM and 4K words of ROM, and the P1 DSP core has 48K words of SRAM and 4K words of ROM. The P0 and P1 DSP cores also have 4K words of shared memory space. The memory is divided into 16K word blocks for access. For more information on these blocks, see ADSP-2192 Memory Map on page 5-8. Most microprocessors use a single address and data bus for memory access. This type of memory architecture is called Von Neumann architecture. But, DSPs require greater data throughput than Von Neumann architecture provides, so many DSPs use memory architectures that have separate buses for program and data transfer. The two buses let the DSP get a data word and an instruction simultaneously. This type of memory architecture is called Harvard architecture. ADSP-219x family DSPs go a step farther by using a modified Harvard architecture. This architecture has program and data buses, but provides a single, unified address space for program and data storage. While the Data Memory (DM) bus only carries data, the Program Memory (PM) bus handles instructions or data, allowing dual-data accesses. ADSP-219x/2192 DSP Hardware Reference 5-1

2 DSP core and I/O processor share accesses to internal memory. Each block of memory can be accessed by the DSP core or I/O processor in every cycle, but the DSP is held off if contending with the I/O processor core for accesses to the same block. A memory access conflict can occur when the DSP core attempts two accesses to the same internal memory block in the same cycle. When this conflict happens, an extra cycle is incurred. The DM bus access completes first and the PM bus access completes in the following (extra) cycle. During a single-cycle, dual-data access, the DSP core uses the independent PM and DM buses to simultaneously access data from two separate memory blocks. Though dual-data accesses provide maximum data throughput, it is important to note some limitations on how programs may use them. The limitations on single-cycle, dual-data accesses are: The two pieces of data must come from different memory blocks. If the core tries to access two words from the same memory block for a single instruction, an extra cycle is needed. For more information on how the buses access these blocks, see Internal Data Bus Exchange on page 5-5. The PM data access execution may not conflict with an instruction fetch operation. If the cache contains the conflicting instruction, the data access completes in a single-cycle and the sequencer uses the cached instruction. If the conflicting instruction is not in the cache, an extra cycle is needed to complete the data access and cache the conflicting instruction. For more information, see Instruction Cache on page 3-9. Efficient memory usage relies on how the program and data are arranged in memory and how the program accesses the data. For more information, see Arranging Data in Memory on page ADSP-219x/2192 DSP Hardware Reference

3 As shown in Figure 5-1, the DSP has three internal buses connected to its internal memory, the Program Memory (PM) bus, Data Memory (DM) bus, and I/O Processor (IO) bus. The PM bus, DM bus, and IO bus share two memory ports; one for each block. Memory accesses from the DSP s core (computational units, data address generators, or program sequencer) use the PM or DM buses, while the I/O processor uses the IO bus for memory accesses. Using the IO bus and cycle-stealing DMA, the I/O processor can provide data transfers between internal memory and the DSP s communication ports (host PCI/USB port or AC 97 port) without hindering the DSP core s access to memory (except for stealing a cycle). There are some bus arbitration issues involved in memory accesses. A DSP core s PM and DM buses can try to access the same block of memory in the same cycle. Also, the DSP cores DM buses can try to access shared memory space in the same cycle. The ADSP-2192 has an arbitration system to handle this conflicting access. Arbitration for accesses to a DSP core s internal memory is fixed at the following priority: (highest priority) I/O processor accesses over the DMA bus, core accesses over the DM bus, and core accesses over the PM bus (lowest priority). Also, I/O processor accesses may not be sequential, so the DSP core s buses are never held off for more than one cycle. Arbitration for accesses to shared memory is fixed with the highest priority for DSP P0 and the lowest priority for DSP P1. Internal Address and Data Buses Each DAG is associated with a particular data bus and memory page. From settings at reset, DAG1 supplies addresses over the DM bus for memory page 0 and DAG2 supplies addresses over the PM bus for memory page 0. These selections can be changed using the DMPGx registers. For more information on address generation, see Program Sequencer on page 3-1 or Data Address Generators on page 4-1. ADSP-219x/2192 DSP Hardware Reference 5-3

4 P0 DSP CORE INTERNAL MEMORY* PAGE 1, BLOCK 0 (0X X13FFF, 24 BIT) ANY TWO PATHS SIMULTANEOUSLY ADDRESSES AND DATA FOLLOW PARALLEL PATHS PAGE 0, BLOCK 3 (0XC000-0XFFFF, 16 BIT) PAGE 0, BLOCK 2 (0X8000-0XBFFF, 16 BIT) PAGE 0, BLOCK 1 (0X4000-0X7FFF, 16 BIT) PAGE 0, BLOCK 0 (0X0000-0X3FFF, 16 BIT) SHARED MEMORY PAGE 2, BLOCK 0 (0X X20FFF, 16 BIT) PAGE 0, BLOCK 1 (0X4000-0X7FFF, 16 BIT) ADDR ADDR DATA DATA ADDR DATA SHARED MEMORY ARBITRATION PM ADDRESS BUS PM DATA BUS 8 PX REGISTER DM ADDRESS BUS DMA ADDRESS DMA DATA DM DATA BUS I/O REGISTERS ARBITRATION DMA DATA DMA ADDRESS DSP P0 DMA CONTROLLER IO ADDR IO DATA DSP P1 DMA CONTROLLER I/O REGISTERS *NOTE: EACH MEMORY BLOCK HAS A SEPARATE CONNECTION TO THE PM AND DM BUSES. Figure 5-1. ADSP-2192 Memory & Internal Buses Block Diagram 5-4 ADSP-219x/2192 DSP Hardware Reference

5 Because the DSP s blocks of internal memory have different widths, placing 16-bit data in a Program Memory block leaves some space unused. For more information on how the DSP works with memory words, see P0 DSP Core Internal Memory Space on page The PM data bus is 24 bits wide, and the DM data bus is 16 bits wide. Both data buses can handle data words (16-bit), but only the PM data bus carries instruction words (24-bit). Internal Data Bus Exchange The data buses let programs transfer the contents of one register to another or to any internal memory location in a single cycle. As shown in Figure 5-1, the PM Bus Exchange (PX) register permits data to flow between the PM and DM data buses. The PX register holds the lower 8 bits during transfers between the PM and DM buses. The alignment of PX register to the buses appears in Figure PM Data Bus (24-bit) (upper 16 bits) PX Register 0 (lower 8 bits) 15 DM Data Bus (16-bit) 0 Figure 5-2. PM Bus Exchange (PX) Registers ADSP-219x/2192 DSP Hardware Reference 5-5

6 The PX register is a Register Group 3 (REG3) registers and is accessible for register-to-register transfers. When reading data from program memory and data memory simultaneously, there is a dedicated path from the upper 16 bits of the PM data bus to the Y registers of the computational units. This read-only path does not use the bus exchange circuit. For transferring data from the PM data bus, the PX register is: 1. Loaded automatically whenever data (not an instruction) is read from program memory to any register. For example: AX0 = PM(I4,M4); In this example, the upper 16 bits of a 24-bit program memory word are loaded into AX0 and the lower 8 bits are automatically loaded into PX. 2. Read out automatically as the lower 8 bits when data is written to program memory. For example: PM(I4,M4) = AX0; In this example, the 16 bits of AX0 are stored into the upper 16 bits of a 24-bit program memory word. The 8 bits of PX are automatically stored to the 8 lower bits of the memory word. 5-6 ADSP-219x/2192 DSP Hardware Reference

7 For transferring data from the DM data bus, the PX register may be: 1. Loaded with a data move instruction, explicitly specifying the PX register as the destination. The lower 8 bits of the data value are used and the upper 8 are discarded. PX = AX0; 2. Read with a data move instruction, explicitly specifying the PX register as a source. The upper 8 bits of the value read from the register are all zeroes. AX0 = PX; Whenever any register is written out to program memory, the source register supplies the upper 16 bits. The contents of the PX register are added as the lower 8 bits for instructions (such as the Type-1 and Type-32) that use the PX register, but the PX register is not used for other instructions (such as the Type-4, Type-12, and Type-29). If these lower 8 bits of data to be transferred to program memory (through the PM data bus) are important, and any instructions will be using the PX register, you should load the PX register from DM data bus before the program memory write operation. ADSP-219x/2192 DSP Hardware Reference 5-7

8 ADSP-2192 Memory Map The ADSP-2192 s memory map appears in Figure 5-3. This memory has multiple memory spaces: internal memory space, shared memory space, system control registers, and shared DSP I/O mapped registers. '633 0(025<0$3 $''5(66 '633 0(025<0$3 $''5(66 3$*( 6+$5('5$0. ))) )))) 6$0( 3$*( 6+$5('5$0. ))) )))) 5(6(59(' 5(6(59(' 3$*( 352*5$ *5$05$0. ))) ))) 3$*( 352*5$ *5$05$0. ))) ))) 3$*( '$7$5$0 %/2&.. '$7$5$0 %/2&.. '$7$5$0 %/2&.. '$7$5$0 %/2&.. )))) & %))) ))) ))) 6+$5(' '63,2 0$33(' 5(*,67(56 3$*(6 $''5(66 )))) 3$*( 5(6(59(' '$7$5$0 %/2&.. '$7$5$0 %/2&.. )))) ))) ))) Figure 5-3. ADSP-2192 Memory Map 5-8 ADSP-219x/2192 DSP Hardware Reference

9 These memory spaces have the following definitions: Internal memory space. The internal RAM space ranges from address 0x through 0x01 3FFF on the P0 DSP and 0x through 0x00 7FFF plus 0x through 0x01 3FFF on the P1 DSP. The internal (boot kernel) ROM space ranges from address 0x through 0x01 4FFF on both DSP cores. Internal memory space refers to the DSP s on-chip SRAM and boot kernel ROM. Shared memory space. This space ranges from address 0x through 0x02 0FFF on both DSP cores. Shared memory space refers to on-chip memory that is accessed through data move instructions and permits communications between the two cores. Accesses to shared memory space are arbitrated, with the highest priority for DSP P0 and the lowest priority for DSP P1. System control registers. This space is separate from other memory spaces and has 256 locations. (This space does not appear in Figure 5-3.) Each DSP core has its own system control register space. These locations are reserved for core-based controls and are accessed through system control register read/write instructions (REG()). Shared I/O memory mapped registers. This space is separate from other memory spaces and has an address range from address 0x00 00 through 0xFF FF. The DSP cores share access to the I/O registers. The I/O registers setup and control memory mapped peripherals. These registers are accessed through I/O port read/write instructions (IO()). Access to I/O memory mapped registers is arbitrated. The priorities (from highest to lowest) are as follows: DSP P0, DSP P1, PCI interface, USB interface. ADSP-219x/2192 DSP Hardware Reference 5-9

10 P0 DSP Core Internal Memory Space The P0 DSP s internal memory space contains four 16K word blocks of Data Memory on Page 0 and one 16K word block of Program Memory on Page 1 on the DSP s memory map. The memory map has a unified, continuous address range. Some features of the DSP s architecture lead to block and page distinctions within the map. These distinctions include: Internal memory block width. Blocks 0, 1, 2, and 3 reside on Page 0, are 16 bits wide, and can contain data only. The block on Page 1 (Program Memory) is 24 bits wide and can contain instructions or data. Internal bus width. The PM data bus is 24 bits wide, and the DM data bus is 16 bits wide. While either bus can access any internal memory block for data, only the PM bus can fetch instructions. The PM address bus and DM address bus are each 24 bits wide. Data Address Generators. For Type-1 instructions, DAG1 generates addresses for DM bus, and DAG2 generates addresses for the PM bus; however, for most instructions, both DAGs can access either bus. At reset, the DAGs generate addresses for Page 0; the page selections are configurable with the DMPGx registers. Page size. Architectural features (which are described in Program Sequencer on page 3-1 and Data Address Generators on page 4-1) lead to 64K word page segmentation of memory a 16-bit address range per page. To move beyond a page range requires changing a value in a page register. These registers hold the upper 8 bits of the 24-bit address. There are page registers associated with I/O memory space ADSP-219x/2192 DSP Hardware Reference

11 To execute programs and use data in internal memory, the ADSP-2192 operates very similarly to previous ADSP-218x DSPs. For most internal memory operations, paging is not required, and the page registers remain at their reset values (Page 0). The DSP s memory architecture permits either bus to access either internal memory block and also permits dual accesses a single cycle operation where each bus accesses a block of memory. To arbitrate simultaneous access, the memory interface: Processes a memory read before memory write Processes a DM bus access before a PM bus access Also on-chip, the DSP has an internal boot kernel ROM in the upper part of Page 1. Programs should treat this area as reserved and should not access this area at runtime. P1 DSP Core Internal Memory Space The P1 DSP s internal memory space is identical to the P0 except that it contains two 16K word blocks of Data Memory on Page 0 and contains one 16K word block of Program Memory on Page 1 on the DSP s memory map. Shared Memory The ADSP-2192 s shared memory space contains one 4K word block of memory. Because this memory is outside of each DSP core and because access is arbitrated between the two cores, access to shared memory has core stall and latency issues. Some points on these issues include: Every access to shared memory incurs at least one cycle of stall (to perform synchronization), therefore minimum latency is 2 cycles. Arbitrated access leads to stalls for the loser of the arbitration. ADSP-219x/2192 DSP Hardware Reference 5-11

12 When accessing shared memory, a DSP locks out the other DSP for several cycles. A DSP can completely lock out the other DSP from shared memory by performing back to back or nearly back to back cycles to shared memory. Once a particular DSP owns the shared memory, it takes two cycles of inactivity to shared memory from that DSP to relinquish the interface. If, for example, both DSP's are accessing the shared memory with the following code loop: ar = dm(shared_memory); nop; nop; /* REPEAT */ Each DSP gets a single shared access every 6 cycles. The best way to get good bandwidth from shared memory is to do bursts of accesses. Each access after the first takes 2 cycles, which is the maximum throughput. Host (PCI/USB) and DSP Internal Memory Space PCI and USB hosts can access both DSP cores internal memory. These accesses occur as DMA processes and are executed by the DSP core s DMA controller. To a host, a DSP core s memory appears as a memory peripheral and is accessible through a set of addresses. For more information, see Host Memory Maps in Host (PCI/USB) Port on page ADSP-219x/2192 DSP Hardware Reference

13 System Control Registers Each DSP core has a separate memory space for system control registers. These registers support parts of the core (for example, DAGs and program sequencer) for controls. For information on using system control registers, see ADSP-219x DSP Core Registers on page A-1. To access system control registers, programs use the system control register read/write instructions (REG()). Shared I/O Memory Mapped Registers The DSP cores share I/O memory spaces for I/O memory mapped registers. Similar to internal memory, the addressing for I/O memory is divided into pages. Programs select a page with the IOPG registers. The I/O registers control and contain status information from DSP peripherals (Host port or AC 97 port) and peripheral DMA. Arranging Data in Memory Each DSP core s memory is divided into 16K word blocks of program and data memory. Although the memory map is unified (either bus can access any address), programs can achieve efficient operation only by minimizing data access conflicts. The following guidelines provide an overview of how programs should interleave data in memory locations. For more information and examples, see the ADSP-219x DSP Instruction Set Reference: If two pieces of data are needed simultaneously (a dual-read), put them in different memory blocks and uses the DM bus to fetch one and the PM bus to fetch the other. If instruction and data fetch combinations repeatedly cause cached conflicts (repeatedly empty and fill cache), re-order the instruction to minimize these conflicts. For more information, see Instruction Cache on page 3-9. ADSP-219x/2192 DSP Hardware Reference 5-13

14 Data Move Instruction Summary Table 5-1 lists the data move instructions. For more information on assembly language syntax, see the ADSP-219x DSP Instruction Set Reference. In Table 5-1, note the meaning of the following symbols: Dreg, Dreg1, Dreg2 indicate any register file location (Register Group) Reg1, Reg2, Reg3, or Reg indicate Register Group 1, 2, 3 or any register. Ia and Mb indicate DAG1 I and M registers. Ic and Md indicate DAG2 I and M registers. Ireg and Mreg indicate I and M registers in either DAG. Imm# and Data# indicate immediate values or data of the # of bits. Table 5-1. Data/Register Move Instruction Summary Instruction Reg = Reg; DM(<Addr16>) = Dreg, Ireg, Mreg ; Dreg, Ireg, Mreg = DM(<Addr16>); <Dreg>, <Reg1>, <Reg2> = <Data16>; Reg3 = <Data12>; IO(<Addr10>) = Dreg; Dreg = IO (<Addr10>); REG(<Addr8>) = Dreg; Dreg = REG(<Addr8>); 5-14 ADSP-219x/2192 DSP Hardware Reference