Hardware Implementation of XTEA
|
|
- Alexander Underwood
- 7 years ago
- Views:
Transcription
1 HI-1 1 Hardware Implementation of XTEA Steven M. Aumack, Michael D. Koontz Jr. Abstract Some very important factors to consider when designing a cryptographic system are performance, speed, size, and security. Sometimes the designer of the cryptosystem decides to prioritize these factors based on specific objectives of the cryptosystem. Tiny Encryption Algorithm (TEA), and the Extension of TEA (XTEA) are examples of cryptographic algorithms that were designed with size and simplicity as the main design criteria. Since TEA s presentation to the public in 1994 and XTEA s presentation in 1997, many software implementations have been designed of both algorithms. However, not nearly as many hardware designs of TEA have been implemented. This report details a hardware implementation of XTEA (Extension of TEA), with a design goal with speed as the main priority as opposed to size. Index Terms Cryptography, TEA (Tiny Encryption Algorithm), XTEA (Extension of Tiny Encryption Algorithm) T I. INTRODUCTION HE Tiny Encryption Algorithm, or TEA, is a block cipher which was originally designed by David Wheeler and Roger Needham of the Cambridge Computer Laboratory. It was first presented at the Fast Software Encryption Workshop in TEA was designed with the idea that a cryptographic algorithm could be implemented with smaller code size and less complexity, and still execute with similar or better performance measurements than other popular cryptographic algorithms such as DES [1]. decryption of the TEA block cipher is to ensure a higher level of security. This is related to the avalanche effect, which states that in order to provide a secure cryptosystem, when one bit of input is changed, then about half of the output bits should change. In the case of TEA, the number of cycles that must occur before changing one input bit effects 32 output bits (half of the 64-bit block) is roughly six cycles. The designers of TEA claim that sixteen cycles should be good enough, but recommend 32 cycles for enough permutation of the output [2]. Since TEA uses a Feistel structure, it uses addition, subtraction, and XOR as reversible operations. The use of addition, subtraction, and XOR operations helps eliminate the need to implement Substitution boxes (S-Box) and Permutation boxes (P-Box) as a part of the design [3]. For security reasons the key length is set to 128 bits to help prevent simple search techniques or persuade attackers against brute force attacks. The key used for TEA is also sometimes called the master key. This is because in the implementation discussed in the original presentation, the master key is subdivided into other derived keys, K[0 3]. The key scheduling method used in TEA is also a simple design. For odd cycles, subkey K[0] and K[1] are used, and for even cycles, subkey K[2] and K[3] are used. Each cycle takes into consideration a variable called delta and is used as a part of the key scheduling. A different value for delta is used in each cycle of TEA. The number delta is derived from the following equation: II. TINY ENCRYPTION ALGORITHM (TEA) A. Background Information As discussed above, TEA is a block cipher. A block cipher takes a specific input size of plaintext, and the cryptographic algorithm produces a corresponding ciphertext of identical size. For TEA, the block size is defined as 64 bits. TEA uses a Feistel structure. Cryptographic algorithms that use a Feistel structure have similar operations for encryption or decryption. For example, the decryption algorithms may require only a reversal of the encryption algorithm or the key schedule. Cryptographic algorithms that use a Feistel structure also use operations such as bit shuffling or linear mixing to help produce an output that is very different from the input. These operations may be repeated for several rounds for increased security. For TEA, the suggested number of rounds is 64. The rounds are implemented in pairs, which results in 32 cycles for one block of plaintext. The fact that there are 32 cycles for encryption or The equation above for delta yields the following rounded number, This number in hexadecimal format is 0x9E3779B9. The following diagram shows encryption for the TEA algorithm. As previously stated, the only operations performed during encryption include addition, XOR, and shift right or shift left. The diagram shows two rounds or one pair/cycle for TEA. The Feistel structure for TEA, and the 4 subkeys used for encryption are also easily seen.
2 HI-1 2 K[0] K[1] K[2] >> 5 void code(long* v, long* k) unsigned long y=v[0],z=v[1], sum=0, /* set up */ delta=0x9e3779b9, /* a key schedule constant */ n=32 ; while (n-->0) /* basic cycle start */ sum = delta ; y = ((z<<4)k[0]) ^ (zsum) ^ ((z>>5)k[1]) ; z = ((y<<4)k[2]) ^ (ysum) ^ ((y>>5)k[3]) ; /* end cycle */ v[0]=y ; v[1]=z ; void decode(long* v,long* k) unsigned long n=32, sum, y=v[0], z=v[1],delta=0x9e3779b9 ; sum=delta<<5 ; >> 5 K[3] Figure 1 - TEA Block Diagram while (n-->0) /* start cycle */ z-= ((y<<4)k[2]) ^ (ysum) ^ ((y>>5)k[3]) ; y-= ((z<<4)k[0]) ^ (zsum) ^ ((z>>5)k[1]) ; sum-=delta ; /* end cycle */ v[0]=y ; v[1]=z ; B. Software Implementation In the original presentation of TEA, David Wheeler and Roger Needham also included some source code for software implementation. The designer s state that the particular algorithm used in the source code for the software implementation of TEA was chosen because it was thought to be a compromise between security and simplicity of design. This algorithm was neither the fastest nor the slowest of those tested prior to the final down selection to one algorithm [2]. As a part of the original presentation of TEA, Wheeler and Needham published the following source code. In the software implementation, the source code separates the 64-bit block into two 32-bit numbers labeled y and z. As previously stated, TEA contains two rounds for one cycle of encryption or decryption. Round one (and subsequent odd rounds) operates on y, and subkeys K[0] and K[1]. Round two (and subsequent even rounds) operates on z, and K[2] and K[3]. Figure 2 - TEA Source Code [2] III. EXTENSIONS OF TINY ENCRYPTION ALGORITHM (XTEA) A. Background Information After some weaknesses and vulnerabilities of TEA were discovered and documented, Wheeler and Needham decided to present a new implementation of TEA and called it Extensions of TEA (XTEA). XTEA was first presented in 1997, three years after TEA was first presented. Similar to TEA, XTEA is also a block cipher, which uses Feistel structure. XTEA also uses the same 64-bit block and a 128-bit key as TEA. The same 64 rounds, or 32 cycles, are also recommended for the algorithm. The vulnerabilities of TEA were discovered using differential related-key attacks [4]. Therefore, XTEA attempts to correct the weaknesses by improving some aspects of the algorithm. The first change that was introduced in XTEA was a correction to the key schedule algorithm. In the updated XTEA, the introduction of subkeys is added more slowly. Also, the subkeys are selected by using two bits of the variable sum. In addition, a shift of 11 is also introduced in the key schedule to help create an irregular sequence of the subkeys. Some other changes introduced in XTEA is a rearrangement of the addition, shifts, and XOR operations. The following diagram shows XTEA. Instead of defined placement of the subkeys, now subkeys are introduced as subkey A and subkey B.
3 HI-1 3 Subkey A >> 5 IV. HARDWARE IMPLEMENTATION OF XTEA A. Top Level Block Diagram During the hardware design process, our project team needed to determine the design criteria for implementation. Our final decision was to implement a hardware design with speed as the main criteria. Therefore, encryption and decryption could be designed separately. The following diagram is a top-level design of the hardware. DATA IN 64 bit KEY 128 bit ENC_DEC LOAD_DATA LOAD_KEY Subkey B >> 5 RESET CLOCK XTEA Figure 3 - XTEA Block Diagram OUTPUT 64 bit READY Figure 5 - Hardware Implementation Top Level Diagram B. Software Implementation Similar to the publication for TEA, when XTEA was published in 1997, Wheeler and Needham also included source code for XTEA. As previously stated, XTEA contains two rounds for one cycle of encryption or decryption. Round one (and subsequent odd rounds) operates on y. The subkey selection in this round depends on the value of sum&3, which is the variable sum logic AND with 3, 0x03h, or 0011b. Round two (and subsequent even rounds) operates on z. The subkey selection in this round depends on the value of sum>>11 & 3, which is SUM shifted by 11 and then a logic AND with 3, 0x03h, or 0011b. tean( long * v, long * k, long N) unsigned long y=v[0], z=v[1], DELTA=0x9e3779b9 ; if (N>0) /* coding */ unsigned long limit=delta*n, sum=0 ; while (sum!=limit) y= ( (z<<4) ^ (z>>5) ) z) ^ (sum k[sum&3] ); sum=delta; z= ( (y<<4) ^ (y>>5) y) ^ (sum k[sum>>11 &3] ); else /* decoding */ unsigned long sum=delta*(-n) ; while (sum) z-= ( (y<<4) ^ (y>>5) y) ^ (sum k[sum>>11 &3] ); sum-=delta; y-= ( (z<<4) ^ (z>>5) z) ^ (sum k[sum&3] ); v[0]=y, v[1]=z ; return ; Figure 4 - XTEA Source Code [5] The definitions of the pins used for the hardware implementation are as follows. RESET: resets the circuit to an initial state CLOCK: input clock signal (active high) DATA_IN: 64-bit data input to circuit (can be plaintext or ciphertext). Also the upper 32-bits are used to input the keyschedule constant KEY: 128-bit key input ENC_DEC: controls circuit operating mode (encryption or decryption) LOAD_DATA: initiates loading of data into the circuit LOAD_KEY: initiates loading of the key and keyschedule constant into the circuit OUTPUT: 64-bit data output (encrypted ciphertext or decrypted plain-text) READY: signals that the circuit is ready to accept input B. Hardware Design Decisions As previously stated, the criteria for the XTEA hardware implementation is to maximize speed. Therefore, we needed to make a few critical design decisions. The first decision we made is to implement encryption and decryption algorithms as separate logic. If our design criteria were to minimize area, we most likely would have used the same adders, XOR s, and other logic for encryption and decryption. Except, in decryption the data flows through the circuit in reverse order. The second design decision is to determine how to implement a major building block for the logic. For XTEA, a major component of both encryption and decryption, besides the XOR gate is an adder. The default adder that is implemented using the design tools we chose is a ripple carry adder. For the hardware design of XTEA, we chose to implement a faster adder. The adder we decided to
4 HI-1 4 implement is a Kogge-Stone parallel prefix adder. following diagram shows a 16-bit Kogge-Stone adder. The equation: y= (z<<4 ^ z>>5) z ^ sum k[sum&3]; This output is the final result for the second step. See the block diagram below for more details about the first two steps. Y(V0) Z(V1) Sum >> 5 SubKey sum = sum delta sum k[sum & 3] (z<<4 ^ z>>5) z PL_1 PL_1 PL_1 y ( (z<<4 ^ z>>5) z) ^ (sum k[sum & 3] ) Figure 6 - Kogge Stone Adder Block Diagram The third design decision is to determine the flow of logic for the encryption and decryption routines. We decided to implement XTEA using registers. After each calculation at the end of a step, the current value is stored in a register. Each step that ends with a value getting stored in a register takes one clock period to complete. There are four steps that occur for every cycle of encryption or decryption. Therefore, if four steps are required, and each step takes one clock period to complete, both encryption and decryption algorithms take four clock periods to complete one cycle. For 32 total cycles, the total number of clock periods to encrypt or decrypt one 64-bit block takes 128 (32*4) clock periods. There are two additional clock periods during the encryption and decryption algorithms. One clock period at the beginning is required for reading input values for data, the key scheduling constant delta and the intermediate sum, and one more clock period at the end for writing the data output back to the main registers for a grand total of 130 clock cycles. C. Encryption and Decryption Algorithms During the detailed design stage of hardware implementation, we used the software source code to create a block diagram of the XTEA encryption and decryption algorithms. The first two lines of source code that is included in the while loop are: Figure 7 - Hardware Implementation Encryption Part II After this step, the value of sum is updated, and the new value of y is used for the third and fourth step of encryption. The final line of source code inside the while loop is: z= (y<<4 ^ y>>5) y ^ sum k[sum>>11 &3]; The output of the third step yields: (y<<4 ^ y>>5) y sum k[sum>>11 &3] These two values are XOR d together and added with the value of z, which results in the final equation: z= (y<<4 ^ y>>5) y ^ sum k[sum>>11 &3]; This final result for z is the output of the fourth step. The new values of sum, y, and z are used in the next iteration of the loop until all 32 cycles are complete for encryption. PL_2 SubKey sum k[sum>>11 & 3] Z(V1) PL_2 >> 5 (y<<4 ^ y>>5) y y= (z<<4 ^ z>>5) z ^ sum k[sum&3]; sum=delta; The output of the first step yields the following three expressions: (z<<4 ^ z>>5) z sum k[sum&3] sum=delta The first two lines of code above are XOR d together and added with the value of y, which results in the final New sum New y z ( (y<<4 ^ y>>5) y) ^ (sum k[sum>>11 & 3] ) Figure 8 - Hardware Implementation Encryption Part I
5 HI-1 5 The block diagram for decryption looks similar. However there are subtle differences. Instead of adders in some equations, subtraction is used as a reverse operation. In order to implement subtraction in hardware, we used an adder with one input inverted and input a 1 on the carry line. Also, the value of delta is slightly different. As opposed to using the value of delta shown in equation (1) used for encryption, the initial value of delta for decryption is multiplied by 32. For each subsequent cycle for decryption sum is subtracted from delta to get the new value of sum. Again, this is a reverse operation from addition where sum added with delta resulted in a next value for sum for encryption. Reset rst_sum ready rst_count load_key? 0 1 S1 The three lines of source code in the while loop for decryption are: z-= (y<<4 ^ y>>5) y ^ sum k[sum>>11 &3]; sum-=delta; y-= (z<<4 ^ z>>5) z ^ sum k[sum&3] ; The first step of decryption yields the following expressions: (y<<4 ^ y>>5) y sum k[sum>>11 &3] sum-=delta The first two lines of code above are XOR d together and added with the value of z, which results in the final equation: z-= (y<<4 ^ y>>5) y ^ sum k[sum>>11 &3]; 0 load_data? 1 S2 S3 enc_l1 en_data enc_data? 0 1 load_sum This result is the second step for decryption. After this step, the value of sum is updated, and the new value of z is used for the third and fourth step of encryption. The final line of source code inside the while loop is: S4 enc_l2 y-= (z<<4 ^ z>>5) z ^ sum k[sum&3] enc_l3 The output of the third step yields: (z<<4 ^ z>>5) z sum k[sum>>11 &3] These two values are XOR d together and added with the value of y, which results in the final equation: S5 en_data en_sum z= (y<<4 ^ y>>5) y ^ sum k[sum>>11 &3]; This final result for z is the output of the fourth step. The new values of sum, y, and z are used in the next iteration of the loop until all 32 cycles are complete for decryption. D. State Diagram For the purposes of the hardware design, we implemented a state diagram to help with logic control of the encryption and decryption algorithms. See the figure to see the flow of the state diagram. done? S6 en_out Figure 9 - Hardware Implementation Flow Diagram The first action in the state diagram is to assert the reset line to initiate the circuit. After the reset signal is asserted,
6 HI-1 6 the values of rst_sum, ready, and rst_count are asserted. The rst_sum signal resets the initial value of sum to zero for encryption and 32*delta for decryption. The rst_count signal resets the encryption/decryption cycle counter. The first decision in the state diagram is whether or not to load the key. If the value of load_key is not asserted, the state diagram continues to the next decision. If load_key is asserted, the key for encryption or decryption and the key schedule constant is loaded. The next decision is whether or not to load the data. If the load_data signal is not asserted, the state diagram loops until the load_data signal is asserted. Once the load_data signal is asserted, the en_data signal is asserted and the input is loaded. At this point, the next decision is whether to encrypt or decrypt the data. If the enc_data signal is not asserted, then the data input will be encrypted. If the enc_data signal is asserted, then the data input will be decrypted. Prior to decrypting the data, the value of sum is loaded, which is decremented after every cycle for decryption. After this step is complete, four clock periods for one complete cycle of encryption or decryption completes. In order to continue on to the next clock cycle, a signal needs to be asserted. For example, the signal enc_l1 needs to be asserted before continuing on to the next clock cycle, and then signal enc_l2 needs to be asserted before continuing on to the next clock cycle. This allows the intermediate values to flow through the pipeline registers. After the four clock cycles complete, another decision needs to be made. We need to determine if the 32 cycles have completed. If 32 cycles have not been completed, the done signal is not asserted and the state diagram loops back to the beginning of the pipeline. If the done signal is asserted, then all 32 cycles have been completed. After all 32 cycles have been completed, the en_out signal is asserted. When the en_out signal is asserted, the tri-state buffers are enabled and the new data is available at the output of the circuit. V. RESULTS After the hardware implementation of our hardware design of XTEA was completed, we recorded some data including area, clock frequency, latency, and throughput. First, as a part of the results, we need to discuss the target chipsets that were used to gather timing analysis. For FPGA implementation, the Xilinx Virtex 4SX25FF668 was chosen. This FPGA was chosen primarily because of its size. For ASIC implementation, 90 nm TCBN90G with the TSMC Library was chosen. This semi-custom library was chosen because it was the library with the smallest transistors available to us (90nm instead of 120nm). Data was recorded for the FPGA hardware implementation. Some of the data recorded includes area (slice flip-flops and look-up-tables (LUTs) as well as equivalent gate count). Data related to clock period and frequency was also recorded. The information listed in the following table was recorded using Active-HDL ver 7.1 Table 1 - FPGA Results Device FPGA Area (Slice Flip-Flops) 1,081 Area (LUTs) 4,608 Area (Equivalent Gate Count including JTAG gate count for IOBs) / = 20,411 NAND Gate Equivalent Clock Period (ns) Clock Frequency (MHz) Similar data was recorded for the ASIC hardware implementation. The data recorded for the ASIC design includes area, clock period, and clock frequency. The information listed in the following table was recorded using Synopsys Design Analyzer Version X Table 2 - ASIC Results Device ASIC Area 49, Clock Period (ns) 1.5 Clock Frequency (MHz) After recording data related to clock frequency, we also recorded data related to latency of the design. After recording data for latency, and knowing that XTEA uses 64-bit blocks, we calculated the throughput in Mbps for both the FPGA and ASIC design. The following table contains latency, which was recorded using Active-HDL ver 7.1, and throughput which was calculated. Table 3 - Throughput for FPGA and ASIC Device Latency (ns) Throughput (Mbps) FPGA ASIC Throughput was calculated in the following manner. The XTEA block size of 64 bits was divided by the latency. The value obtained is throughput in bits per second (bps). This value was divided by 1024 to get Kilobits per second (kbps), and divided by 1024 again to get Megabits per second (Mbps). There is a noticeable latency difference between the FPGA and ASIC design implementation. The ASIC is a little more than four times faster than the FPGA. VI. CONCLUSION This paper provides enough data to show that XTEA can be implemented using hardware, either an FPGA or ASIC. The clock frequency was fast, and the throughput was also was high. This particular hardware implementation of XTEA was derived from the published source code of the original designers of TEA and XTEA. From this source code, a block
7 HI-1 7 diagram and state diagram were produced to help complete the hardware implementation with successful results. The work provided in this paper is important because there are not many hardware implementations of TEA or XTEA available to the public. If an end user is interested in using this hardware design and implementation for their application, the end user should determine if the security of XTEA meets their requirements and is sufficient for their application. The end user should compare the speed and throughput of this hardware implementation with other secret key block cipher cryptosystems to determine which algorithm will meet their speed and data requirements. The end user should also compare this hardware implementation of XTEA with other hardware implementations that may or may not become public in the future. For future work, other designers could expand upon this project in a number of ways. The designer could decide to change this implementation by using a fully pipelined architecture. The use of the Kogge-Stone adder will be very beneficial when migrating this design to a fully pipelined architecture. By changing this design to a fully pipelined design, the designer would also have the opportunity to reduce the critical path for all operations thus reducing the clock frequency even more, which results in higher throughput. Another way that a designer could expand upon this design would be to add FIFO memory for larger files. For our implementation and simulation, we only input one 64-bit block. We did not input any values larger than 64-bits. Therefore, the implementation could be modified to accept larger input sizes, and encrypt or decrypt multiple blocks of data than just one block of data. REFERENCES [1] S. Liu, O. Gavrylyako, and P. Bradford, Implementing the TEA algorithm on Sensors, Proceedings of the 42 nd annual Southeast regional conference, pp , [2] D. Wheeler and R. Needham, TEA, a tiny encryption algorithm, Proc. Fast Software Encryption: Second International Workshop, Lecture Notes in Computer Science, vol. 1008, pp , December [3] P. Israsena, Securing Ubiquitous and Low-Cost RFID Using Tiny Encryption Algorithm, Wireless Pervasive Computing, st International Symposium, pp. 1-4, [4] J. Kelsey, B. Schneider, and D. Wagner, Related-Key Cryptanalysis of 3-WAY, Biham-DES, CAST, DES-X, NewDES, RC2, and TEA, Proceedings of the First International Conference on Information and Communication Security: Lecture Notes In Computer Science; Vol. 1334, pp , [5] D. Wheeler and R. Needham, TEA Extensions, unpublished, October 1997.
Hardware Implementations of RSA Using Fast Montgomery Multiplications. ECE 645 Prof. Gaj Mike Koontz and Ryon Sumner
Hardware Implementations of RSA Using Fast Montgomery Multiplications ECE 645 Prof. Gaj Mike Koontz and Ryon Sumner Overview Introduction Functional Specifications Implemented Design and Optimizations
More informationImplementation of Full -Parallelism AES Encryption and Decryption
Implementation of Full -Parallelism AES Encryption and Decryption M.Anto Merline M.E-Commuication Systems, ECE Department K.Ramakrishnan College of Engineering-Samayapuram, Trichy. Abstract-Advanced Encryption
More informationHow To Encrypt With A 64 Bit Block Cipher
The Data Encryption Standard (DES) As mentioned earlier there are two main types of cryptography in use today - symmetric or secret key cryptography and asymmetric or public key cryptography. Symmetric
More informationCryptography and Network Security Prof. D. Mukhopadhyay Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur
Cryptography and Network Security Prof. D. Mukhopadhyay Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Lecture No. # 11 Block Cipher Standards (DES) (Refer Slide
More informationCryptography and Network Security
Cryptography and Network Security Spring 2012 http://users.abo.fi/ipetre/crypto/ Lecture 3: Block ciphers and DES Ion Petre Department of IT, Åbo Akademi University January 17, 2012 1 Data Encryption Standard
More informationDesign and Analysis of Parallel AES Encryption and Decryption Algorithm for Multi Processor Arrays
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 5, Issue, Ver. III (Jan - Feb. 205), PP 0- e-issn: 239 4200, p-issn No. : 239 497 www.iosrjournals.org Design and Analysis of Parallel AES
More informationCryptography and Network Security Block Cipher
Cryptography and Network Security Block Cipher Xiang-Yang Li Modern Private Key Ciphers Stream ciphers The most famous: Vernam cipher Invented by Vernam, ( AT&T, in 1917) Process the message bit by bit
More informationCSE140 Homework #7 - Solution
CSE140 Spring2013 CSE140 Homework #7 - Solution You must SHOW ALL STEPS for obtaining the solution. Reporting the correct answer, without showing the work performed at each step will result in getting
More informationIJESRT. [Padama, 2(5): May, 2013] ISSN: 2277-9655
IJESRT INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY Design and Verification of VLSI Based AES Crypto Core Processor Using Verilog HDL Dr.K.Padama Priya *1, N. Deepthi Priya 2 *1,2
More informationCSCE 465 Computer & Network Security
CSCE 465 Computer & Network Security Instructor: Dr. Guofei Gu http://courses.cse.tamu.edu/guofei/csce465/ Secret Key Cryptography (I) 1 Introductory Remarks Roadmap Feistel Cipher DES AES Introduction
More informationThe implementation and performance/cost/power analysis of the network security accelerator on SoC applications
The implementation and performance/cost/power analysis of the network security accelerator on SoC applications Ruei-Ting Gu grating@eslab.cse.nsysu.edu.tw Kuo-Huang Chung khchung@eslab.cse.nsysu.edu.tw
More informationCryptography and Network Security Chapter 3
Cryptography and Network Security Chapter 3 Fifth Edition by William Stallings Lecture slides by Lawrie Brown (with edits by RHB) Chapter 3 Block Ciphers and the Data Encryption Standard All the afternoon
More informationAES1. Ultra-Compact Advanced Encryption Standard Core. General Description. Base Core Features. Symbol. Applications
General Description The AES core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. Basic core is very small (start at 800 Actel tiles). Enhanced versions
More informationDesign and Verification of Area-Optimized AES Based on FPGA Using Verilog HDL
Design and Verification of Area-Optimized AES Based on FPGA Using Verilog HDL 1 N. Radhika, 2 Obili Ramesh, 3 Priyadarshini, 3 Asst.Profosser, 1,2 M.Tech ( Digital Systems & Computer Electronics), 1,2,3,
More information6.857 Computer and Network Security Fall Term, 1997 Lecture 4 : 16 September 1997 Lecturer: Ron Rivest Scribe: Michelle Goldberg 1 Conditionally Secure Cryptography Conditionally (or computationally) secure
More informationEnhancing Advanced Encryption Standard S-Box Generation Based on Round Key
Enhancing Advanced Encryption Standard S-Box Generation Based on Round Key Julia Juremi Ramlan Mahmod Salasiah Sulaiman Jazrin Ramli Faculty of Computer Science and Information Technology, Universiti Putra
More information1 Data Encryption Algorithm
Date: Monday, September 23, 2002 Prof.: Dr Jean-Yves Chouinard Design of Secure Computer Systems CSI4138/CEG4394 Notes on the Data Encryption Standard (DES) The Data Encryption Standard (DES) has been
More informationBlock encryption. CS-4920: Lecture 7 Secret key cryptography. Determining the plaintext ciphertext mapping. CS4920-Lecture 7 4/1/2015
CS-4920: Lecture 7 Secret key cryptography Reading Chapter 3 (pp. 59-75, 92-93) Today s Outcomes Discuss block and key length issues related to secret key cryptography Define several terms related to secret
More informationImproving Performance of Secure Data Transmission in Communication Networks Using Physical Implementation of AES
Improving Performance of Secure Data Transmission in Communication Networks Using Physical Implementation of AES K Anjaneyulu M.Tech Student, Y.Chalapathi Rao, M.Tech, Ph.D Associate Professor, Mr.M Basha,
More informationImplementation and Design of AES S-Box on FPGA
International Journal of Research in Engineering and Science (IJRES) ISSN (Online): 232-9364, ISSN (Print): 232-9356 Volume 3 Issue ǁ Jan. 25 ǁ PP.9-4 Implementation and Design of AES S-Box on FPGA Chandrasekhar
More informationInternational Association of Scientific Innovation and Research (IASIR) (An Association Unifying the Sciences, Engineering, and Applied Research)
International Association of Scientific Innovation and Research (IASIR) (An Association Unifying the Sciences, Engineering, and Applied Research) ISSN (Print): 2279-0020 ISSN (Online): 2279-0039 International
More informationKeywords Web Service, security, DES, cryptography.
Volume 3, Issue 10, October 2013 ISSN: 2277 128X International Journal of Advanced Research in Computer Science and Software Engineering Research Paper Available online at: www.ijarcsse.com Provide the
More informationSolutions to Problem Set 1
YALE UNIVERSITY DEPARTMENT OF COMPUTER SCIENCE CPSC 467b: Cryptography and Computer Security Handout #8 Zheng Ma February 21, 2005 Solutions to Problem Set 1 Problem 1: Cracking the Hill cipher Suppose
More informationHardware Implementation of AES Encryption and Decryption System Based on FPGA
Send Orders for Reprints to reprints@benthamscience.ae The Open Cybernetics & Systemics Journal, 2015, 9, 1373-1377 1373 Open Access Hardware Implementation of AES Encryption and Decryption System Based
More informationSecret File Sharing Techniques using AES algorithm. C. Navya Latha 200201066 Garima Agarwal 200305032 Anila Kumar GVN 200305002
Secret File Sharing Techniques using AES algorithm C. Navya Latha 200201066 Garima Agarwal 200305032 Anila Kumar GVN 200305002 1. Feature Overview The Advanced Encryption Standard (AES) feature adds support
More informationDesign and FPGA Implementation of a Novel Square Root Evaluator based on Vedic Mathematics
International Journal of Information & Computation Technology. ISSN 0974-2239 Volume 4, Number 15 (2014), pp. 1531-1537 International Research Publications House http://www. irphouse.com Design and FPGA
More informationParallel AES Encryption with Modified Mix-columns For Many Core Processor Arrays M.S.Arun, V.Saminathan
Parallel AES Encryption with Modified Mix-columns For Many Core Processor Arrays M.S.Arun, V.Saminathan Abstract AES is an encryption algorithm which can be easily implemented on fine grain many core systems.
More informationAStudyofEncryptionAlgorithmsAESDESandRSAforSecurity
Global Journal of Computer Science and Technology Network, Web & Security Volume 13 Issue 15 Version 1.0 Year 2013 Type: Double Blind Peer Reviewed International Research Journal Publisher: Global Journals
More information40G MACsec Encryption in an FPGA
40G MACsec Encryption in an FPGA Dr Tom Kean, Managing Director, Algotronix Ltd, 130-10 Calton Road, Edinburgh EH8 8JQ United Kingdom Tel: +44 131 556 9242 Email: tom@algotronix.com February 2012 1 MACsec
More informationCMOS Binary Full Adder
CMOS Binary Full Adder A Survey of Possible Implementations Group : Eren Turgay Aaron Daniels Michael Bacelieri William Berry - - Table of Contents Key Terminology...- - Introduction...- 3 - Design Architectures...-
More informationECE 3401 Lecture 7. Concurrent Statements & Sequential Statements (Process)
ECE 3401 Lecture 7 Concurrent Statements & Sequential Statements (Process) Concurrent Statements VHDL provides four different types of concurrent statements namely: Signal Assignment Statement Simple Assignment
More informationHow To Understand And Understand The History Of Cryptography
CSE497b Introduction to Computer and Network Security - Spring 2007 - Professors Jaeger Lecture 5 - Cryptography CSE497b - Spring 2007 Introduction Computer and Network Security Professor Jaeger www.cse.psu.edu/~tjaeger/cse497b-s07/
More informationSplit Based Encryption in Secure File Transfer
Split Based Encryption in Secure File Transfer Parul Rathor, Rohit Sehgal Assistant Professor, Dept. of CSE, IET, Nagpur University, India Assistant Professor, Dept. of CSE, IET, Alwar, Rajasthan Technical
More informationFloating Point Fused Add-Subtract and Fused Dot-Product Units
Floating Point Fused Add-Subtract and Fused Dot-Product Units S. Kishor [1], S. P. Prakash [2] PG Scholar (VLSI DESIGN), Department of ECE Bannari Amman Institute of Technology, Sathyamangalam, Tamil Nadu,
More informationChapter 4 Register Transfer and Microoperations. Section 4.1 Register Transfer Language
Chapter 4 Register Transfer and Microoperations Section 4.1 Register Transfer Language Digital systems are composed of modules that are constructed from digital components, such as registers, decoders,
More informationLecture Note 8 ATTACKS ON CRYPTOSYSTEMS I. Sourav Mukhopadhyay
Lecture Note 8 ATTACKS ON CRYPTOSYSTEMS I Sourav Mukhopadhyay Cryptography and Network Security - MA61027 Attacks on Cryptosystems Up to this point, we have mainly seen how ciphers are implemented. We
More informationNetwork Security Technology Network Management
COMPUTER NETWORKS Network Security Technology Network Management Source Encryption E(K,P) Decryption D(K,C) Destination The author of these slides is Dr. Mark Pullen of George Mason University. Permission
More informationA Study of New Trends in Blowfish Algorithm
A Study of New Trends in Blowfish Algorithm Gurjeevan Singh*, Ashwani Kumar**, K. S. Sandha*** *(Department of ECE, Shaheed Bhagat Singh College of Engg. & Tech. (Polywing), Ferozepur-152004) **(Department
More informationNetwork Security: Secret Key Cryptography
1 Network Security: Secret Key Cryptography Henning Schulzrinne Columbia University, New York schulzrinne@cs.columbia.edu Columbia University, Fall 2000 c 1999-2000, Henning Schulzrinne Last modified September
More informationHorst Görtz Institute for IT-Security
Horst Görtz Institute for IT-Security On the Vulnerability of FPGA Bitstream Encryption against Power Analysis Attacks Extracting Keys from Xilinx Virtex-II FPGAs Amir Moradi, Alessandro Barenghi, Timo
More informationPavithra.S, Vaishnavi.M, Vinothini.M, Umadevi.V
International Journal of Scientific & Engineering Research, Volume 6, Issue 4, April-2015 965 OPTIMIZATION OF AES ALGORITHM USING HARDWARE AND SOFTWARE Pavithra.S, Vaishnavi.M, Vinothini.M, Umadevi.V Abstract-In
More informationChapter 2 Logic Gates and Introduction to Computer Architecture
Chapter 2 Logic Gates and Introduction to Computer Architecture 2.1 Introduction The basic components of an Integrated Circuit (IC) is logic gates which made of transistors, in digital system there are
More informationImproved Method for Parallel AES-GCM Cores Using FPGAs
Improved Method for Parallel -GCM Cores Using FPGAs Karim Moussa Ali Abdellatif, Roselyne Chotin-Avot, abib Mehrez To cite this version: Karim Moussa Ali Abdellatif, Roselyne Chotin-Avot, abib Mehrez.
More informationCRYPTOGRAPHY IN NETWORK SECURITY
ELE548 Research Essays CRYPTOGRAPHY IN NETWORK SECURITY AUTHOR: SHENGLI LI INSTRUCTOR: DR. JIEN-CHUNG LO Date: March 5, 1999 Computer network brings lots of great benefits and convenience to us. We can
More informationLecture 4 Data Encryption Standard (DES)
Lecture 4 Data Encryption Standard (DES) 1 Block Ciphers Map n-bit plaintext blocks to n-bit ciphertext blocks (n = block length). For n-bit plaintext and ciphertext blocks and a fixed key, the encryption
More informationELECTENG702 Advanced Embedded Systems. Improving AES128 software for Altera Nios II processor using custom instructions
Assignment ELECTENG702 Advanced Embedded Systems Improving AES128 software for Altera Nios II processor using custom instructions October 1. 2005 Professor Zoran Salcic by Kilian Foerster 10-8 Claybrook
More informationResearch Article. ISSN 2347-9523 (Print) *Corresponding author Shi-hai Zhu Email:
Scholars Journal of Engineering and Technology (SJET) Sch. J. Eng. Tech., 2014; 2(3A):352-357 Scholars Academic and Scientific Publisher (An International Publisher for Academic and Scientific Resources)
More informationDecimal Number (base 10) Binary Number (base 2)
LECTURE 5. BINARY COUNTER Before starting with counters there is some vital information that needs to be understood. The most important is the fact that since the outputs of a digital chip can only be
More informationLecture 8: Synchronous Digital Systems
Lecture 8: Synchronous Digital Systems The distinguishing feature of a synchronous digital system is that the circuit only changes in response to a system clock. For example, consider the edge triggered
More informationA PPENDIX H RITERIA FOR AES E VALUATION C RITERIA FOR
A PPENDIX H RITERIA FOR AES E VALUATION C RITERIA FOR William Stallings Copyright 20010 H.1 THE ORIGINS OF AES...2 H.2 AES EVALUATION...3 Supplement to Cryptography and Network Security, Fifth Edition
More informationFPGA BASED HARDWARE KEY FOR TEMPORAL ENCRYPTION
FPGA BASED HARDWARE KEY FOR TEMPORAL ENCRYPTION Abstract In this paper, a novel encryption scheme with time based key technique on an FPGA is presented. Time based key technique ensures right key to be
More informationSystems I: Computer Organization and Architecture
Systems I: omputer Organization and Architecture Lecture 8: Registers and ounters Registers A register is a group of flip-flops. Each flip-flop stores one bit of data; n flip-flops are required to store
More informationLet s put together a Manual Processor
Lecture 14 Let s put together a Manual Processor Hardware Lecture 14 Slide 1 The processor Inside every computer there is at least one processor which can take an instruction, some operands and produce
More informationCHAPTER 3 Boolean Algebra and Digital Logic
CHAPTER 3 Boolean Algebra and Digital Logic 3.1 Introduction 121 3.2 Boolean Algebra 122 3.2.1 Boolean Expressions 123 3.2.2 Boolean Identities 124 3.2.3 Simplification of Boolean Expressions 126 3.2.4
More informationNetwork Security: Cryptography CS/SS G513 S.K. Sahay
Network Security: Cryptography CS/SS G513 S.K. Sahay BITS-Pilani, K.K. Birla Goa Campus, Goa S.K. Sahay Network Security: Cryptography 1 Introduction Network security: measure to protect data/information
More informationModule 3: Floyd, Digital Fundamental
Module 3: Lecturer : Yongsheng Gao Room : Tech - 3.25 Email : yongsheng.gao@griffith.edu.au Structure : 6 lectures 1 Tutorial Assessment: 1 Laboratory (5%) 1 Test (20%) Textbook : Floyd, Digital Fundamental
More informationA Comparative Study Of Two Symmetric Encryption Algorithms Across Different Platforms.
A Comparative Study Of Two Symmetric Algorithms Across Different Platforms. Dr. S.A.M Rizvi 1,Dr. Syed Zeeshan Hussain 2 and Neeta Wadhwa 3 Deptt. of Computer Science, Jamia Millia Islamia, New Delhi,
More informationImplementation of Modified Booth Algorithm (Radix 4) and its Comparison with Booth Algorithm (Radix-2)
Advance in Electronic and Electric Engineering. ISSN 2231-1297, Volume 3, Number 6 (2013), pp. 683-690 Research India Publications http://www.ripublication.com/aeee.htm Implementation of Modified Booth
More informationON SUITABILITY OF FPGA BASED EVOLVABLE HARDWARE SYSTEMS TO INTEGRATE RECONFIGURABLE CIRCUITS WITH HOST PROCESSING UNIT
216 ON SUITABILITY OF FPGA BASED EVOLVABLE HARDWARE SYSTEMS TO INTEGRATE RECONFIGURABLE CIRCUITS WITH HOST PROCESSING UNIT *P.Nirmalkumar, **J.Raja Paul Perinbam, @S.Ravi and #B.Rajan *Research Scholar,
More informationStrengthen RFID Tags Security Using New Data Structure
International Journal of Control and Automation 51 Strengthen RFID Tags Security Using New Data Structure Yan Liang and Chunming Rong Department of Electrical Engineering and Computer Science, University
More informationCyber Security Workshop Encryption Reference Manual
Cyber Security Workshop Encryption Reference Manual May 2015 Basic Concepts in Encoding and Encryption Binary Encoding Examples Encryption Cipher Examples 1 P a g e Encoding Concepts Binary Encoding Basics
More informationKey Hopping A Security Enhancement Scheme for IEEE 802.11 WEP Standards
White Paper Key Hopping A Security Enhancement Scheme for IEEE 802.11 WEP Standards By Dr. Wen-Ping Ying, Director of Software Development, February 2002 Introduction Wireless LAN networking allows the
More informationIntroduction to Xilinx System Generator Part II. Evan Everett and Michael Wu ELEC 433 - Spring 2013
Introduction to Xilinx System Generator Part II Evan Everett and Michael Wu ELEC 433 - Spring 2013 Outline Introduction to FPGAs and Xilinx System Generator System Generator basics Fixed point data representation
More informationA New Paradigm for Synchronous State Machine Design in Verilog
A New Paradigm for Synchronous State Machine Design in Verilog Randy Nuss Copyright 1999 Idea Consulting Introduction Synchronous State Machines are one of the most common building blocks in modern digital
More informationFPGA Implementation of RSA Encryption Engine with Flexible Key Size
FPGA Implementation of RSA Encryption Engine with Flexible Key Size Muhammad I. Ibrahimy, Mamun B.I. Reaz, Khandaker Asaduzzaman and Sazzad Hussain Abstract An approach to develop the FPGA of a flexible
More informationLEVERAGING FPGA AND CPLD DIGITAL LOGIC TO IMPLEMENT ANALOG TO DIGITAL CONVERTERS
LEVERAGING FPGA AND CPLD DIGITAL LOGIC TO IMPLEMENT ANALOG TO DIGITAL CONVERTERS March 2010 Lattice Semiconductor 5555 Northeast Moore Ct. Hillsboro, Oregon 97124 USA Telephone: (503) 268-8000 www.latticesemi.com
More information150127-Microprocessor & Assembly Language
Chapter 3 Z80 Microprocessor Architecture The Z 80 is one of the most talented 8 bit microprocessors, and many microprocessor-based systems are designed around the Z80. The Z80 microprocessor needs an
More informationDr. Jinyuan (Stella) Sun Dept. of Electrical Engineering and Computer Science University of Tennessee Fall 2010
CS 494/594 Computer and Network Security Dr. Jinyuan (Stella) Sun Dept. of Electrical Engineering and Computer Science University of Tennessee Fall 2010 1 Introduction to Cryptography What is cryptography?
More informationMessage Authentication Codes
2 MAC Message Authentication Codes : and Cryptography Sirindhorn International Institute of Technology Thammasat University Prepared by Steven Gordon on 28 October 2013 css322y13s2l08, Steve/Courses/2013/s2/css322/lectures/mac.tex,
More informationNetwork Security CS 5490/6490 Fall 2015 Lecture Notes 8/26/2015
Network Security CS 5490/6490 Fall 2015 Lecture Notes 8/26/2015 Chapter 2: Introduction to Cryptography What is cryptography? It is a process/art of mangling information in such a way so as to make it
More informationDesign of an Encryption-Decryption Module Oriented for Internet Information Security SOC Design
Design of an Encryption-Decryption Module Oriented for Internet Information Security SOC Design Yixin Liu, Haipeng Zhang, Tao Feng School of Electronics & Information, Hangzhou Dianzi University, Hangzhou,
More informationBreakthrough AES Performance with. Intel AES New Instructions
White Paper Breakthrough AES Performance with Intel AES New Instructions Kahraman Akdemir, Martin Dixon, Wajdi Feghali, Patrick Fay, Vinodh Gopal, Jim Guilford, Erdinc Ozturk, Gil Wolrich, Ronen Zohar
More informationAutomata Designs for Data Encryption with AES using the Micron Automata Processor
IJCSNS International Journal of Computer Science and Network Security, VOL.15 No.7, July 2015 1 Automata Designs for Data Encryption with AES using the Micron Automata Processor Angkul Kongmunvattana School
More informationASYNCHRONOUS COUNTERS
LB no.. SYNCHONOUS COUNTES. Introduction Counters are sequential logic circuits that counts the pulses applied at their clock input. They usually have 4 bits, delivering at the outputs the corresponding
More informationFPGA IMPLEMENTATION OF AES ALGORITHM
FPGA IMPLEMENTATION OF AES ALGORITHM S.A. Annadate 1, Nitin Ram Chavan 2 1,2 Electronics and Telecommunication Dept, J N Collage of engineering Aurangabad, (India) ABSTRACT Advanced Encryption Standard
More informatione.g. τ = 12 ps in 180nm, 40 ps in 0.6 µm Delay has two components where, f = Effort Delay (stage effort)= gh p =Parasitic Delay
Logic Gate Delay Chip designers need to choose: What is the best circuit topology for a function? How many stages of logic produce least delay? How wide transistors should be? Logical Effort Helps make
More informationFPGA IMPLEMENTATION OF AN AES PROCESSOR
FPGA IMPLEMENTATION OF AN AES PROCESSOR Kazi Shabbir Ahmed, Md. Liakot Ali, Mohammad Bozlul Karim and S.M. Tofayel Ahmad Institute of Information and Communication Technology Bangladesh University of Engineering
More informationLightweight Cryptography From an Engineers Perspective
Lightweight Cryptography From an Engineers Perspective ECC 2007 Acknowledgement Christof Paar A. Bogdanov, L. Knudsen, G. Leander, M. Robshaw, Y. Seurin, C. Vikkelsoe S. Kumar 2 Outline Motivation Hardware
More informationAn On-chip Security Monitoring Solution For System Clock For Low Cost Devices
An On-chip Security Monitoring Solution For System Clock For Low Cost Devices Frank Vater Innovations for High Performance Microelectronics Im Technologiepark 25 15236 Frankfurt (Oder), Germany vater@ihpmicroelectronics.com
More informationETEC 2301 Programmable Logic Devices. Chapter 10 Counters. Shawnee State University Department of Industrial and Engineering Technologies
ETEC 2301 Programmable Logic Devices Chapter 10 Counters Shawnee State University Department of Industrial and Engineering Technologies Copyright 2007 by Janna B. Gallaher Asynchronous Counter Operation
More informationHaving read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop.
Objectives Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop. describe how such a flip-flop can be SET and RESET. describe the disadvantage
More informationSide Channel Analysis and Embedded Systems Impact and Countermeasures
Side Channel Analysis and Embedded Systems Impact and Countermeasures Job de Haas Agenda Advances in Embedded Systems Security From USB stick to game console Current attacks Cryptographic devices Side
More informationLecture 5: Gate Logic Logic Optimization
Lecture 5: Gate Logic Logic Optimization MAH, AEN EE271 Lecture 5 1 Overview Reading McCluskey, Logic Design Principles- or any text in boolean algebra Introduction We could design at the level of irsim
More informationCryptography and Network Security Prof. D. Mukhopadhyay Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur
Cryptography and Network Security Prof. D. Mukhopadhyay Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Module No. #01 Lecture No. #10 Symmetric Key Ciphers (Refer
More information1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1.
File: chap04, Chapter 04 1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1. 2. True or False? A gate is a device that accepts a single input signal and produces one
More informationExperiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa
Experiment # 9 Clock generator circuits & Counters Eng. Waleed Y. Mousa 1. Objectives: 1. Understanding the principles and construction of Clock generator. 2. To be familiar with clock pulse generation
More informationA Parallel Processor for Distributed Genetic Algorithm with Redundant Binary Number
A Parallel Processor for Distributed Genetic Algorithm with Redundant Binary Number 1 Tomohiro KAMIMURA, 2 Akinori KANASUGI 1 Department of Electronics, Tokyo Denki University, 07ee055@ms.dendai.ac.jp
More informationSecurity+ Guide to Network Security Fundamentals, Third Edition. Chapter 6. Wireless Network Security
Security+ Guide to Network Security Fundamentals, Third Edition Chapter 6 Wireless Network Security Objectives Overview of IEEE 802.11 wireless security Define vulnerabilities of Open System Authentication,
More informationA Secure Software Implementation of Nonlinear Advanced Encryption Standard
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) ISSN: 2319 4200, ISBN No. : 2319 4197 Volume 1, Issue 5 (Jan. - Feb 2013), PP 44-48 A Secure Software Implementation of Nonlinear Advanced Encryption
More informationSpeeding Up RSA Encryption Using GPU Parallelization
2014 Fifth International Conference on Intelligent Systems, Modelling and Simulation Speeding Up RSA Encryption Using GPU Parallelization Chu-Hsing Lin, Jung-Chun Liu, and Cheng-Chieh Li Department of
More information6 Data Encryption Standard (DES)
6 Data Encryption Standard (DES) Objectives In this chapter, we discuss the Data Encryption Standard (DES), the modern symmetric-key block cipher. The following are our main objectives for this chapter:
More informationEncryption Quality Analysis and Security Evaluation of CAST-128 Algorithm and its Modified Version using Digital Images
Encryption Quality Analysis and Security Evaluation CAST-128 Algorithm and its Modified Version using Digital s Krishnamurthy G N, Dr. V Ramaswamy Abstract this paper demonstrates analysis well known block
More informationCryptography and Network Security. Prof. D. Mukhopadhyay. Department of Computer Science and Engineering. Indian Institute of Technology, Kharagpur
Cryptography and Network Security Prof. D. Mukhopadhyay Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Module No. # 01 Lecture No. # 12 Block Cipher Standards
More informationEvaluating The Performance of Symmetric Encryption Algorithms
International Journal of Network Security, Vol.10, No.3, PP.213 219, May 2010 213 Evaluating The Performance of Symmetric Encryption Algorithms Diaa Salama Abd Elminaam 1, Hatem Mohamed Abdual Kader 2,
More informationFlip-Flops, Registers, Counters, and a Simple Processor
June 8, 22 5:56 vra235_ch7 Sheet number Page number 349 black chapter 7 Flip-Flops, Registers, Counters, and a Simple Processor 7. Ng f3, h7 h6 349 June 8, 22 5:56 vra235_ch7 Sheet number 2 Page number
More informationHardware Implementation of the Stone Metamorphic Cipher
International Journal of Computer Science & Network Security VOL.10 No.8, 2010 Hardware Implementation of the Stone Metamorphic Cipher Rabie A. Mahmoud 1, Magdy Saeb 2 1. Department of Mathematics, Faculty
More informationAN RC4 BASED LIGHT WEIGHT SECURE PROTOCOL FOR SENSOR NETWORKS
AN RC4 BASED LIGHT WEIGHT SECURE PROTOCOL FOR SENSOR NETWORKS Chang N. Zhang and Qian Yu Department of Computer Science, University of Regina 3737 Wascana Parkway, Regina, SK S4S 0A2 Canada {zhang, yu209}@cs.uregina.ca
More informationCHAPTER 11: Flip Flops
CHAPTER 11: Flip Flops In this chapter, you will be building the part of the circuit that controls the command sequencing. The required circuit must operate the counter and the memory chip. When the teach
More informationA New 128-bit Key Stream Cipher LEX
A New 128-it Key Stream Cipher LEX Alex Biryukov Katholieke Universiteit Leuven, Dept. ESAT/SCD-COSIC, Kasteelpark Arenerg 10, B 3001 Heverlee, Belgium http://www.esat.kuleuven.ac.e/~airyuko/ Astract.
More information