The Effect and Technique of System Coherence in ARM Multicore Technology

Transcription

1 The Effect and Technique of System Coherence in ARM Multicore Technology John Goodacre Senior Program Manager ARM Division Cambridge, UK Cortex -A9 Microarchitecture (single core variant) Coresight / JTAG Debug Cortex A9 Single core CoreSight Debug Access Port Profiling Monitor Block Dual-instruction Decode stage queue Prediction queue Virtual to physical register pool Register Rename stage Branch Monitor Out of order multi-issue with speculation queue and Dispatch + Dispatch stage Auto-prefetcher ALU/MUL ALU- ALU ALU- Address Memory System OoO Write back stage IRQ/FIQ PL9 Interrupt prefetch stage Branch Prediction Fast-loop mode cache Global History Buffer BR-Target Addr Return Stack Load-Store Unit Store Buffer Dual-instruction Decode stage quad-slot with forwarding µtlb MMU Program Trace Unit PL L L Control Bus Interface Unit (BIU) Master interface Secondary master (with filtering) ECC RAMs Coresight Trace AMBA AXI bit

2 Cortex-A9 MPCore Structure ARM Coresight Multcore Debug and Trace Architecture Tightly coupled multiple core configuration enables range of AMP and SMP configurations, configurable at boot time Generalized Interrupt Control and Distribution Primary AMBA bit Interface -- Transfers Snoop Control Unit (SCU) Advanced Bus Interface Unit Snoop Filtering L (PL) Timers Coherence Port Optional nd with Address Filtering Modified MESI coherency protocol for cache-tocache transfers and direct data intervention coherence port (ACP) enables acceleration engines and peripherals to share multicore optimized coherency design Event bus across cores for fine grained communication within coherency domain Addressing system performance System performance is not only defined by the processor Speed/width and latency of DRAM and processor system interface Connectivity and efficiency interacting with system components Offchip Bridged components On chip system components Tightly coupled components Process System Bus Bridge Interconnect Important to consider system design, especially interaction with other system components such as and accelerators DRAM DRAM Interface

3 Traditional SoC Integration 7 GPIO Interconnect Memory flushes data from cache to make visible to accelerator. Writes to mailbox to indicate availability of data Interrupt serviced by accelerator Read data from memory Writes result back to memory Notifies availability of result data 7 services interrupt Reads accelerator result data Analysis of traditional SoC accelerator SoC integration Inefficient usage of cache Significant performance and power implications from data movement High signalling latencies due to mailbox access and interrupt latencies Enhanced SoC Integration ARM MPCore: Coherence Port (ACP) Simplified software and reduces cache flush overheads s gain access to cache hierarchy, increasing system performance and reducing overall power Uses AMBA AXI technology for compatibility with standard un-cached peripherals and accelerators Cortex-A9 MPCore (- s) MPCore Technology / SCU L Memory 7 shared, with per-master lockdown to limit high-throughput master flooding ACP Events AMBA AXI leaves data in the cache Next-cycle notify to accelerator to check and process data issues read - may return from L, L, or from main memory issues write of result, L coherence ensured and may be configured to allocated into L cache raises event to to check for result data 7 issues read, may hit in L

4 IPSEC Acceleration Using I/O Coherency ACP provides WAN sub-system with IPSEC IPSEC Header Crypto/Authentication WAN GE FIFOs SCU AMBA AXI Interconnect L L -Packet Buffer AMBA AXI Interconnect DDR TDM PCI LAN GE FIFOs Main Memory. WAN port receives packets and allocates packet into L coherently. IPSEC block processes the packet and modifies coherent memory. Core looks at header, decides it is encrypted and interrupts IPSEC block. ARM core performs NAT/QoS/Firewall and sends packet through LAN port 7 ACP - Access to Shared s Example: CRC engine for TCP packet forwarding on byte packet Using typical system latency, ignoring common processing overhead Assumed writes are fully buffered Algorithm Stage Design style Approximate Cycle Counts Traditional shared memory with mailbox communication ACP attached accelerator with synchronous event Packet received and processed by Flush cache to make data visible to accelerator notified of data availability Reads data from cache line Write data (assuming buffered) reads processes cache line Total latency overhead > [write to mailbox GPIO] Typical - [read data from off-chip] Typical - ~7 cycles [Send Event] [read from L/L] [from L] ~ cycles ACP solution is appropriate for cycle-offload accelerators executing in s of cycles with cache resident workloads. For example in low latency situations required by audio echo cancelation

5 Summary ARM Cortex-A9 has now exposed the MPCore coherence technology to the wider SoC Interface is known as Coherence Port (ACP) We re hearing about ~% reduction in memory transactions due to reduction in cache flushing Software no longer needs to be concerned with cache flush, which can be particularly troublesome on a multicore Q First devices expected be in sample around end of this year 9