CHAPTER 4 THE PARALLEL ALGORITHM FOR DETECTION AND EXECUTION OF ARITHMETIC OPERATIONS AT INTRAINSTRUCTION LEVEL

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1 39 CHAPTER 4 THE PARALLEL ALGORITHM FOR DETECTION AND EXECUTION OF ARITHMETIC OPERATIONS AT INTRAINSTRUCTION LEVEL In this chapter the relevant work of parallelism exploitation within a single statement is presented. The implementation specification and the environment in which the rearrangement method was developed is described. The parallel algorithm, the data structures and the various modules used in the implementation of the parallel algorithm are presented. Also the working of the algorithm is explained with a detailed example. 4.1 EXISTING WORK Y.N.Srikant (1990) deals with a method which parses and constructs the task graph. The task graph is an estimate of operations that could be done in parallel. The operations at the same level indicate that they could be done in parallel. His approach is aimed at a single instruction or intrainstruction level. E.Dekel et al (1983) and Dan Bar-On et al (1985) have represented arithmetic expression as a tree. B.Pradeep et al (1994) considered the tree as input to their program for parallel evaluation. Y.N.Srikant (1990) uses nesting level of parenthesis to find the parallel operations. His algorithm fails to produce nesting level when the

2 40 operators are of the same precedence. Similarly when the expression is enclosed within parenthesis and the operators are of the same precedence, the output of the algorithm is the same as the input. Hence, nesting levels are not produced and therefore parallel operations cannot be detected. For instance if statement (4.1) is subjected to the algorithm, statement (4. 2) is produced as the result. Since there is no nesting level, the algorithm fails to identify parallel operations. a + b + c + d (a + b + c + d) (4.1) (4.2) If statement (4.2) is given as input to the algorithm, the output would also be statement (4.2) only. So, again nesting level is not produced and parallel operations cannot be detected. Proper association reduces tree height ( D.J.Kuck et al 1972). For example, a + b + c + d may be computed as (((a + b)+c)+d) in 3 steps or as (a +b) + (c +d) in 2 steps. The expression, a +b *c +d can be evaluated as (b *c)+(a +d) by combining associative and commutative properties. Since subtraction and division are neither commutative nor associative, they are treated differently. Subtraction is handled as addition if + and - operators are properly interchanged. The authors treat (a +b-c-d) as (a +b)-(c +d) and a *b/c/d as (a *b)/(c *d). 4.2 IMPLEMENTATION SPECIFICATION In the implementation of the algorithm, operators, +,-,*,/,(,), variables and constants are considered in the formation of the arithmetic expression. The expression is stored in every processor. Mesh architecture is used and the time

3 41 complexity of this parallel algorithm is 0(log n) where, n is the number of elements in the given arithmetic expression. The number of processors are assumed to be as many as the number of elements of the arithmetic expression, namely n. 4.3 IMPLEMENTATION ENVIRONMENT Description of the hardware PARAM, a network of transputers is the machine used for the implementation. Transputers, are special kind of Microprocessors with a Floating point unit, four high speed bidirectional datalinks and on-chip fast memory of four kilo bytes, besides the main central processing unit (CPU). These machines consists of two parts, the front-end and the back-end. The front end is the host and the back-end is the compute engine which is a network of transputers. The host can be a personal computer, a SUN or a VAX machine. All the development work is done on the host machine and the bootable image of the parallel program is downloaded to the back-end network for actual execution Running a parallel program PARAS is a software development environment for message passing machines built around transputers. These message passing machines are general purpose MIMD machines which employ a network of processing nodes to solve a single problem. Processing nodes execute sequential programs ' asynchronously and co-operate by sending data in the form of messages. The collection of interacting sequential programs, which collectively perform a single job, is called a parallel program.

4 42 An application program with PARAS is developed into a bootable file using four basic tools, namely, the compiler pcc, the linker pin, the configurer pconf and the collector pcollect. The compiler takes source code and generates an object code in a file with a name ending with.teo. The linker takes a number of object code files, programmer created library' and the system library as input and generates the task image in a linked unit.lku file. The configurer takes a configuration file with the file name extension.cfs specifying the details of processing nodes, their interconnection topology, description of tasks and their placement, that is, which task is to be placed on which node. The configurer produces a binary file with extension.cfb. The collector takes the output of the configurer, a file with extension.cfb, places the self loading code and outputs a bootable image of the application with extension.btl. The bootable image is then executed on the parallel machine using the pserver of the PARAS Structure of the configuration file A node topology and a task specification is required for the configuration stage. The network of nodes is specified in terms of number and type of processors and their connectivity. The connectivity is achieved by the connect statement. Tasks are specified with expected memory requirements of various segments of the code. The actual placement of the tasks on the processors is mentioned in the place statement. Finally, the linked unit to be used for the task is given by the use statement. The use statement specifies the physical process to be associated with the logical process. The sample code used for configuring is as follows, in which the source file is hello.c and logical process is mytask :

5 43 T800 (memory = 4M) mynode; connect mynode.link[0], host; /* specification for the tasks */ process (stacksize = 100k, heapsize =100k) mytask; /* placement of the tasks on the declared processors */ place mytask on mynode; /* specify the linked units for the tasks */ use 'hello.lku' for mytask; /* Where the source file is 'hello.c' */ 4.4 DATA STRUCTURES USED The data structures used in the implementation of this algorithm are given in Figure The data structure DECIDE The fields of DECIDE, a doubly linked list are as follows: lptr and rptr are the link fields; symbol denotes the operator in that processor; pr-id denotes the processor identifier; precedence denotes the precedence of the operator. The significance of the mark field will be explained in due course The data structure OPERATE The doubly linked list is maintained for identifying which processor should route the data for the parallel operation. In other words, operand details in various processors are stored in this list. The operands are stored in each of the individual processors in the variable res.

6 44 lptr pr-id symbol precedence mark rptr DECIDE lptr pr-id rptr OPERATE Figure 4.1 Data structures 4.5 DESCRIPTION OF THE MODULES USED The functions performed by the various modules used in the implementation of the algorithm to detect and execute the parallel operations are given in this section Precedence calculation module - precal The variable precedence is a field in the doubly linked list. The variable paren indicates the nesting level of the parenthesis and is used in precedence determination, whose initial value is zero. When the current value of paren is added to default precedence value of the symbol, the precedence is increased.

7 The default precedence of operators is as given in Table 4.1. Table 4.1 Default precedence Operators Value of default precedence ( 3 ) -2 +, - 1 *,/ Algorithm for calculation of precedence Step 1: precedence = paren + default value of symbol Step 2: Check whether the current operator is the left parenthesis *( Step 3: If symbol = ( then paren = paren + 3 Step 4: If symbol is the right parenthesis *) then paren = paren - 3 Step 5: [On encountering a )\ nesting level is closed ] Set precedence = -2 [default value]

8 Working of the precedence calculation algorithm Whenever an operator is encountered, precedence is calculated as the sum of paren and the default precedence value of the encountered operator, symbol is as given in Table 4.1; paren is used to increase the precedence of operators enclosed within parenthesis. If the current encountered operator is (\ paren is incremented by three to indicate the nesting level. Similarly if ) is encountered paren is decremented by three to indicate that a nesting level is over and precedence of ) is set as -2. EXPRESSION a + b- c + d + (e*f) PRECEDENCE Figure 4.2 Assignment of precedence Result calculation module - updatel This module is executed when the last operation is encountered. Any processor containing the root of the equivalent tree of the arithmetic expression, computes the operation and sends the result to the processor 0.

9 Routing of operands Every processor has an identifier denoted by the pr-id field in the data structures. OPERATE->pr-id is the first processor containing the operand for the parallel operation. OPERATE->rptr->pr-id is the second processor containing the operand for the parallel operation. DECIDE->pr-id is the processor which is to perform the parallel operation. The processor represented by the pr-id field in the OPERATE node routes the first operand to the processor containing the operator which is denoted by the DECIDE node. The processor represented by the pr-id field in the successor node of OPERATE, routes the second operand to the processor containing the operator which is denoted by the DECIDE node Receiving operands The processor containing the operator is represented by the pr-id field of DECIDE and it performs the operation. Only the processor containing the operator would execute receive statements. if (DECIDE->pr-id = node-id), then, the execution steps are as follows: 1. Receive the first operand from the processor represented by OPERATE->pr-id 2. Receive the second operand from the processor represented by OPERATE->rptr->pr-id 3. Evaluate the operation by invoking compute 4. Send the value to node 0

10 Reversing module - update2 When the precedence of the previous operator and the current operator is the same, this module checks for (-,+) or (/,*) combination and reverses them; the steps are as follows: 1. The reve flag is set to one 2. The previous and current operators (-,+) or (/,*) are exchanged as (+,-) and (*,/) respectively. 3. The updateo module is called Update module - updateo The steps in the working of the updateo module are given below: 1. The mark field is set to 1 to indicate operation completion. 2. The processors containing operands for the operation are determined. 3. If the operator is enclosed within parenthesis the mark field is set to indicate that nesting level has been processed. 4. The operands are routed. 5. OPERATE is updated to reflect the result of the computation and the node representing the operands involved in the computation are deleted from the data structure. PREV and DECIDE pointers are updated.

11 Compute module - compute The sequence of functions are, 1. Determine the operator 2. Perform the operation 3. Return the result 4.6 THE PARALLEL ALGORITHM The steps involved in the algorithm for detection and execution of parallel operations are given below: 1. The processors scan the input and construct the data structures DECIDE and OPERATE. 2. Set TEMP = DECIDE and PREV = NULL 3. The first operator s precedence is compared with the second operator. If the first operator s precedence is greater than that of the second it is one of the parallel operations. The function updateo is called and the operation is performed. All the other processors update the data structures DECIDE and OPERATE. If the precedence of the current node is greater than or equal to the precedence of the successor node and if the current node is not the only node then updateo module is invoked.

12 50 Else if the current node is the only node updatel module is invoked. Else PREV and DECIDE pointers are updated. 4. As long as DECIDE is not NULL, this step is repeated. If precedence of DECIDE > precedence of PREV and if precedence of DECIDE >= the successor s precedence or the successor is not existing, then updateo module is invoked. Else if precedence of DECIDE is less than the predecessor s precedence or less than the successor s precedence, then PREV and DECIDE pointers are updated else the reverse module, update2 is executed. 5. Set DECIDE = TEMP 6. Set OPERATE = TEMPI 7. Delete all nodes with mark field equal to 1 8. Repeat through step 2 until DECIDE is not equal to NULL

13 EXPLANATION OF THE ALGORITHM below: The algorithm is explained with the sample expression (4.3) given a+b-c+d+(e*f) (4.3) The working of the algorithm is explained in Table 4.2 to The assignment of precedence according to Table 4.1 is given in Figure 4.2. Table 4.2 depicts the data structure DECIDE which will be residing in all the processors. Table 4. 3 depicts the data structure OPERATE which will be residing in all the processors. Table 4.2 The initial data structure DECIDE lptr pr-id symbol precedence mark rptr NULL ( 3 10 * 5 12 ) -2 NULL In Table 4.2, processor with pr-id 1 has the same precedence as processor 3. So it can be executed. That is why the mark field is set to 1 in Table 4.4. PREV and DECIDE point to the row containing pr-id 3 and 5 respectively in Table 4.4. In Table 4.3, the nodes representing processors with pr-id 0 and 2 are removed, since they will route the data to processor 1 for the operation and results are furnished in Table 4.5. The updations to the data

14 52 structures are made in all the processors. In Table 4.4 the next possible parallel operation is in the processor with the value of the pr-id as 5. But, since in processor 3, operator exists the update2 module is called and operators are changed as shown in Table 4.6. The need for rearrangement is explained below. If a +b, c +d in statement (4.3) are computed in parallel and then the result of these operations are subtracted, it will deviate from the sequential processing result. Hence, if the expression is rewritten as a +b +d-c, then a +b and d-c can be performed in parallel and the results are added, it will still produce the same result as sequential processing. The OPERATE data structure gets updated as in Table 4.7 when processor with pr-id 5, performs the operation. That is, PREV pointer is set to the node represented by the rptr of DECIDE (the row with pr-id value as 7 ) and the pointer of DECIDE is set to the rptr of PREV (the node with the pr-id value as 8). But its precedence is less than the successor. So PREV and DECIDE are updated to point to the next node respectively. Since the precedence of DECIDE (that is node with pr-id 10 ) is greater than the predecessor and successor, it is executed and the enclosing parenthesis are removed. Hence their mark field is set to 1. As a result, the data structure OPERATE changes as shown in Table 4.8. All nodes having mark field set to 1 are deleted from DECIDE. The updated structure is given in Table 4.9. Node 3 performs the operation and OPERATE is updated as furnished in Table DECIDE is updated and shown in Table Since there is only one node, DECIDE->rptr is NULL. Therefore updatel module is called which executes the operation and sends the result to node 0.

15 53 Table 4.3 The initial data structure OPERATE lptr pr-id rptr NULL NULL Table 4.4 The data structure DECIDE indicating a parallel operation lptr pr-id symbol precedence mark rptr NULL ( 3 10 * 5 12 ) -2 NULL

16 Table 4.5 The data structure OPERATE reflecting the computation performed by processor 1 lptr pr-id rptr NULL NULL Table 4.6 The data structure DECIDE indicating all the parallel operations and the rearrangement of operators lptr pr-id symbol precedence mark rptr NULL ( * ) -2 1 NULL Appendix 1. The program modules implementing the algorithm is given in

17 Table 4.7 The data structure OPERATE reflecting the computation performed by processor 5 lptr pr-id rptr NULL NULL Table 4.8 The data structure OPERATE reflecting the computation performed by processor 10 lptr pr-id rptr NULL NULL Table 4.9 The updated data structure DECIDE lptr pr-id symbol precedence mark rptr NULL NULL

18 56 Table 4.10 The data structure OPERATE reflecting the computation performed by processor 3 Iptr pr-id rptr NULL 3 10 NULL Table 4.11 The final data structure DECIDE lptr pr-id symbol precedence mark rptr NULL NULL 4.8 CONCLUSION A parallel approach to detect and evaluate arithmetic operations at intrainstruction level has been discussed. Rearrangements have also been discussed which will help in exploiting maximum parallelism. The existing method assumes tree of an expression as input. This chapter has discussed the data structures and the modules that have been used in the exploitation of parallelism. Also this chapter focuses on the parallel algorithm which detects and executes the arithmetic binary operations in 0(log n) time, where n is the number of elements of the arithmetic expression. The assumption of this algorithm is that the number of processors are as many as the number of elements of the arithmetic expression. In the next chapter this assumption is constrained to a limited few.