# Model Answers HW2 - Chapter #3

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2 addition to this two-step address issue, since the data bus is also 16 bits, the microprocessor will need 2 bus cycles to fetch the 32-bit instruction or operand. c. For the PC needs 24 bits (24-bit addresses), and for the IR needs 32 bits (32-bit addresses). 3. Consider a hypothetical microprocessor generating a 16-bit address (for example, assume that the program counter and the address registers are 16 bits wide) and having a 16-bit data bus. a. What is the maximum memory address space that the processor can access directly if it is connected to a 16-bit memory? b. What is the maximum memory address space that the processor can access directly if it is connected to an 8-bit memory? c. What architectural features will allow this microprocessor to access a separate I/O space? d. If an input and an output instruction can specify an 8-bit I/O port number, how many 8-bit I/O ports can the microprocessor support? How many 16-bit I/O ports? Explain. a. The Maximum memory address space = 2^16 = 64 Kbytes. b. The Maximum memory address space = 2^16 = 64 Kbytes. Therefore, in (a) and (b), the microprocessor is to access 64K bytes, but the difference thing between them is that the access of 8-bit memory will transfer a 8 bits and the access of 16-bit memory may transfer 8 bits or 16 bits word. c. Separate I/O instructions are needed because during its execution will generate separate its own signals I/O signals. That signals will be different from the memory signals which is generated during the execution for memory instructions. Therefore, one more output pin will be needed to carry I/O signals. d. With an 8-bit I/O port number the microprocessor can support 2^8 = bit input ports, and 2^8 = bit output ports. With an 8-bit I/O port number the microprocessor can support 2^8 = bit input ports, and 2^8 = bit output ports. Thus, the size of the I/O port will not change the number of I/O ports since the number of I/O ports depends on the number of bits which is used to represent the I/O port number (equals to 8 bits in both cases). 4. Consider a 32-bit microprocessor, with a 16-bit external data bus, driven by an 8-MHz input clock. Assume that this microprocessor has a bus cycle whose minimum duration equals four input clock cycles. What is the maximum data transfer rate across the bus that this microprocessor can sustain, in bytes/s? To increase its performance, would it be better to make its external data bus 32 bits or to double the external clock frequency supplied to the microprocessor? State any other assumptions you make, and explain. Hint: Determine the number of bytes that can be transferred per bus cycle. Since minimum bus cycle duration = 4 clock cycles and bus clock = 8 MHz Then, maximum bus cycle rate = 8 M / 4 = 2 M/s

3 Data transferred per bus cycle = 16 bit = 2 bytes Data transfer rate per second = bus cycle rate * data per bus cycle = 2 M * 2 = 4 Mbytes/sec. To increase its performance: By doubling the frequency, it may mean adopting a new chip manufacturing technology (assuming each instruction will have the same number of clock cycles); By doubling the external data bus, that means wider (may be newer) on-chip data bus drivers/latches and modifications to the bus control logic. Therefore, in the first situation the speed of the memory chips will need to double, not to slow down the microprocessor. Regarding the second situation, the word length of the memory will must double to be able to send/receive 32-bit quantities. 5. Consider two microprocessors having 8- and 16-bit-wide external data buses, respectively. The two processors are identical otherwise and their bus cycles take just as long. a. Suppose all instructions and operands are two bytes long. By what factor do the maximum data transfer rates differ? b. Repeat assuming that half of the operands and instructions are one byte long. a. Through a single bus cycle, the 8-bit microprocessor transfers one byte while the 16-bit microprocessor transfers two bytes. The 16-bit microprocessor has twice the data transfer rate. b. By assuming that we have to perform 50 transfers of operands and instructions which 25 are one byte long and 25 are two bytes long. The 8-bit microprocessor needs 25 + (2 x 25) = 75 bus cycles for the transfer. The 16-bit microprocessor needs = 50 bus cycles. Therefore, the data transfer rates differ by a factor of The VAX SBI bus uses a distributed, synchronous arbitration scheme. Each SBI device (i.e., processor, memory, I/O module) has a unique priority and is assigned a unique transfer request (TR) line. The SBI has 16 such lines (TR0,TR1,..., TR15), with TR0 having the highest priority. When a device wants to use the bus, it places a reservation for a future time slot by asserting its TR line during the current time slot. At the end of the current time slot, each device with a pending reservation examines the TR lines; the highest-priority device with a reservation uses the next time slot. A maximum of 17 devices can be attached to the bus. The device with priority 16 has no TR line. Why not? The lowest-priority device has priority 16. That device have to defer to all the others. Therefore, it may transmit in any slot not reserved by the other SBI devices. 7. On the VAX SBI, the lowest-priority device usually has the lowest average wait time. For this reason, the processor is usually given the lowest priority on the SBI. Why does the priority 16 device usually have the lowest average wait time? Under what circumstances would this not be true? From the beginning for any slot, only the priority 16 device may transmit when none of the TR lines is asserted. This provides it the lowest average wait time under most circumstances. We could say that when there is much demand on the bus and most of the time having at least one pending request, that will prevent the priority 16 device to have the lowest average wait time.

6 By assuming that we have a mix of 100 instructions and operands. From the question: 20% of the operands and instructions are 32-bits long, so it is bit. 40% of the operands and instructions are 16-bits long, so it is bit. 40% of the operands and instructions are only 8-bits = 1 byte long, so it is 40 bytes. The number of bus cycles needed for the 16-bit microprocessor will equal to: (20 * 2) = 120 bus cycles. The number of bus cycles needed for the 32-bit microprocessor will equal to: = 100 bus cycles. By calculating the improvement achieved with the 32-bit microprocessor to the 16-bit microprocessor will equal to 20/120 = 16.6%. 15. The microprocessor of (Problem 11) initiates the fetch operand stage of the increment memory direct instruction at the same time that a keyboard actives an interrupt request line. After how long does the processor enter the interrupt processing cycle? Assume a bus clocking rate of 10 MHz. Since the clocking rate is 10 MHz, the clock period is 10 9 s = 100 ns. Since the microprocessor of initiates the fetch operand stage of the increment memory direct instruction at the same time that a keyboard actives an interrupt request line, so no need for this: Four bus clock cycles to fetch opcode Three bus clock cycles to fetch operand address Therefore, the processor requires nine clock cycles to keep executing the instruction. Actually, the Interrupt begins after 9*100 = 900 ns done.

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