An Efficient SIMD-based Quarter-Pixel Interpolation Method for H.264/AVC

Transcription

1 IJCSNS International Journal of Computer Science and Network Security, VOL.6 No.11, November An Efficient SIMD-based Quarter-Pixel Interpolation Metod for H.264/AVC Cae-Bong Son, and Hye-Jeong Co VIA-Multimedia Center, Kwangwoon University, 447-1, Wolgye-Dong, Nowon-Gu, , Seoul, Korea Summary Many media processors wic support SIMD (Single Instruction Multiple Data) instructions ave been widely used for digital signal processing and multimedia applications. In particular, a set of SIMD instructions is very effective in video applications wic reuire bot simple operations and sort data types, mostly 8-bit or 16-bit samples. Tis paper proposes te fast uarter-pixel interpolation of te H.264/AVC, wic can be implemented wit te Intel SIMD instructions. Te implementation of te proposed metod is approximately six times faster tan tat of te JM software for te H.264/AVC uarter-pixel interpolation operation wic needs multiple bilinear and 6-tap filtering. Key words: Media processor, SIMD, H.264/AVC, uarter-pixel interpolation, video codec 1. Introduction H.264/AVC, wic is te latest video compression standard, as surfaced as one of te essential parts in new media suc as Korea s T-DMB and S-DMB, Europe s DVB-H, and te Blu-ray Disc, te new generation DVD. H.264/AVC is superior to prior video compression standards suc as H.261, H.263, MPEG-1, MPEG-2, and MPEG-4 in compression efficiency. In particular, H.264/AVC can ave te same image uality to te MPEG-2 wit only 50% of its bitrate. However, its advanced video compression tecnology to obtain suc a ig compression rates reuires ig computational complexity [1]. One of te tecniues of te H.264/AVC to enance te coding efficiency is te uarter-pixel motion estimation/compensation, wic adopts te 6-tap FIR and bi-linear filters. Te 6-tap filter s coefficient is (1, -5, 20, - 5, 1) for interpolations of luminance and crominance, and it takes about 25% of te entire decoding time at a decoder side [2]. Most of te microprocessors available today support multimedia instructions to accelerate teir application programs. For instance, Intel s Xeon, Pentium IV, and AMD s Atlon64 all ave te MMX, SSE, and SSE2 instructions of te SIMD (Single Instruction Multiple Data) model. Tese instructions can process multiple data in parallel in a single instruction. However, tere are more cases in wic it takes more time to pack or unpack data in teir registers properly tan to do computations in implementation wit te SIMD instructions [3][4]. In tis paper, an optimized SIMD algoritm for te interpolation of te H.264/AVC was proposed in te Intel processor supporting SIMD instructions. Te proposed algoritm is based on te use of symmetry of te 6-tap FIR filter coefficient for parallel computation in te data level, resulting in significant reduction of multiplications. 2. Intel SIMD Tecnology SIMD tecnology was introduced in te IA-32 arcitecture based on te MMX tecnology. MMX tecnology allows SIMD computations to be performed on packed byte, word, and double-word integers. Te integers belong to a set of eigt 64-bit registers called MMX registers. Te Pentium III processor extended te SIMD computation model by employing te Streaming SIMD Extensions (SSE). SSE enables SIMD computations to be performed on operands tat support four packed singleprecision floating-point data elements. Te operands can be loaded in a memory or in a set of eigt 128-bit XMM registers. SSE also extended SIMD computational capability by adding additional 64-bit MMX instructions. Fig. 1 sows a typical SIMD computation in wic two sets of four packed data elements (X1, X2, X3, and X4, and Y1, Y2, Y3, and Y4) are operated in parallel, respectively. In te Pentium 4 processor, te SIMD computation model was enanced by introducing Streaming SIMD Extensions 2 (SSE2) and Streaming SIMD Extensions 3 (SSE3). SSE2 is executed wit operands loaded in eiter memory or in te XMM registers. Te SIMD computation capability was improved to process packed double-precision floating-point data elements and 128-bit packed integers. Te SSE supports 144 instructions, operating on two packed doubleprecision floating-point data elements or on 16 packed byte, 8 packed word, 4 double word, and 2 uad word integers. In te SSE3, SSE and SSE2 are extended by providing additional 13 instructions tat can accelerate application performance in specific areas. Tese include Manuscript received November 5, Manuscript revised November 25, 2006.

2 86 IJCSNS International Journal of Computer Science and Network Security, VOL.6 No.11, November 2006 video processing, complex aritmetic, and tread syncronization. SSE3 complements SSE and SSE2 wit additional instructions tat process SIMD data asymmetrically, facilitate orizontal computation, and avoid loading cace line splits [5]. X4 X3 X2 X1 a = (G+b+1)>>1 d = (G++1)>>1 f = (b+j+1)>>1 k = (j+m+1)>>1 e = (b++1)>>1 p = (+s+1)>>1 c = (H+b+1)>>1 n = (M++1)>>1 i = (+j+1)>>1 = (j+s+1)>>1 g = (b+m+1)>>1 r = (m+s+1)>>1 (2) Y4 Y3 Y2 Y1 OP OP OP OP A aa B X4 op Y4 X3 op Y3 X2 op Y2 X1 op Y1 Fig. 1 Typical SIMD Operations. C bb D 64-bit MMX Register mm0 mm1 mm2 mm3 mm4 mm5 mm6 mm7 128-bit SSE Register xmm0 xmm1 xmm2 xmm3 xmm4 xmm5 xmm6 xmm7 E F G a b c H I J d cc dd i j k m ee ff n R e p f K L M s N P Q gg g r S Fig. 2 SIMD instruction registers. T U 3. Overview of Quarter-Pixel Interpolation In te H.264/AVC standard, a 6-tap FIR filter is at first applied for alf-pixel interpolation in luminance components. Its coefficients are (1, -5, 20, 20, -5, -1) wic can be considered as a low-pass filter. After tat, a bi-linear filter is used for uarter-pixel estimation. For example, te alf-pixels aa, bb, b, cc, dd,, j, m, ee, ff, s, gg, and, as sown in Fig. 3, can be calculated as follows. b = (( E - 5*F + 20*G + 20*H 5*I + J) +16 )/32 = (( A - 5*C + 20*G + 20*M 5*R + T) +16 )/32 m = (( B - 5*D + 20*H + 20*N 5*S + U) +16 )/32 s = (( K - 5*L + 20*M + 20*N 5*P + Q) +16 )/32 j = (( cc - 5*dd + 20*1 + 20*m1 5*ee + ff) +512 )/1024 or ((aa - 5*bb + 20*b1 + 20*s1 5*gg + ) +512 )/1024 (1) For interpolation at te alf-pixel j, interpolations at te neigboring six points, cc, dd, ee, and ff or aa, bb, gg, and sould be available in advance. On te oter and, for uarter-pixels a, c, d, e, f, g, i, k, n, p and, teir interpolations are denoted by Fig. 3 Quarter-pixel interpolation for luminance. All te interpolation points can be classified into layer 0~3, according to teir mutual dependencies. Points in te layer-0 represent te integer pixels tat are originally available as te input. Points at wic te interpolation depends on te layer-0 pixels are classified as te layer-1. In te same way, layer-2 and 3 can be defined. Obviously, te input pixels A, B, C, D,, U belong to te layer-0 and te alf-pixels, b,, m, and s are grouped to te layer-1. Te uarter-pixels, a, c, d, e, g, n, p, r, and j are considered to be in te layer-2. Finally, f, i, k, and longs to te layer-3. Teoretically, all te tree layers of computations sould be performed for interpolation in motion estimation (At an encoder wit 1/4 pixel accuracy). On te oter and, te layer-3 computation is necessary in motion compensation (decoder) for a full compliant to te H.264/AVC baseline specification, depending on motion vector (MV) for eac block [6],[7].

3 IJCSNS International Journal of Computer Science and Network Security, VOL.6 No.11, November Proposed SIMD-based Quarter-Pixel Interpolation Metod In tis paper, a new computation for te uarter-pixel interpolation of te H.264/AVC is proposed for SIMD arcitecture. Te proposed algoritm is derived by minimizing te number of memory access. Te formulas to compute alf-pixel interpolations are proposed by using te symmetry of te 6-tap FIR filter coefficients, resulting in significant reduction of te multiplications. b = (( E 5 * F + 20 * G + 20 * H 5 * I+ J ) + 16 ) / 32 = ((( E + J ) ( F + I ) * 5 + ( G + H ) * 20 ) + 16 ) / 32 = ((( G + H ) * 4 F I ) * 5 + E + J + 16 ) / 32 = (( A 5 * C + 20 * G + 20 * M 5 * R + T ) + 16 ) / 32 = ((( A + T ) ( C + R ) * 5 + ( G + M ) * 20 ) + 16 ) / 32 = ((( G + M ) * 4 C R) * 5 + A + T + 16 ) / 32 (3) Fig.4 sows of te proposed uarter-pixel interpolations in te orizontal direction wit SIMD instructions. In order to carry out interpolations using SIMD instructions, te pixel data sould be loaded in registers, as sown in Fig. 4(a). Tose data could exceed te bites in computing te 6-tap filtering, wic called for converting te byte data into word units wit te PUNPCKxx instructions [5]. Fig. 4(b) sows te 6-tap filtering to compute te euation (3) for eigt alf-pixel values. In Fig. 4(c), te alf-pixel and integer-pixel values are computed wit te instruction along wit uarter-pixel ones. Ten te PUNPCKxx instructions are adopted to store te integer-, alf- and uarter-pixel values at te proper place of te register. (b) A metod to make alf-pixel by using te 6-tap filtering following te euation (3) (c) A metod to make uarter-pixel by using alf- and integer-pixel Fig. 4 An SIMD data flow for te orizontal uarter-pixel interpolations (a)data arrangement for te orizontal interpolations, (b)alf-pixel interpolation by using te 6-tap filtering, (c)uarter-pixel interpolation wit alf- and integer-pixels. (: Half-pixel value, : Quarter-pixel value). (a) Data arrangement for te orizontal interpolations Te uarter-pixel interpolations for te second vertical direction are obtained by computing te integerand alf-pixel information out of te completed information after te uarter-pixel interpolations for orizontal direction. Fig. 5 sows a case of vertical uarter-pixel interpolation using SIMD along wit te way to store te integer- and alf-pixel from te orizontal direction in te register. If you perform te same computation as Fig. 4(b) in te stored register, you can get alf-pixel for te vertical direction. Te uarter-pixel can be obtained by performing Fig. 4(c) in te orizontal direction. Interpolations for bot te directions will leave uarter-pixel for te diagonal element and alf-pixel just as sown in Fig. 6(a). Fig. 6(b) presents a structure to compute te values for te alf-pixel and diagonal

4 88 IJCSNS International Journal of Computer Science and Network Security, VOL.6 No.11, November 2006 elements, wic can be obtained by using te PUNPCKxx and instructions. xmm0 xmm1 xmm2 xmm3 xmm4 xmm5 03 y03 02 y02 01 y01 00 y y13 12 y12 11 y11 10 y10 y23 33 y y43 42 y42 23 y22 21 y21 20 y20 53 y53 52 y52 51 y32 31 y31 30 y30 41 y41 40 y40 y51 50 y50 Fig. 5 Data arrangement to implement vertical uarter-pixel interpolations. : Half-pixel value y : integer-pixel value I I I I I I I I I I (a) Half- and uarter-pixel created after te orizontal and vertical interpolations (b) A metod to make uarter-pixel for te diagonal element and alfpixel. Fig. 6 Data arrangement to implement vertical uarter-pixel interpolations. (a) Half- and uarter-pixel created after te orizontal and vertical interpolations (b) A metod to make uarter-pixel for te diagonal element and alf-pixel. I : integer-pixel value, : Half-pixel value, : Quarter-pixel value. 5. Experiment Results Te processor used in tis experiment is te Intel Pentium IV (2.4GHz), supporting 64-bit MMX and 128-bit SSE2 instructions. VTune performance analyzer was used for PUNCKxx performance profiling and actual execution time is used for performance evaluation [8]. Table 1 presents te numbers of instruction clock ticks of te JM and te proposed metods for te H.264/AVC interpolation. Te proposed SIMD-based interpolation gives benefit for loading and storing of data, multiplication, calculation and logic computation. However, extra computation like packing and unpacking of data is reuired for te proposed algoritm but it is not significant in overall performance. Table 1: Comparison of clock ticks for eac module Metod SIMD JM Horizontal Vertical Instruction Direction Direction Memory Move Logic and Aritmetic Multiply Data pack/unpack Total Clock tick Speedup Table 2 sows te comparison of actual execution time of uarter-pixel interpolation module of te reference encoder, and proposed algoritm using te SSE2(128-bit). We created 100,000 8x8 block generated wit a random number generator, and te average execution time is measured wit te generated data. Eac input video used in our experiment consists of 300 frames. As sown in Table 3, te proposed metod is about 6 times faster tan te JM reference software for an H.264/AVC uarter-pixel interpolation. Table 2: Comparison of excution time and performance of uarter-pixel interpolation for te 8x8 block speedup Time (sec) Speedup metod Horizontal Vertical Horizontal Vertical JM SIMD According to Table 1, te proposed algoritm would be approximately 5.4 times and 9.2 times faster tan te JM for eac direction module. Table 2 sows tat te actual execution time is 5.2 and 8.9 times faster tan te JM for eac directional module. As sown in Table 3, te execution time is measured in terms of image size. Eac input video used in our experiment consists of 300 frames. As sown in Table 3, te proposed metod is about 6 times faster tan te JM reference software for an H.264/AVC uarter-pixel interpolation.

5 IJCSNS International Journal of Computer Science and Network Security, VOL.6 No.11, November Table 3: Comparison of implementation time and performance of uarterpixel interpolation for video seuence speedup Time (sec) metod JM SIMD Speedup QCIF(176x144) QVGA(320x240) CIF(352x288) Conclusions Tis paper presents a optimized metod to uarter-pixel interpolations used in H.264/AVC by using SIMD instructions. Te proposed metod resulted in about 6 times of performance improvement in uarter-pixel interpolations compared to te JM. From our experiments, We ave sown tat proposed metod is suitable for uarter-pixel interpolations at H.264/AVC codecs in SIMD processors. Wit increasingly more real-time applications in H.264 encoders, it is possible tat te proposed SIMD based uarter-pixel interpolation will be indispensable. Acknowledgments Te present Researc as been conducted by te Researc Grant of Kwangwoon University in 2006 Cae-Bong Son received te B.S., M.S., and P.D. degree in electronics engineering form Kwangwoon University, Seoul, Korea in 1993, 1995, and 2006, respectively. From 2000 to 2005, e was a full-time lecturer, Hanyang Women s College, Department of Internet Informations Engineering. He is currently a full-time lecturer, Department of Electronics and Communications Engineering. Kwangwoon University, Seoul, Korea. His researc interests include image compression, transcoding, digital broadcasting systems. Hye-Jeong Co received te B.S. degree in 2004 form te Department of Internet Informations Engineering, Hanyang Women s College, Seoul, Korea. Se is currently pursuing te joint M.S. and P.D. degree in electronics engineering from Kwangwoon University, Seoul, Korea. Her researc interests include video coding, digital broadcasting systems. References [1] J. Ostermann, J. Bormans, PList, D. Marpe, M. Narroske, F. Pereira, T. Stockammer, and T. Wedi, Video coding wit H.264/AVC: tool, performance, and complexity, IEEE Circuit and Syst. Mag. Vol. 4, pp. 7-28, 2004 [2] M. Horowitz, A. Joc, F.kossentini, and A. Hallapuro, H.264/AVC baseline profile decoder complexity analysis, IEEE Trans Circ and Syst. Video Tec, vol. 13, n0 7, pp , 2003 [3] Ricard G., "Te Software Optimization Cookbook", Intel Press, 2002 [4] Intel Corp., "Intel Pentium 4 and Intel Xeon Processor Optimization - Reference Manual", Order Number: , 2002 [5] Intel Corp., " IA-32 Intel Arcitecture Optimization Reference Manual", Order Number: US, April 2006 [6] T. Wiegand, G.J. Sullivan, G. Bjontegaard and A. Luta, Overview of te H.264/AVC Video Coding Standard, IEEE Trans. Circuits Syst. Video Tecnol, vol 13, no.7, pp , July 2003 [7] Wen-Nung Lie, Han-Cing Ye, Lin, T.C.-I, Cien-Fa Cen Hardware-efficient computing arcitecture for motion compensation interpolation in H.264 video coding IEEE international Symposium on Circuit and system, vol. 3, pp , May 2005 [8] Intel Corp., Intel VTune TM Performance Analyzer, Version 7.0, 2003