Broadband Digital Direct Down Conversion Receiver Suitable for Software Defined Radio

Transcription

1 Broadband Digital Direct Down Conversion Receiver Suitable for Software Defined Radio Moamed Ratni, Dragan Krupezevic, Zaoceng Wang, Jens-Uwe Jürgensen Abstract Sony International Europe GmbH, Germany. Advanced Tecnology Center Stuttgart Broadband Wireless Tecnology Researc Wile a significant amount of work as been carried out on digital receivers to support flexible and adaptive ig data rate processing for multiple systems, small interest as been sown on te part and especially te advantages of using a broadband front end. Tis paper presents a callenge raised in te design of a single flexible multimode and multiband receiver. It proposes a new direct down conversion tecnique and its advantages using Six-Port tecniques. A brief study of Six-Port based direct down conversion receiver is first presented. Ten te functionality of tis direct conversion receiver concept is ten verified for a multi-carrier system based on HIPERLAN/ parameters and a single-carrier system based on UMTS-FDD parameters. Tis new direct down conversion receiver tecnique is suitable for multi-system platforms and software defined radios. Introduction Te demand for ig data rate application transmission as increased drastically in te last decade. Furter, wireless communications systems ave evolved from voice services to ig data rate applications during te last few years. Suc broadband applications impose some radio frequency () design callenges. Troug te last decade designers ave progressively converted te conventional eterodyne arcitecture to omodyne conversion and ten to te low-cost direct down conversion arcitecture. Direct conversion receiver (DCR) is very appealing particularly for broadband receivers because of its inerent simplicity and low cost, wen requires only one major integrated circuit for te portion. Moreover, DCR can be implemented on monolitic integration easier tan eterodyne receiver and DCR suffers less from bulky expensive filters needed for image rejection. Direct conversion receiver tecnique as recently become te topic of active researc. Among te different direct conversion receiver arcitectures, te Six-Port receiver is considered as a good candidate [--] for meeting te above requirements. Te Six-Port receiver is used in ig frequency microwave analyzers [4] as well as in Direct Conversion Receiver were a wide bandwidt is required [5-6]. Moreover, te Six-Port tecniques can afford easily broadband applications and teir constrains in respect to te conventional direct receivers were te need of an accurate 90 degree pase sifter is needed at a specific frequency. Tis disadvantage as indered te direct conversion receiver becoming a mainstream approac in today s broadband application. Tis inerent problem can be solved in te six-port tecnique, because, no mixers are used as in conventional direct receiver but power detectors (PD). Tese last ones will detect te voltage levels, wic is proportional to signal. A simple calibration done only once at product manufacture can alleviate te imperfections of te Six-Port cip. Six-Port direct down conversion tecnique It as been sown tat broadband front-end receivers are necessary for future wireless communications systems to fulfill te standard requirements of multiband, multimode and multisystem communication system. Te front end as severe requirements. Te receiver arcitecture design as to cope wit different systems, frequencies, power levels and bandwidt. Tis includes filtering, amplification, down conversion and base-band amplification. On te oter and, digital signal processing needs to be reconfigurable and reprogrammable by software downloading. Several design issues exist in direct conversion arcitecture using Six-Port tecnique, wic require special attention to te front-end design. Te coice of te receiver arcitecture depends first of all on /0/$ IEEE PIMRC 00

2 te system requirements, e.g. Te type of access tecnique (FDMA TDMA, CDMA, and OFDM), modulation type, modulation sub-carriers, cannel spacing and symbol rate. All tese criteria ave to be taken into account in te receiver design. If a monolitic integration (one cip solution) is required, one as to consider process tecnology issues in order to fulfill low cost, low power consumption, and small size. Direct down conversion concept in te case of Six- Port tecnique means simply a translation of te signal to baseband using power readings witout any mixer, terefore, no intermediate frequency. Te cannel filtering is acieved at te baseband using low pass filtering to suppress nearby unwanted signals. Normally additional digital filtering is required, owever, te bandwidt can be reconfigurable. structure Since te power level of te local oscillator does not cange, te number of te output ports can be reduced from four to tree. Te device is ten called. Tis leads to lower cost and smaller size circuit. Te (FP) DCR is a passive linear device (Figure ), consisting of two input ports and tree outputs. A power divider constituted wit a resistive structure and a pase sifter. Te structure uses power detectors instead of conventional mixers. Te structure of te power detector tat we are proposing consists of non-biased FET transistor (Figure.) [4] signal Vgs C C R4 Figure : detector structure Te proposed power detector structure does not need a drain DC-biasing. Te basic detector concept relies on deformation of te signal wit a nonlinear element. In consequence, te signal will be decomposed in DC signal component and a number of armonics. R C RL Vout Te DC signal is ten proportional to te signal amplitude. Te main advantage of using a transistor as a power detector is tat te power consumption is considerably reduced, wile providing at te same time a large dynamic range. On te oter and using a power detector is a key issue to avoid using bulky image rejection filters required for mixers. Te basic functionality of te consists of a sum of a received wit a local oscillator () signal under various pase angles. No mixer is needed to perform tis combination but only a passive combiner (power divider) is utilized (Figure ). Te first power detector measures te signal level. Wile te second and te tird PD measure combined and signal under various pase angles Te power levels at te first PD and te combined signals are used to calculate te in-pase (I) and quadrature (Q) signals. Te pase sift θ of te pase sifter is a linear function of te frequency f. Te acieved pase sift allows te receiver to work in approximately one frequency decade (-9 GHz). Te in-pase (I) and quadrature (Q) signals can be obtained in baseband after a matematical calculation of te tree-output voltage of te power detectors P, P, and P, I = () Q = () + IP + I P + I P Q 0 + P + P + P We assume tat te local oscillator power level is known and does not cange. Te coefficients, I, I, I and 0,,, correspond to te transfer coefficients of te Five- Port receiver. Te calibration procedure consists of solving a system equation wit four unknowns i i Four known signals are sent ( I + jq, i =, 4 ), On te tree outputs of te, we can measure four levels of eac voltages ( P i k, k =,, i =, 4 ). We can write two sets of equations from wic te unknowns (-coefficients) are found from (). Te calibration procedure can be done only

3 I I I I 0 = AI I I I 4 I Q0 Q Q Q = AQ Q Q Q Q Te calibration procedure can be done once at product manufacturer to take into account component tolerances due to te tecnology but, could be also acieved at any time. It can also be carried out after tat as been implemented on te front-end receiver. Tis will alleviate te imperfections of te receiver front-end. In order to ave a multi-band and multi-cannel receiver; a cannel selection can be acieved by simple tuning of te local oscillator signal. direct down conversion structure Te direct down converter tecnique consists of down converting te signal from to base band witout any mixer and wit no intermediate frequency. Figure.. sows one of te proposed arcitecture for broadband front-end receiver supporting bot mobile and Wireless LAN applications. Te circuit arcitecture operates in te & 5 GHz frequency range and can support up to 0 MHz bandwidt Te receiver unit consists of a down-conversion of te transmit signal received from te antenna to base band unit. Te receiver unit performs first a filtering and amplification before te signal is fed to our main direct down converter circuit after a second amplification. Te signal is ten down converted from to base band using te direct down conversion tecniques to base-band. Te tree outputs represent te power reading of te. Tese power levels are ten amplified before A/D conversion. related digital processing is applied using te tree digitized values in order to compute te IQ values. Base-band digital processing Te base-band signal processing of te receiver consists first of A/D conversion before IQ computation, Te base-band DCR concept is depicted in Figure 4. Te first step in te IQ computation is to derive te 4 (), I, I, I and Q0,,, coefficients. As cited above, tese coefficients correspond to te transfer function of te receiver. Teir values are not exactly known, and sould be found troug te process of calibration. Tis process consists of sending one modulated signal on one input of te and a CW signal on te local oscillator () input. Te signal as different levels (at least tree) for eac signal te level is known wit different pase states. Using equation () and () one can derive a system equation from wic te calibration coefficients are obtained. Note tat tis calibration is done off line and can be processed in real time. Te coefficients are ten stored in te memory of te base band unit to calculate te IQ values. After IQ values are derived te system digital processing ten applies specific processing to te IQ values. Tis digital processing consists of filtering, syncronization, FFT, cannel estimation, and demodulated IQ constellations. Prototype and test results A prototype test bed of te transceiver as been set up (Figure 5). Te transmitter unit consists of an up-conversion of base-band signal from te base-band unit, wic delivers a signal wit up to 0 MHz bandwidt at power of 0 dbm to te input of signal. Te signal is ten up-converted to a frequency range between -6 GHz. Te output signal is fed to te transmit antenna after a switc. Te purpose of te switc is to switc between different standards. Te base-band digital processing consists of FPGA based ardware prototyping platform. Terefore a transceiver for te different standard as been implemented: Single-carrier (SC) system based on UMTS-FDD [7] and a multi-carrier system (MC) system based on HIPERLAN/ [8]. Te MC system utilized HIPERLAN/ like parameters in terms of number of sub-carriers and bandwidt. Te SC system utilized UMTS-FDD like parameters in terms of cip rate and bandwidt. Te transmitter was implemented on a prototyping board consisting of a FPGA and D/A converters; te receiver was implemented on a prototyping board consisting of a FPGA and A/D converters.

4 Te tests for te transceiver prototype were performed at two different frequencies 5.5 and.4 GHz. MC signal using HIPERLAN/ like parameters in terms of number of carriers and bandwidt were 6 MHz signal as been transmitted and demodulated. Figure 6a. sows te spectrum of te HIPERLAN/ like transmit signal. Twelve bit A/D converter was used to sample te analog signal out of te. Ten, IQ values are derived from tree power levels based on () and (). After filtering, syncronization was performed. Te input signals were ten transformed to frequency domain by FFT. Finally cannel estimation and equalization were carried out. Figure 6b. Sows te demodulated QPSK constellation signal. SC signal using UTRA-FDD like parameters in terms of cip rate and bandwidt were 5 MHz signal as been transmitted and demodulated. Conclusion New broadband digital direct down conversion tecniques and its advantages using Six-Port tecnique for broadband demodulation ave been demonstrated. Baseband aspects of a direct conversion receiver concept utilizing Six-Port tecnology was also presented. Te functionality of tis direct conversion receiver concept is verified for a multi-carrier system based on HIPERLAN/ parameters and a single carrier system based on UTRA-FDD parameters. Tis new direct down conversion tecnique is suitable for multi-system platform and software defined radio. References [] Ji Li, R.G.Bossisio and Ke Wu: A six port direct digital millimeter wave receiver IEEE MTTSymposium Digest, vol.. pp659-66, San Diego, May 994 [] S. O. Tatu, E. Moldovan, K. We, R. Bosisio. A New Direct Millimeter wave Six-Port Receiver IEEE Trans on MTT,Vol.49,N.,pp.57-5,Dec. 00. [] J. Hyyrylainen, L. Bogod, S. Kangasmaa, H.O. Scek, T. Ylamurto. Six-Port Direct Conversion Receiver EUMC 997. Conference procedings pp [4] M. Ratni, B. Huyart, E. Bergeault, L. P. Jallet. A new structure for a six-port reflectometer using a silicon MOSFET transistor for power measurement IEEE MTT-S Digest, Anaeim CA, USA, 06/99. [5] M.Abe, N.Saso, V.Brankovic, and D.Krupezevic: Direct Conversion Receiver MMIC based on Six-Port Tecnology, ECWT 000, Conference Proceedings, pp. 9-4, Paris, October 000. [6] M. Ratni, D. Krupezevic, V. Brankovic, M. Abe, N. Saso: Design Considerations for Direct Conversion Receiver using Circuit ; EUWC 00. [7] Universal Mobile Telecommunications System (UMTS); UE Radio transmission and reception (FDD) (G TS 5.0 version..0 Release 999); ETSI TS 5 0 v..0 (000-0). [8] Broadband Radio Access Networks (BRAN); HIPERLAN Type ; Pysical (PHY) Layer; ETSI TS v.. (000-04). Signal Directional Coupler Divider Pase Sifter θ Divider Signal Analogue Domain Digital Domain S S Signal Digital IQ Comp. Receiver Signal Processing Output s IQ Values Display Figure 4. Direct conversion receiver concept using P P P Figure. structure

5 .4 GHz Driver Circuit Preselection Cip 5.5 GHz Bias Supply Baseband Unit Figure. direct down conversion receiver structure P P P GHz GHz I Tx Q Tx SMIQ Switc 5GHz PA 5GHz AGC LNA Switc PA DC Amplifier cip DAC DAC DAC DAC 4 AGC Block MC/SC Transmitter Feed troug Baseband Interface P P P FPGA Transmitter module ADC ADC ADC Oscilloscope I Rx Q Rx IQ- Computation MC/SC Receiver FPGA Receiver module Figure 5. Broadband transceiver topology Figure 6a. Transmit signal spectrum at 5.5 GHz Figure 6b. Demodulated QPSK constellation