ILI9320. a-si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color. Datasheet Preliminary

Transcription

1 a-si TFT LC Single Chip river atasheet Preliminary Version: V55 ocument No: S_V55pdf ILI TECHNOLOGY CORP 4F, No, Tech 5 th Rd, Hsinchu Science Park, Taiwan 3, ROC Tel ; Fax

2 Table of Contents Section Page Introduction 7 Features 7 3 Block iagram 9 4 Pin escriptions 5 Pad Arrangement and Coordination 6 Block escription 3 7 System Interface 6 7 Interface Specifications 6 7 Input Interfaces 7 7 i8/8-bit System Interface 8 7 i8/-bit System Interface 9 73 i8/9-bit System Interface 3 74 i8/8-bit System Interface 3 73 Serial Peripheral Interface (SPI) 3 74 VSYNC Interface RGB Input Interface RGB Interface 4 75 RGB Interface Timing Moving Picture Mode bit RGB Interface bit RGB Interface bit RGB Interface45 76 Interface Timing 48 8 Register escriptions 49 8 Registers Access 49 8 Instruction escriptions 5 8 Index (IR) 54 8 Status Read (RS) Start Oscillation (Rh)54 84 river Output Control (Rh) LC riving Wave Control (Rh) Entry Mode (R3h) Resizing Control Register (R4h) isplay Control (R7h) isplay Control (R8h) 6 8 isplay Control 3 (R9h) 6 8 isplay Control 4 (RAh) 6 Page of 9 Version: 54

3 8 RGB isplay Interface Control (RCh) 6 8 Frame Marker Position (h) 63 8 RGB isplay Interface Control (RFh) 64 8 Power Control (Rh) 64 8 Power Control (Rh) 66 8 Power Control 3 (Rh) Power Control 4 (Rh) GRAM Horizontal/Vertical Address Set (Rh, Rh) 67 8 Write ata to GRAM (Rh) 68 8 Read ata from GRAM (Rh) 68 8 Power Control 7 (R9h) 7 83 Frame Rate and Color Control (RBh) 7 84 Gamma Control (R3h ~ R3h) 7 85 Horizontal and Vertical RAM Address Position (R5h, R5h, R5h, R53h) 7 86 Gate Scan Control (R6h, R6h, R6Ah) Partial Image isplay Position (R8h) Partial Image RAM Start/End Address (R8h, R8h) Partial Image isplay Position (R83h) Partial Image RAM Start/End Address (R84h, R85h) Panel Interface Control (R9h) Panel Interface Control (R9h) Panel Interface Control 3 (R93h) Panel Interface Control 4 (R95h) Panel Interface Control 5 (R97h) Panel Interface Control 6 (R98h) 78 9 GRAM Address Map & Read/Write 8 Window Address Function 86 Gamma Correction 88 Application 93 Configuration of Power Supply Circuit 93 isplay ON/OFF Sequence 95 3 eep Standby and Sleep Mode 96 4 Power Supply Configuration 97 5 Voltage Generation 98 6 Applied Voltage to the TFT panel 99 7 Oscillator 99 8 Frame Rate Adjustment 9 Partial isplay Function Resizing Function Page 3 of 9 Version: 54

4 Electrical Characteristics Absolute Maximum Ratings C Characteristics 3 Clock Characteristics 4 Reset Timing Characteristics 5 LC river Output Characteristics 錯 誤! 尚 未 定 義 書 籤 6 AC Characteristics 6 i8-system Interface Timing Characteristics 6 Serial ata Transfer Interface Timing Characteristics 63 RGB Interface Timing Characteristics Revision History 9 Page 4 of 9 Version: 54

5 Figures FIGURE SYSTEM INTERFACE AN RGB INTERFACE CONNECTION 7 FIGURE 8-BIT SYSTEM INTERFACE ATA FORMAT 8 FIGURE3 -BIT SYSTEM INTERFACE ATA FORMAT 9 FIGURE4 9-BIT SYSTEM INTERFACE ATA FORMAT 3 FIGURE5 8-BIT SYSTEM INTERFACE ATA FORMAT 3 FIGURE6 ATA TRANSFER SYNCHRONIZATION IN 8/9-BIT SYSTEM INTERFACE 3 FIGURE 7 ATA FORMAT OF SPI INTERFACE 33 FIGURE8 ATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI) 34 FIGURE9 ATA TRANSMISSION THROUGH VSYNC INTERFACE) 35 FIGURE MOVING PICTURE ATA TRANSMISSION THROUGH VSYNC INTERFACE 35 FIGURE OPERATION THROUGH VSYNC INTERFACE 36 FIGURE TRANSITION FLOW BETWEEN VSYNC AN INTERNAL CLOCK OPERATION MOES 38 FIGURE RGB INTERFACE ATA FORMAT 39 FIGURE GRAM ACCESS AREA BY RGB INTERFACE 4 FIGURE TIMING CHART OF SIGNALS IN 8-/-BIT RGB INTERFACE MOE 4 FIGURE TIMING CHART OF SIGNALS IN 6-BIT RGB INTERFACE MOE 4 FIGURE EXAMPLE OF UPATE THE STILL AN MOVING PICTURE 43 FIGURE8 INTERNAL CLOCK OPERATION/RGB INTERFACE MOE SWITCHING 46 FIGURE9 GRAM ACCESS BETWEEN SYSTEM INTERFACE AN RGB INTERFACE 47 FIGURE RELATIONSHIP BETWEEN RGB I/F SIGNALS AN LC RIVING SIGNALS FOR PANEL 48 FIGURE REGISTER SETTING WITH SERIAL PERIPHERAL INTERFACE (SPI) 49 FIGURE REGISTER SETTING WITH I8 SYSTEM INTERFACE 5 FIGURE 3 REGISTER REA/WRITE TIMING OF I8 SYSTEM INTERFACE 5 FIGURE4 GRAM ACCESS IRECTION SETTING 56 FIGURE5 -BIT MPU SYSTEM INTERFACE ATA FORMAT 57 FIGURE6 8-BIT MPU SYSTEM INTERFACE ATA FORMAT 58 FIGURE 7 ATA REA FROM GRAM THROUGH REA ATA REGISTER IN 8-/-/9-/8-BIT INTERFACE MOE 69 FIGURE 8 GRAM ATA REA BACK FLOW CHART 7 FIGURE 9 GRAM ACCESS RANGE CONFIGURATION 7 FIGURE3 GRAM REA/WRITE TIMING OF I8-SYSTEM INTERFACE 8 FIGURE3 I8-SYSTEM INTERFACE WITH 8-/-/9-BIT ATA BUS (SS=, BGR= ) 8 FIGURE3 I8-SYSTEM INTERFACE WITH 8-BIT ATA BUS (SS=, BGR= ) 83 FIGURE 33 I8-SYSTEM INTERFACE WITH 8-/9-BIT ATA BUS (SS=, BGR= ) 85 FIGURE 34 GRAM ACCESS WINOW MAP 86 FIGURE 35 GRAYSCALE VOLTAGE GENERATION 88 FIGURE 36 GRAYSCALE VOLTAGE AJUSTMENT 89 FIGURE 37 GAMMA CURVE AJUSTMENT 9 FIGURE 38 RELATIONSHIP BETWEEN SOURCE OUTPUT AN VCOM 9 Page 5 of 9 Version: 54

6 FIGURE 39 RELATIONSHIP BETWEEN GRAM ATA AN OUTPUT LEVEL 9 FIGURE 4 POWER SUPPLY CIRCUIT BLOCK 95 FIGURE 4 ISPLAY ON/OFF REGISTER SETTING SEQUENCE 96 FIGURE 4 EEP STANY/SLEEP MOE REGISTER SETTING SEQUENCE 96 FIGURE 43 POWER SUPPLY ON/OFF SEQUENCE 97 FIGURE 44 VOLTAGE CONFIGURATION IAGRAM 98 FIGURE 45 VOLTAGE OUTPUT TO TFT LC PANEL 99 FIGURE 46 OSCILLATION CONNECTION 99 FIGURE 47 PARTIAL ISPLAY EXAMPLE FIGURE 48 ATA TRANSFER IN RESIZING FIGURE 49 RESIZING EXAMPLE FIGURE 5 I8-SYSTEM BUS TIMING FIGURE 5 SPI SYSTEM BUS TIMING FIGURE5 RGB INTERFACE TIMING8 Page 6 of 9 Version: 54

7 Introduction a-si TFT LC Single Chip river is a 6,4-color one-chip SoC driver for a-tft liquid crystal display with resolution of 4RGBx3 dots, comprising a 7-channel source driver, a 3-channel gate driver,,8 bytes RAM for graphic data of 4RGBx3 dots, and power supply circuit has four kinds of system interfaces which are i8-system MPU interface (8-/9-/-/8-bit bus width), VSYNC interface (system interface + VSYNC, internal clock, [:]), serial data transfer interface (SPI) and RGB 6-/-/8-bit interface (OTCLK, VSYNC, HSYNC, ENABLE, [:]) In RGB interface and VSYNC interface mode, the combined use of high-speed RAM write function and widow address function enables to display a moving picture at a position specified by a user and still pictures in other areas on the screen simultaneously, which makes it possible to transfer display the refresh data only to minimize data transfers and power consumption can operate with 5V I/O interface voltage, and an incorporated voltage follower circuit to generate voltage levels for driving an LC The also supports a function to display in 8 colors and a sleep mode, allowing for precise power control by software and these features make the an ideal LC driver for medium or small size portable products such as digital cellular phones, smart phone, PA and PMP where long battery life is a major concern Features Single chip solution for a liquid crystal QVGA TFT LC display 4RGBx3-dot resolution capable with real 6,4 display color Support MVA (Multi-domain Vertical Alignment) wide view display Incorporate 7-channel source driver and 3-channel gate driver Internal,8 bytes graphic RAM High-speed RAM burst write function System interfaces i8 system interface with 8-/ 9-/-/8-bit bus width Serial Peripheral Interface (SPI) RGB interface with 6-/-/8-bit bus width (VSYNC, HSYNC, OTCLK, ENABLE, [:]) VSYNC interface (System interface + VSYNC) n-line liquid crystal AC drive: invert polarity at an interval of arbitrarily n lines (n: ~ 64) Internal oscillator and hardware reset Resizing function ( /, /4) Reversible source/gate driver shift direction Window address function to specify a rectangular area for internal GRAM access Bit operation function for facilitating graphics data processing Bit-unit write data mask function Page 7 of 9 Version: 54

8 Pixel-unit logical/conditional write function Abundant functions for color display control γ-correction function enabling display in 6,4 colors Line-unit vertical scrolling function Partial drive function, enabling partially driving an LC panel at positions specified by user Incorporate step-up circuits for stepping up a liquid crystal drive voltage level up to 6 times (x6) Power saving functions 8-color mode standby mode sleep mode Low -power consumption architecture Low operating power supplies: IOVcc = 5V ~ 33 V (interface I/O) Vcc = 4V ~ 33 V (internal logic) Vci = 5V ~ 33 V (analog) LC Voltage drive: Source/VCOM power supply voltage VH - GN = 45V ~ 6V VCL GN = -V ~ -3V VCI VCL 6V Gate driver output voltage VGH - GN = V ~ V VGL GN = -5V ~ -V VGH VGL 3V VCOM driver output voltage VCOMH = 3V ~ (VH-5)V VCOML = (VCL+5)V ~ V VCOMH-VCOML 6V a-tft LC storage capacitor: Cst only Page 8 of 9 Version: 54

9 3 Block iagram IOVCC IM[3:] nreset ncs nwr/scl n RS SI SO [:] HSYNC VSYNC OTCLK ENABLE TEST TEST TS[7:] MPU I/F 8-bit -bit 9-bit 8-bit SPI I/F RGB I/F 8-bit -bit 6-bit VSYNC I/F Index Register (IR) 7 Control Register (CR) Graphics Operation Read Latch 7 8 Write Latch 7 Address Counter (AC) V63 ~ LC Source river Grayscale Reference Voltage S[7:] VREGOUT VGS VCC V GN Regulator Graphics RAM (GRAM) OSC OSC RC-OSC Timing Controller LC Gate river G[3:] VCI VCI VCILVL AGN Charge-pump Power Circuit VCOM Generator VCOM VLOUT C+ VH C+ C+ VCL VLOUT VLOUT3 C+ C3- C- C- C+ C3+ C- C- C- VGH VGL VCOMR VCOMH VCOML Page 9 of 9 Version: 54

10 4 Pin escriptions a-si TFT LC Single Chip river Pin Name I/O Type escriptions Input Interface Select the MPU system interface mode IM3, IM, IM, IM/I ncs RS nwr/scl n nreset SI SO [:] I I I I I I I O I/O IOVcc MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc IM3 IM IM IM MPU-Interface Mode Pin in use Setting invalid Setting invalid i8-system -bit interface [:], [8:] i8-system 8-bit interface [:] I Serial Peripheral Interface (SPI) SI, SO * Setting invalid Setting invalid Setting invalid i8-system 8-bit interface [:] i8-system 9-bit interface [:9] * * Setting invalid When the serial peripheral interface is selected, IM pin is used for the device code I setting A chip select signal Low: the is selected and accessible High: the is not selected and not accessible Fix to the GN level when not in use A register select signal Low: select an index or status register High: select a control register Fix to GN level when not in use A write strobe signal and enables an operation to write data when the signal is low Fix to IOVCC level when not in use SPI Mode: Synchronizing clock signal in SPI mode A read strobe signal and enables an operation to read out data when the signal is low Fix to IOVCC level when not in use A reset pin Initializes the with a low input Be sure to execute a power-on reset after supplying power SPI interface input pin The data is latched on the rising edge of the SCL signal Fix to GN level when not in use SPI interface output pin The data is outputted on the falling edge of the SCL signal Let SO as open when not in use An 8-bit parallel bi-directional data bus for MPU system interface mode 8-bit I/F: [:] is used 9-bit I/F: [:9] is used -bit I/F: [:] and [8:] is used 8-bit I/F: [:] is used 8-bit parallel bi-directional data bus for RGB interface operation 6-bit RGB I/F: [:] are used Page of 9 Version: 54

11 Pin Name I/O Type escriptions -bit RGB I/F: [:] and [:] are used 8-bit RGB I/F: [:] are used ENABLE I MPU IOVcc Unused pins must be fixed GN level ata ENEABLE signal for RGB interface operation Low: Select (access enabled) High: Not select (access inhibited) The EPL bit inverts the polarity of the ENABLE signal OTCLK VSYNC HSYNC FMARK OSC OSC I I I O I O MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc Oscillation resistor S7~S O LC G3~G O LC VCOM VCOMH VCOML VCOMR VGS O O O I I TFT common electrode Stabilizing capacitor Stabilizing capacitor Variable resistor or open AGN or external resistor Fix to GN level when not in use ot clock signal for RGB interface operation PL = : Input data on the rising edge of OTCLK PL = : Input data on the falling edge of OTCLK Fix to GN level when not in use Frame synchronizing signal for RGB interface operation VSPL = : Active low VSPL = : Active high Fix to GN level when not in use Line synchronizing signal for RGB interface operation HSPL = : Active low HSPL = : Active high Fix to GN level when not in use Output a frame head pulse signal The FMARK signal is used when writing RAM data in synchronization with frame Leave the pin open when not in use Connect an external resistor for generating internal clock by internal R-C oscillation, or an external clock signal is supplied through OSC LC riving signals Source output voltage signals applied to liquid crystal To change the shift direction of signal outputs, use the SS bit SS =, the data in the RAM address h is output from S SS =, the data in the RAM address h is output from S7 S, S4, S7, display red (R), S, S5, S8, display green (G), and S3, S6, S9, display blue (B) (SS = ) Gate line output signals VGH: the level selecting gate lines VGL: the level not selecting gate lines A supply voltage to the common electrode of TFT panel VCOM is AC voltage alternating signal between the VCOMH and VCOML levels The high level of VCOM AC voltage Connect to a stabilizing capacitor The low level of VCOM AC voltage Adjust the VCOML level with the VV bits Connect to a stabilizing capacitor A reference level to generate the VCOMH level either with an externally connected variable resistor or by setting the register of the When using a variable resistor, halt the internal VCOMH adjusting circuit by setting the register and place the resister between VREGOUT and AGN When generating the VCOMH level by setting the register, leave this pin open Reference level for the grayscale voltage generating circuit The VGS level can be changed by connecting to an external resistor Charge-pump and Regulator Circuit Page of 9 Version: 54

12 Pin Name I/O Type escriptions Vci I Power A supply voltage to the analog circuit Connect to an external power supply supply of 5 ~ 33V AGN I Power AGN for the analog side: AGN = V In case of COG, connect to supply GN on the FPC to prevent noise VciLVL I VciLVL must be at the same voltage level as Vci noise Power VciLVL=5V ~ 33V Connect to the external power supply supply In COG case, connect the VciLVL with Vci on the FPC to prevent VciOUT Vci VLOUT O I O Stabilizing capacitor Vci Stabilizing capacitor Vci Stabilizing capacitor, VH VH O VLOUT VLOUT O Stabilizing capacitor, VGH An internal reference voltage generated between Vci and AGN The amplitude between Vci and GN is determined by the VC[:] bits An internal reference voltage for the step-up circuit The amplitude between Vci and GN is determined by the VC[:] bits Make sure to set the Vci voltage so that the VLOUT, VLOUT and VLOUT3 voltages are set within the respective specification Output voltage from the step-up circuit, which is generated from Vci The step-up factor is set by BT bits VLOUT= 45 ~ 6V Place a stabilizing capacitor between AGN Power supply for the source driver and Vcom drive Connect to VLOUT and VH = 45 ~ 6V Output voltage from the step-up circuit, which is generated from Vci and VH The step-up factor is set by BT bits VLOUT= maxv VGH I VLOUT Power supply for the gate driver, connect to VLOUT VLOUT3 O Stabilizing capacitor, VGL Output voltage from the step-up circuit, which is generated from Vci and VH The step-up factor is set by BT bits VLOUT3= max -5V Place a stabilizing capacitor and shottkey diode between AGN VGL I VLOUT3 Power supply for the gate driver, connect to VLOUT3 VCL O Stabilizing capacitor, VCL VcomL driver power supply VCLC = ~ 33V Place a stabilizing capacitor between AGN C+, C- Step-up I/O C+, C- capacitor Capacitor connection pins for the step-up circuit C+, C- C+, C- Step-up I/O C+, C- capacitor Capacitor connection pins for the step-up circuit C3+, C3- Output voltage generated from the reference voltage VREGOUT Vcc IOVcc I/O I I Stabilizing capacitor or power supply Power supply Power supply V O Power igital core power pad The voltage level is set with the VRH bits VREGOUT is () a source driver grayscale reference voltage, () VcomH level reference voltage, and (3) Vcom amplitude reference voltage Connect to a stabilizing capacitor VREGOUT = 3 ~ (VH 5)V Power Pads A supply voltage to the internal logic: Vcc = 4~33V A supply voltage to the interface pins: IM[3:], nreset, ncs, nwr, n, RS, [:], VSYNC, HSYNC, OTCLK, ENABLE, SCL, SI, SO IOVcc = 5 ~ 33V and Vcc IOVcc In case of COG, connect to Vcc on the FPC if IOVcc=Vcc, to prevent noise Page of 9 Version: 54

13 Pin Name I/O Type escriptions Connect them with the uf capacitor GN I Power supply GN for the logic side: GN = V IOGN I IOGN for the interface pins Power IOGN = V In case of COG, connect to GN on the FPC to supply prevent noise Test Pads VT, V3T - Open ummy pads Connect to IOVcc, GN or leave these pins as open VTEST - Open ummy pad Connect to IOVcc, GN or leave this pin as open VREFC - Open ummy pad Connect to IOVcc, GN or leave this pin as open VREF - Open ummy pad Connect to IOVcc, GN or leave this pin as open VTEST - Open ummy pad Connect to IOVcc, GN or leave this pin as open VREF - Open ummy pad Connect to IOVcc, GN or leave this pin as open VMON - Open ummy pad Connect to IOVcc, GN or leave this pin as open TESTA5 - Open ummy pad Connect to IOVcc, GN or leave this pin as open IOVCCUM~ O Power Output the IOVcc voltage level These pins are internally shorted to IOVCC VCCUM - Power ummy pin Connect to VCC or leave this pin as open IOGNUM~3 O Power Output the GN voltage level These pins are internally shorted to GN When adjacent pins are needed to pull low, tie these pins to IOGNUM~3 OSCUM~4 - Open ummy pads Connect to GN or leave these pins as open OSCUM~ - Open ummy pads Connect to GN or leave these pins as open AGNUM - Power ummy pad Leave this pin as open AGNUM~4 O Power Output the GN voltage level These pins are internally shorted to GN UMMYR~ - - ummy pads Leave these pins as open VGLMY~4 O Open ummy pads Connect to IOVcc, GN or leave these pins as open TESTO~38 O Open Test pins Leave them open TEST,, 5 I IOGN Test pins (internal pull low) Connect to GN TEST3 I Open ummy pin Connect to IOVcc or leave these pins as open TEST4 I Open ummy pin Connect to IOVcc or leave these pins as open TSC I Open ummy pin Connect to GN or leave these pins as open TS~8 I Open Test pins (internal pull low) Leave them open VPP - Open Test pins Must let these pads as open VPP - Open Test pins Must let these pads as open VPP3 - - Test pins Must let these pads as open or connect to GN Liquid crystal power supply specifications Table No Item escription TFT Source river 7 pins (4 x RGB) TFT Gate river 3 pins 3 TFT isplay s Capacitor Structure Cst structure only (Common VCOM) 4 Liquid Crystal rive Output 5 Input Voltage S ~ S7 V ~ V63 grayscales G ~ G3 VGH - VGL VCOM VCOMH - VCOML: Amplitude = electronic volumes VCOMH=VCOMR: Adjusted with an external resistor IOVcc 5 ~ 33V Vcc 4 ~ 33V Vci 5 ~ 33V Page of 9 Version: 54

14 6 Liquid Crystal rive Voltages 7 Internal Step-up Circuits VH 45V ~ 6V VGH V ~ V VGL -5V ~ -V VCL -9V ~ -3V VGH - VGL Max 3V Vci - VCL Max 6V VLOUT (VH) Vci x, x3 VLOUT (VGH) Vci x6, x7, x8 VLOUT3 (VGL) Vci x-3, x-4, x-5 VCL Vci x- Page of 9 Version: 54

15 5 Pad Arrangement and Coordination Page of 9 Version: 54

16 a-si TFT LC Single Chip river Chip Size: um x 67um (including scribe line) Chip thickness : 4um (typ) or 5um (customer order) Pad Location: Pad Center Coordinate Origin: Chip center UMMYR UMMYR TESTO VCCUM VPP VPP VPP VPP VPP VPP VPP VPP VPP3 VPP3 VPP3 TESTO IOGNUM TESTO3 TEST TEST TEST4 TEST5 TEST3 IM/I IM IM IM3 TESTO4 IOVCCUM TESTO5 (-a) TESTO38 TESTO37 UMMYR UMMYR9 VGLMY4 G G4 G6 G8 G Au bump height: um (typ) Au Bump Size: um x um (No 99 ~ 54) Gate: G ~ G3 Source: S ~ S7 5um x 8um (No ~ 98) Input Pads Pad to 98 nreset VSYNC HSYNC OTCLK ENABLE 9 8 TESTO6 IOGNUM TESTO SO SI n nwr/scl RS ncs TESTO8 IOVCCUM TESTO9 FMARK TS8 TS7 TS6 TS5 TS4 TS3 TS TS TS TSC TESTO IOGNUM3 TESTO TESTO 6um G3 G3 G3 G38 G3 VGLMY3 TESTO36 TESTO35 S S S3 S4 S5 S6 S7 S8 S9 Alignment Marks Alignment Mark: -a, -b um Bump View Face Up (Bump View) TESTO3 (-b) Page of 9 Version: 54 OSCUM OSCUM OSC OSCUM3 OSCUM4 OSC OSCUM OSCUM UMMYR3 UMMYR4 IOGN IOGN IOGN IOGN IOGN IOGN IOGN IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC VCC VCC VCC VCC VCC VCC VCC VCC V V V V V V V V V V V V V TESTO VREF TESTO VREF TESTO VREFC TESTO VTEST AGN AGN AGN AGN AGN AGN AGN AGN AGN AGN AGN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN TESTO VTEST TESTO8 VGS TESTO9 VT TESTO VMON TESTO V3T VCOM VCOM VCOM VCOM VCOM VCOM VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH VCOML VCOML VCOML VCOML VCOML VCOML TESTO TESTO3 VREGOUT TESTO4 TESTA5 TESTO5 VCOMR TESTO6 VCL VCL VCL VLOUT VLOUT VLOUT VH VH VH VH VH VH VH VCIOUT VCIOUT VCIOUT VCI VCI VCI VCI VCI VCILVL VCI VCI VCI VCI VCI VCI VCI VCI C- C- C- C- C- C+ C+ C+ C+ C+ C- C- C- C- C- C+ C+ C+ C+ C+ AGNUM VLOUT3 VLOUT3 VGL VGL VGL VGL VGL VGL VGL VGL VGL VGL AGNUM AGNUM3 AGNUM4 VLOUT VLOUT VGH VGH VGH VGH TESTO7 C- C- C- TESTO8 C+ C+ C+ TESTO9 C- C- C- C+ C+ C+ C- C- C- C+ C+ C+ C3- C3- C3- C3+ C3+ C3+ TESTO3 UMMYR5 UMMYR6 X Y um S7 S7 S7 S7 S7 S7 S78 S79 S7 TESTO34 TESTO33 VGLMY G39 G3 G3 G3 G3 G9 G7 G5 G3 G VGLMY UMMYR8 UMMYR7 TESTO3

17 No Name X Y No Name X Y No Name X Y No Name X Y No Name X Y UMMYR RS V VCOMH C UMMYR CS* V VCOMH C TESTO TESTO V VCOML C VCCUM IOVCCUM V VCOML C VPP TESTO V VCOML C VPP FMARK TESTO VCOML C VPP TS VREF VCOML AGNUM VPP TS TESTO VCOML VLOUT VPP TS VREF TESTO VLOUT VPP TS TESTO TESTO VGL VPP TS VREFC VREGOUT VGL 7-55 VPP TS TESTO TESTO VGL VPP TS VTEST TESTA VGL VPP TS AGN TESTO VGL VPP TS AGN VCOMR VGL TESTO TSC AGN TESTO VGL IOGNUM TESTO AGN VCL VGL TESTO IOGNUM AGN VCL VGL TEST TESTO AGN VCL VGL TEST TESTO AGN VLOUT AGNUM TEST OSCUM AGN VLOUT AGNUM TEST OSCUM AGN VLOUT AGNUM TEST OSC AGN VH VLOUT IM/I OSCUM AGN VH VLOUT IM OSCUM GN VH VGH IM OSC GN VH VGH IM OSCUM GN VH VGH TESTO OSCUM GN VH VGH IOVCCUM UMMYR GN VH TESTO TESTO UMMYR GN VCIOUT C RESET* IOGN GN -55 VCIOUT C VSYNC IOGN GN 5-55 VCIOUT C HSYNC IOGN GN VCI TESTO OTCLK IOGN GN 3-55 VCI C ENABLE IOGN GN VCI C IOGN GN VCI C IOGN GN VCI TESTO IOVCC GN VCILVL C IOVCC GN VCI C IOVCC GN VCI C IOVCC TESTO VCI C IOVCC VTEST VCI C IOVCC TESTO VCI C IOVCC VGS VCI C VCC TESTO VCI C TESTO VCC VT VCI C IOGNUM VCC TESTO C C TESTO VCC VMON C C VCC TESTO C C VCC V3T C C VCC VCOM C C VCC VCOM C C V VCOM C C V VCOM C C V VCOM C C V VCOM C TESTO SO V VCOMH C UMMYR SI V VCOMH C UMMYR * V VCOMH C TESTO WR*/SCL V VCOMH C TESTO Page of 9 Version: 54

18 No Name X Y No Name X Y No Name X Y No Name X Y No Name X Y 3 UMMYR G G S S UMMYR G G S S VGLMY G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G VGLMY S S G G TESTO S S G G TESTO S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S Page 8 of 9 Version: 54

19 No Name X Y No Name X Y No Name X Y No Name X Y No Name X Y 6 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S Page 9 of 9 Version: 54

20 No Name X Y No Name X Y No Name X Y No Name X Y No Name X Y 9 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S7-3 5 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S TESTO S S S S TESTO S S S S VGLMY S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G Page of 9 Version: 54

21 No Name X Y No Name X Y No Name X Y G G G G G G G G G G G G5-5 5 G G G G G G G G G G G G G G G G G G4-9 5 G G G G G G G G G G G G3-7 5 G G G G G G8-5 G G G G G G G G G G G G -9 5 G G G G G G G G G G G G G G G G G G8-5 7 G G G G G G G G G G G VGLMY G G UMMYR G G UMMYR G G TESTO G G TESTO G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G Alignment mark X Y 59 G G a G G b -468 Page of 9 Version: 54

22 S ~ S7 G ~ G3 UMMY UMMYR TESTO VGLMY (No 99 ~ 54) 5 Unit: um 5 5 I/O Pads (No ~ 98) Pad Pump Pad Pump 8 7 Page of 9 Version: 54

23 6 Block escription MPU System Interface supports three system high-speed interfaces: i8-system high-speed interfaces to 8-, 9-, -, 8-bit parallel ports and serial peripheral interface (SPI) The interface mode is selected by setting the IM[3:] pins has a -bit index register (IR), an 8-bit write-data register (R), and an 8-bit read-data register (R) The IR is the register to store index information from control registers and the internal GRAM The R is the register to temporarily store data to be written to control registers and the internal GRAM The R is the register to temporarily store data read from the GRAM ata from the MPU to be written to the internal GRAM are first written to the R and then automatically written to the internal GRAM in internal operation ata are read via the R from the internal GRAM Therefore, invalid data are read out to the data bus when the read the first data from the internal GRAM Valid data are read out after the performs the second read operation Registers are written consecutively as the register execution time except starting oscillator takes clock cycle Registers selection by system interface (8-/9-/-/8-bit bus width) I8 Function RS nwr n Write an index to IR register Read an internal status Write to control registers or the internal GRAM by R register Read from the internal GRAM by R register Registers selection by the SPI system interface Function R/W RS Write an index to IR register Read an internal status Write to control registers or the internal GRAM by R register Read from the internal GRAM by R register Parallel RGB Interface supports the RGB interface and the VSYNC interface as the external interface for displaying a moving picture When the RGB interface is selected, display operations are synchronized with externally supplied signals, VSYNC, HSYNC, and OTCLK In RGB interface mode, data (-) are written in synchronization with these signals according to the polarity of enable signal (ENABLE) to prevent flicker on display while updating display data In VSYNC interface mode, the display operation is synchronized with the internal clock except frame synchronization, where the operation is synchronized with the VSYNC signal isplay data are written to the internal GRAM via the system interface In this case, there are constraints in speed and method in writing data to the internal RAM For details, see the External isplay Interface section The allows for switching between the external display interface and the system interface by instruction so that the optimum interface is Page 3 of 9 Version: 54

24 selected for the kind of picture to be displayed on the screen (still and/or moving picture(s)) The RGB interface, by writing all display data to the internal RAM, allows for transferring data only when updating the frames of a moving picture, contributing to low power requirement for moving picture display Bit Operation The supports a write data mask function for selectively writing data to the internal RAM in units of bits and a logical/compare operation to write data to the GRAM only when a condition is met as a result of comparing the data and the compare register bits For details, see Graphics Operation Functions Address Counter (AC) The address counter (AC) gives an address to the internal GRAM When the index of the register for setting a RAM address in the AC is written to the IR, the address information is sent from the IR to the AC As writing data to the internal GRAM, the address in the AC is automatically updated plus or minus The window address function enables writing data only in the rectangular area arbitrarily set by users on the GRAM Graphics RAM (GRAM) GRAM is graphics RAM storing bit-pattern data of,8 (4 x 3x 8/8) bytes with 8 bits per pixel Grayscale Voltage Generating Circuit The grayscale voltage generating circuit generates a liquid crystal drive voltage according to grayscale data set in the γ-correction register to display in 6,4 colors For details, see the γ-correction Register section Timing Controller The timing generator generates a timing signal for operation of internal circuits such as the internal GRAM The timing for the display operation such as RAM read operation and the timing for the internal operation such as access from the MPU are generated in the way not to interfere each other Oscillator (OSC) implements internal/external resistor to generate the oscillation frequency and internal resistor will be used in the default setting User can adjust the frame rate by the Rbh and R9h registers when internal resistor is used or adjust the frame rate by the external resistor which is placed between the OSC and OSC pins LC river Circuit The LC driver circuit of consists of a 7-output source driver (S ~ S7) and a 3-output gate driver (G~G3) isplay pattern data are latched when the 7 th bit data are input The latched data control the source driver and generate a drive waveform The gate driver for scanning gate lines outputs either VGH Page 4 of 9 Version: 54

25 or VGL level The shift direction of 7 source outputs from the source driver is set with the SS bit and the shift direction of gate outputs from the gate driver is set with the GS bit The scan mode by the gate driver is set with the SM bit These bits allow setting an appropriate scan method for an LC module LC river Power Supply Circuit The LC drive power supply circuit generates the voltage levels VREGOUT, VGH, VGL and Vcom for driving an LC Page 5 of 9 Version: 54

26 7 System Interface 7 Interface Specifications has the system interface to read/write the control registers and display graphics memory (GRAM), and the RGB Input Interface for displaying a moving picture User can select an optimum interface to display the moving or still picture with efficient data transfer All display data are stored in the GRAM to reduce the data transfer efforts and only the updating data is necessary to be transferred User can only update a sub-range of GRAM by using the window address function also has the RGB interface and VSYNC interface to transfer the display data without flicker the moving picture on the screen In RGB interface mode, the display data is written into the GRAM through the control signals of ENABLE, VSYNC, HSYNC, OTCLK and data bus [:] In VSYNC interface mode, the internal display timing is synchronized with the frame synchronization signal (VSYNC) The VSYNC interface mode enables to display the moving picture display through the system interface In this case, there are some constraints of speed and method to write data to the internal RAM operates in one of the following 4 modes The display mode can be switched by the control register When switching from one mode to another, refer to the sequences mentioned in the sections of RGB and VSYNC interfaces Operation Mode Internal operating clock only (isplaying still pictures) RGB interface () (isplaying moving pictures) RGB interface () (Rewriting still pictures while displaying moving pictures) VSYNC interface (isplaying moving pictures) RAM Access Setting (RM) System interface (RM = ) RGB interface (RM = ) System interface (RM = ) System interface (RM = ) isplay Operation Mode (M[:]) Internal operating clock (M[:] = ) RGB interface (M[:] = ) RGB interface (M[:] = ) VSYNC interface (M[:] = ) Note ) Registers are set only via the system interface Note ) The RGB-I/F and the VSYNC-I/F are not available simultaneously Page 6 of 9 Version: 54

27 System System Interface 8//6 ncs RS nwr n [:] RGB Interface ENABLE VSYNC HSYNC OTCLK Figure System Interface and RGB Interface connection 7 Input Interfaces The following are the system interfaces available with the The interface is selected by setting the IM[3:] pins The system interface is used for setting registers and GRAM access IM3 IM IM IM/I Interface Mode Pin Setting invalid Setting invalid i8-system -bit interface [:], [8:] i8-system 8-bit interface [:] I Serial Peripheral Interface (SPI) SI, SO * Setting invalid Setting invalid Setting invalid i8-system8-bit interface [:] i8-system 9-bit interface [:9] * * Setting invalid Page 7 of 9 Version: 54

28 7 i8/8-bit System Interface The i8/8-bit system interface is selected by setting the IM[3:] as levels System ncs A nwr n [3:] 8 ncs RS nwr n [:] 8-bit System Interface (6K colors) TRI=, FM[:]= Input ata Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Figure 8-bit System Interface ata Format Page 8 of 9 Version: 54

29 7 i8/-bit System Interface The i8/-bit system interface is selected by setting the IM[3:] as levels The 6K or 65K color can be display through the -bit MPU interface When the 6K color is displayed, two transfers ( st transfer: bits, nd transfer: bits or st transfer: bits, nd transfer: bits) are necessary for the -bit CPU interface TRI FM -bit MPU System Interface ata Format system -bit interface ( transfers/pixel) 65,536 colors * st Transfer R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B 8-system -bit interface ( transfers/pixel) 6,4 colors st Transfer nd Transfer R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B 8-system -bit interface ( transfers/pixel) 6,4 colors st Transfer nd Transfer R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Figure3 -bit System Interface ata Format Page 9 of 9 Version: 54

30 73 i8/9-bit System Interface The i8/9-bit system interface is selected by setting the IM[3:] as and the ~9 pins are used to transfer the data When writing the -bit register, the data is divided into upper byte (8 bits and LSB is not used) lower byte and the upper byte is transferred first The display data is also divided in upper byte (9 bits) and lower byte, and the upper byte is transferred first The unused [8:] pins must be tied to AGN System ncs A nwr n [8:] 9 ncs RS nwr n [:9] 9-bit System Interface (6K colors) TRI=, FM[:]= Input ata st Transfer (Upper bits) 9 nd Transfer (Lower bits) 9 Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Figure4 9-bit System Interface ata Format 74 i8/8-bit System Interface The i8/8-bit system interface is selected by setting the IM[3:] as and the ~ pins are used to transfer the data When writing the -bit register, the data is divided into upper byte (8 bits and LSB is not used) lower byte and the upper byte is transferred first The display data is also divided in upper byte (8 bits) and lower byte, and the upper byte is transferred first The written data is expanded into 8 bits internally (see the figure below) and then written into GRAM The unused [9:] pins must be tied to AGN Page 3 of 9 Version: 54