MCP6021/1R/2/3/4. Rail-to-Rail Input/Output, 10 MHz Op Amps. Features. Description. Applications. Package Types. Design Aids. Typical Application

Transcription

1 Rail-to-Rail Input/Output, 1 MHz Op Amps Features Rail-to-Rail Input/Output Wide Bandwidth: 1 MHz (typical) Low Noise: 8.7 nv/ Hz, at 1 khz (typical) Low Offset Voltage: - Industrial Temperature: ±5 µv (maximum) - Extended Temperature: ±25 µv (maximum) Mid-Supply V REF : MCP621 and MCP623 Low Supply Current: 1 ma (typical) Total Harmonic Distortion: -.53% (typical, G = 1 V/V) Unity Gain Stable Power Supply Range: 2.5V to 5.5V Temperature Range: - Industrial: -4 C to +85 C - Extended: -4 C to +125 C Applications Automotive Multi-Pole Active Filters Audio Processing DAC Buffer Test Equipment Medical Instrumentation Design Aids SPICE Macro Models FilterLab Software Mindi Circuit Designer & Simulator Microchip Advanced Part Selector (MAPS) Analog Demonstration and Evaluation Boards Application Notes Typical Application Photo Detector 1 pf V DD /2 5.6 pf 1 kω Transimpedance Amplifier MCP621 Description The MCP621, MCP621R, MCP622, MCP623 and MCP624 from Microchip Technology Inc. are rail-torail input and output op amps with high performance. Key specifications include: wide bandwidth (1 MHz), low noise (8.7 nv/ Hz), low input offset voltage and low distortion (.53% THD+N). The MCP623 also offers a Chip Select pin (CS) that gives power savings when the part is not in use. The single MCP621 and MCP621R are available in SOT The single MCP621, single MCP623 and dual MCP622 are available in 8-lead PDIP, SOIC and TSSOP. The Extended Temperature single MCP621 is available in 8-lead MSOP. The quad MCP624 is offered in 14-lead PDIP, SOIC and TSSOP packages. The MCP621/1R/2/3/4 family is available in Industrial and Extended temperature ranges. It has a power supply range of 2.5V to 5.5V. Package Types V OUT 1 V SS 2 V IN + 3 V OUT 1 V DD 2 V IN + 3 MCP621 SOT MCP621 PDIP SOIC, MSOP, TSSOP NC 1 V IN 2 V IN + 3 V SS 4 MCP621R SOT V DD V IN V SS V IN 8 NC 7 V DD 6 V OUT 5 V REF MCP622 PDIP SOIC, TSSOP V OUTA 1 V INA 2 V INA + 3 V SS 4 MCP623 PDIP SOIC, TSSOP NC 1 V IN 2 V IN + 3 V SS 4 8 V DD 7 V OUTB 6 V INB 5 V INB + 8 CS 7 V DD 6 V OUT 5 V REF MCP624 PDIP SOIC, TSSOP V OUTA 1 V INA 2 V INA + 3 V DD 4 V INB + 5 V INB 6 V OUTB 7 14 V OUTD 13 V IND 12 V IND + 11 V SS 1 VINC+ 9 V INC 8 V OUTC 29 Microchip Technology Inc. DS21685D-page 1

2 NOTES: DS21685D-page 2 29 Microchip Technology Inc.

3 1. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings V DD V SS...7.V Current at Analog Input Pins (V IN +, V IN )...±2 ma Analog Inputs (V IN +, V IN )... V SS 1.VtoV DD +1.V All Other Inputs and Outputs... V SS.3V to V DD +.3V Difference Input Voltage... V DD V SS Output Short Circuit Current...Continuous Current at Output and Supply Pins...±3 ma Storage Temperature C to +15 C Maximum Junction Temperature (T J ) C ESD Protection On All Pins (HBM; MM)... 2 kv; 2V Notice: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. See Section Input Voltage and Current Limits. DC ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, T A = +25 C, V DD = +2.5V to +5.5V, V SS = GND, V CM = V DD /2, V OUT V DD /2 and R L =1kΩ to V DD /2. Parameters Sym Min Typ Max Units Conditions Input Offset Input Offset Voltage: Industrial Temperature Parts V OS µv V CM = V Extended Temperature Parts V OS µv V CM = V, V DD = 5.V Extended Temperature Parts V OS mv V CM = V, V DD = 5.V T A = -4 C to +125 C Input Offset Voltage Temperature Drift ΔV OS /ΔT A ±3.5 µv/ C T A = -4 C to +125 C Power Supply Rejection Ratio PSRR 74 9 db V CM = V Input Current and Impedance Input Bias Current I B 1 pa Industrial Temperature Parts I B 3 15 pa T A = +85 C Extended Temperature Parts I B 64 5, pa T A = +125 C Input Offset Current I OS ±1 pa Common-Mode Input Impedance Z CM Ω pf Differential Input Impedance Z DIFF Ω pf Common-Mode Common-Mode Input Range V CMR V SS -.3 V DD +.3 V Common-Mode Rejection Ratio CMRR 74 9 db V DD = 5V, V CM = -.3V to 5.3V CMRR 7 85 db V DD = 5V, V CM = 3.V to 5.3V CMRR 74 9 db V DD = 5V, V CM = -.3V to 3.V Voltage Reference (MCP621 and MCP623 only) V REF Accuracy (V REF V DD /2) V REF_ACC mv V REF Temperature Drift ΔV REF /ΔT ±1 µv/ C T A = -4 C to +125 C A Open-Loop Gain DC Open-Loop Gain (Large Signal) A OL 9 11 db V CM = V, V OUT = V SS +.3V to V DD -.3V Output Maximum Output Voltage Swing V OL, V OH V SS +15 V DD -2 mv.5v input overdrive Output Short Circuit Current I SC ±3 ma V DD = 2.5V I SC ±22 ma V DD = 5.5V 29 Microchip Technology Inc. DS21685D-page 3

4 AC ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, T A = +25 C, V DD = +2.5V to +5.5V, V SS = GND, V CM = V DD /2, V OUT V DD /2, R L =1kΩ to V DD /2 and C L = 6 pf. Parameters Sym Min Typ Max Units Conditions Power Supply Supply Voltage V DD V Quiescent Current per Amplifier I Q ma I O = AC Response Gain Bandwidth Product GBWP 1 MHz Phase Margin PM 65 G = +1 V/V Settling Time,.2% t SETTLE 25 ns G = +1 V/V, V OUT = 1 mv p-p Slew Rate SR 7. V/µs Total Harmonic Distortion Plus Noise f = 1 khz, G = +1 V/V THD+N.53 % V OUT =.25V to 3.25V (1.75V ± 1.5V PK ), V DD = 5.V, BW = 22 khz f = 1 khz, G = +1 V/V, R L = 6Ω THD+N.64 % V OUT =.25V to 3.25V (1.75V ± 1.5V PK ), V DD = 5.V, BW = 22 khz f = 1 khz, G = +1 V/V THD+N.14 % V OUT = 4V P-P, V DD = 5.V, BW = 22 khz f = 1 khz, G = +1 V/V THD+N.9 % V OUT = 4V P-P, V DD = 5.V, BW = 22 khz f = 1 khz, G = +1 V/V THD+N.5 % V OUT = 4V P-P, V DD = 5.V, BW = 22 khz Noise Input Noise Voltage E ni 2.9 µvp-p f =.1 Hz to 1 Hz Input Noise Voltage Density e ni 8.7 nv/ Hz f = 1 khz Input Noise Current Density i ni 3 fa/ Hz f = 1 khz MCP623 CHIP SELECT (CS) ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, T A = +25 C, V DD = +2.5V to +5.5V, V SS = GND, V CM = V DD /2, V OUT V DD /2, R L =1kΩ to V DD /2 and C L = 6 pf. Parameters Sym Min Typ Max Units Conditions CS Low Specifications CS Logic Threshold, Low V IL V SS.2 V DD V CS Input Current, Low I CSL µa CS = V SS CS High Specifications CS Logic Threshold, High V IH.8 V DD V DD V CS Input Current, High I CSH.1 2. µa CS = V DD GND Current I SS µa CS = V DD Amplifier Output Leakage I O(LEAK).1 µa CS = V DD CS Dynamic Specifications CS Low to Amplifier Output Turn-on Time t ON 2 1 µs G = +1, V IN = V SS, CS =.2V DD to V OUT =.45V DD time CS High to Amplifier Output High-Z Time t OFF.1 µs G = +1, V IN = V SS, CS =.8V DD to V OUT =.5V DD time Hysteresis V HYST.6 V V DD = 5.V, Internal Switch DS21685D-page 4 29 Microchip Technology Inc.

5 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, V DD = +2.5V to +5.5V and V SS = GND. Parameters Sym Min Typ Max Units Conditions Temperature Ranges Industrial Temperature Range T A C Extended Temperature Range T A C Operating Temperature Range T A C Note 1 Storage Temperature Range T A C Thermal Package Resistances Thermal Resistance, 5L-SOT-23 θ JA 256 C/W Thermal Resistance, 8L-PDIP θ JA 85 C/W Thermal Resistance, 8L-SOIC θ JA 163 C/W Thermal Resistance, 8L-MSOP θ JA 26 C/W Thermal Resistance, 8L-TSSOP θ JA 124 C/W Thermal Resistance, 14L-PDIP θ JA 7 C/W Thermal Resistance, 14L-SOIC θ JA 12 C/W Thermal Resistance, 14L-TSSOP θ JA 1 C/W Note 1: The industrial temperature devices operate over this extended temperature range, but with reduced performance. In any case, the internal junction temperature (T J ) must not exceed the absolute maximum specification of 15 C. CS V OUT t ON High-Z Amplifier On t OFF High-Z 1.1 Test Circuits The test circuits used for the DC and AC tests are shown in Figure 1-2 and Figure 1-3. The bypass capacitors are laid out according to the rules discussed in Section 4.7 Supply Bypass. -1 ma I SS -5 na (typical) -5 na (typical) (typical) I CS 1 na 1 na 1 na (typical) (typical) (typical) FIGURE 1-1: Timing diagram for the CS pin on the MCP623. V DD V R 1µF IN N.1 µf C 1kΩ B1 C B2 V OUT MCP621 C L R L 6 pf 1 kω V DD /2 R G R F V L 2kΩ 2kΩ FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. V DD /2 R N V DD.1 µf 1µF V IN C B1 C B2 V 1kΩ OUT MCP621 C L R L 6 pf 1 kω R G R F V L 2kΩ 2kΩ FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 29 Microchip Technology Inc. DS21685D-page 5

6 NOTES: DS21685D-page 6 29 Microchip Technology Inc.

7 2. TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, T A =+25 C, V DD = +2.5V to +5.5V, V SS =GND, V CM =V DD /2, V OUT V DD /2, R L =1kΩ to V DD /2 and C L = 6 pf. Percentage of Occurances 16% 14% 12% 1% 8% 6% 4% 2% % -5 I-Temp Parts Samples V CM = V T A = +25 C Percentage of Occurances 24% 22% 2% 18% 16% 14% 12% 1% 8% 6% 4% 2% % -2 I-Temp Parts Samples V CM = V T A = -4 C to +85 C Input Offset Voltage (µv) Input Offset Voltage Drift (µv/ C) FIGURE 2-1: Input Offset Voltage, (Industrial Temperature Parts). FIGURE 2-4: Input Offset Voltage Drift, (Industrial Temperature Parts). Percentage of Occurances 24% 22% 2% 18% 16% 14% 12% 1% 8% 6% 4% 2% % E-Temp Parts Samples V DD = 5.V V CM = V T A = +25 C Percentage of Occurances 24% 22% 2% 18% 16% 14% 12% 1% 8% 6% 4% 2% % -2 E-Temp Parts Samples V CM = V T A = -4 C to +125 C Input Offset Voltage (µv) Input Offset Voltage Drift (µv/ C) FIGURE 2-2: Input Offset Voltage, (Extended Temperature Parts). FIGURE 2-5: Input Offset Voltage Drift, (Extended Temperature Parts). Input Offset Voltage (µv) V DD = 2.5V -4 C +25 C +85 C +125 C Common Mode Input Voltage (V) Input Offset Voltage (µv) V DD = 5.5V -4 C +25 C +85 C +125 C Common Mode Input Voltage (V) 6. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage with V DD = 2.5V. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage with V DD = 5.5V. 29 Microchip Technology Inc. DS21685D-page 7

8 1.E-1 1.E+ 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5 1.E+6 1.E+2 1.E+3 1.E+4 1.E+5 1.E+6 MCP621/1R/2/3/4 Note: Unless otherwise indicated, T A =+25 C, V DD = +2.5V to +5.5V, V SS =GND, V CM =V DD /2, V OUT V DD /2, R L =1kΩ to V DD /2 and C L = 6 pf. Input Offset Voltage (µv) V DD = 5.V V CM = V Ambient Temperature ( C) Input Offset Voltage (µv) 2 V CM = V DD / V DD = 5.5V -5 V DD = 2.5V Output Voltage (V) FIGURE 2-7: Temperature. Input Offset Voltage vs. FIGURE 2-1: Output Voltage. Input Offset Voltage vs. Input Noise Voltage Density (nv/ Hz) 1, k 1k 1k 1M Frequency (Hz) Input Noise Voltage Density (nv/ Hz) V DD = 5.V f = 1 khz f = 1 khz Common Mode Input Voltage (V) 5.5 FIGURE 2-8: vs. Frequency. Input Noise Voltage Density FIGURE 2-11: Input Noise Voltage Density vs. Common Mode Input Voltage. CMRR, PSRR (db) CMRR PSRR+ PSRR k 1k 1k 1M Frequency (Hz) PSRR, CMRR (db) CMRR PSRR (V CM = V) Ambient Temperature ( C) FIGURE 2-9: Frequency. CMRR, PSRR vs. FIGURE 2-12: Temperature. CMRR, PSRR vs. DS21685D-page 8 29 Microchip Technology Inc.

9 1.E+ 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5 1.E+6 1.E+7 1.E+8 MCP621/1R/2/3/4 Note: Unless otherwise indicated, T A =+25 C, V DD = +2.5V to +5.5V, V SS =GND, V CM =V DD /2, V OUT V DD /2, R L =1kΩ to V DD /2 and C L = 6 pf. Input Bias, Offset Currents (pa) 1, 1, V DD = 5.5V I B, T A = +125 C I OS, T A = +125 C I B, T A = +85 C I OS, T A = +85 C Common Mode Input Voltage (V) Input Bias, Offset Currents (pa) 1, 1, 1 1 V CM = V DD V DD = 5.5V Ambient Temperature ( C) I B I OS FIGURE 2-13: Input Bias, Offset Currents vs. Common Mode Input Voltage. FIGURE 2-16: vs. Temperature. Input Bias, Offset Currents Quiescent Current (ma/amplifier) C +85 C +25 C -4 C Power Supply Voltage (V) Quiescent Current (ma/amplifier) V DD = 5.5V.9.8 V DD = 2.5V V CM = V DD -.5V Ambient Temperature ( C) FIGURE 2-14: Supply Voltage. Quiescent Current vs. FIGURE 2-17: Temperature. Quiescent Current vs. Output Short Circuit Current (ma) C +85 C +25 C -4 C Supply Voltage (V) Open-Loop Gain (db) Phase Gain k 1k 1k 1M 1M 1M 1 1 Frequency (Hz) Open-Loop Phase ( ) FIGURE 2-15: vs. Supply Voltage. Output Short-Circuit Current FIGURE 2-18: Frequency. Open-Loop Gain, Phase vs. 29 Microchip Technology Inc. DS21685D-page 9

10 1.E+2 1.E+3 1.E+4 1.E+5 MCP621/1R/2/3/4 Note: Unless otherwise indicated, T A =+25 C, V DD = +2.5V to +5.5V, V SS =GND, V CM =V DD /2, V OUT V DD /2, R L =1kΩ to V DD /2 and C L = 6 pf. DC Open-Loop Gain (db) 13 V DD = 5.5V V DD = 2.5V k 1k 1k Load Resistance (Ω) DC Open-Loop Gain (db) V DD = 2.5V V DD = 5.5V Ambient Temperature ( C) FIGURE 2-19: Load Resistance. DC Open-Loop Gain vs. FIGURE 2-22: Temperature. DC Open-Loop Gain vs. DC Open-Loop Gain (db) V CM = V DD /2 V DD = 5.5V V DD = 2.5V Output Voltage Headroom (V); V DD - V OH or V OL - V SS Gain Bandwidth Product (MHz) Gain Bandwidth Product V DD = 5.V Phase Margin, G = Common Mode Input Voltage (V) Phase Margin, G = +1 ( ) FIGURE 2-2: Small Signal DC Open-Loop Gain vs. Output Voltage Headroom. FIGURE 2-23: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage. Gain Bandwidth Product (MHz) GBWP, V DD = 5.5V GBWP, V DD = 2.5V PM, V DD = 2.5V PM, V DD = 5.5V Ambient Temperature ( C) FIGURE 2-21: Gain Bandwidth Product, Phase Margin vs. Temperature. Phase Margin, G = +1 ( ) Gain Bandwidth Product (MHz) Gain Bandwidth Product V DD = 5.V V CM = V DD /2 Phase Margin, G = Output Voltage (V) 15 FIGURE 2-24: Gain Bandwidth Product, Phase Margin vs. Output Voltage Phase Margin, G = +1 ( ) DS21685D-page 1 29 Microchip Technology Inc.

11 1.E+4 1.E+5 1.E+6 1.E+7 1.E+3 1.E+4 1.E+5 1.E+6 MCP621/1R/2/3/4 Note: Unless otherwise indicated, T A =+25 C, V DD = +2.5V to +5.5V, V SS =GND, V CM =V DD /2, V OUT V DD /2, R L =1kΩ to V DD /2 and C L = 6 pf. Slew Rate (V/µs) Falling, V DD = 5.5V Rising, V DD = 5.5V Falling, V DD = 2.5V Rising, V DD = 2.5V Ambient Temperature ( C) Maximum Output Voltage Swing (V P-P ) 1 1 V DD = 5.5V V DD = 2.5V.1 1k 1k 1M 1M Frequency (Hz) FIGURE 2-25: Slew Rate vs. Temperature. FIGURE 2-28: Maximum Output Voltage Swing vs. Frequency. THD+N (%).1%.1%.1%.1% G = +1 V/V G = +1 V/V G = +1 V/V f = 1 khz BW Meas = 22 khz V DD = 5.V Output Voltage (V P-P ) THD+N (%).1%.1%.1%.1% G = +1 V/V G = +1 V/V G = +1 V/V f = 2 khz BW Meas = 8 khz V DD = 5.V Output Voltage (V P-P ) FIGURE 2-26: Total Harmonic Distortion plus Noise vs. Output Voltage with f = 1 khz. FIGURE 2-29: Total Harmonic Distortion plus Noise vs. Output Voltage with f = 2 khz. Input, Output Voltage (V) V IN V OUT V DD = 5.V G = +2 V/V Time (1 µs/div) Channel to Channel Separation (db) G = +1 V/V 15 1k 1k 1k Frequency (Hz) 1M FIGURE 2-27: The MCP621/1R/2/3/4 family shows no phase reversal under overdrive. FIGURE 2-3: Channel-to-Channel Separation vs. Frequency (MCP622 and MCP624 only). 29 Microchip Technology Inc. DS21685D-page 11

12 6.E-2 5.E-2 4.E-2 3.E-2 2.E-2 1.E-2.E+ -1.E-2-2.E-2-3.E-2-4.E-2-5.E-2-6.E-2.E+ 2.E-7 4.E-7 6.E-7 8.E-7 1.E-6 1.E-6 1.E-6 2.E-6 2.E-6 2.E-6.E+ 5.E-7 1.E-6 2.E-6 2.E-6 3.E-6 3.E-6 4.E-6 4.E-6 5.E-6 5.E-6 6.E-2 5.E-2 4.E-2 3.E-2 2.E-2 1.E-2.E+ -1.E-2-2.E-2-3.E-2-4.E-2-5.E-2-6.E-2.E+ 5.E-7 1.E-6 2.E-6 2.E-6 3.E-6 3.E-6 4.E-6 4.E-6 5.E-6 5.E-6 MCP621/1R/2/3/4 Note: Unless otherwise indicated, T A =+25 C, V DD = +2.5V to +5.5V, V SS =GND, V CM =V DD /2, V OUT V DD /2, R L =1kΩ to V DD /2 and C L = 6 pf. Output Voltage Headroom; V DD -V OH or V OL -V SS (mv) 1, 1 1 V OL - V SS V DD - V OH Output Current Magnitude (ma) Output Voltage Headroom V DD -V OH or V OL -V SS (mv) 1 9 V OL - V SS V 5 DD - V OH Ambient Temperature ( C) FIGURE 2-31: vs. Output Current. Output Voltage Headroom FIGURE 2-34: vs. Temperature. Output Voltage Headroom Output Voltage (1 mv/div) G = +1 V/V Output Voltage (1 mv/div) G = -1 V/V R F = 1 kω Time (2 ns/div).e+ 2.E-7 4.E-7 6.E-7 8.E-7 1.E-6 1.E-6 1.E-6 2.E-6 2.E-6 2.E-6 Time (2 ns/div) FIGURE 2-32: Pulse Response. Small-Signal Non-inverting FIGURE 2-35: Response. Small-Signal Inverting Pulse Output Voltage (V) Time (5 ns/div) G = +1 V/V Output Voltage (V) G = -1 V/V R F = 1 kω Time (5 ns/div) FIGURE 2-33: Pulse Response. Large-Signal Non-inverting FIGURE 2-36: Response. Large-Signal Inverting Pulse DS21685D-page Microchip Technology Inc.

13 .E+ 5.E-6 1.E-5 1.5E-5 2.E-5 2.5E-5 3.E-5 3.5E-5 MCP621/1R/2/3/4 Note: Unless otherwise indicated, T A =+25 C, V DD = +2.5V to +5.5V, V SS =GND, V CM =V DD /2, V OUT V DD /2, R L =1kΩ to V DD /2 and C L = 6 pf. V REF Accuracy; V REF V DD /2 (mv) Power Supply Voltage (V) V REF Accuracy; V REF V DD /2 (mv) 5 Representative Part V DD = 5.5V 1 V -1 DD = 2.5V Ambient Temperature ( C) FIGURE 2-37: V REF Accuracy vs. Supply Voltage (MCP621 and MCP623 only). FIGURE 2-4: V REF Accuracy vs. Temperature (MCP621 and MCP623 only). Quiescent Current (ma/amplifier) Op Amp turns on here CS swept high to low V DD = 2.5V G = +1 V/V V IN = 1.25V Op Amp shuts off here Hysteresis CS swept low to high Chip Select Voltage (V) FIGURE 2-38: Chip Select (CS) Hysteresis (MCP623 only) with V DD = 2.5V. Quiescent Current (ma/amplifier) 1.6 Op Amp Op Amp 1.4 turns on here shuts off here Hysteresis CS swept.8 high to low.6 CS swept low to high V.4 DD = 5.5V G = +1 V/V.2 V IN = 2.75V Chip Select Voltage (V) FIGURE 2-41: Chip Select (CS) Hysteresis (MCP623 only) with V DD = 5.5V. Chip Select Voltage, Output Voltage (V) Output on CS Voltage V OUT Output High-Z Time (5 µs/div) V DD = 5.V G = +1 V/V V IN = V SS Output on Input Current Magnitude (A) 1.E-2 1m 1.E-3 1m 1.E-4 1µ 1.E-5 1µ 1.E-6 1µ 1.E-7 1n 1.E-8 1n +125 C 1.E-9 1n +85 C 1.E-1 1p +25 C 1.E-11 1p -4 C 1.E-12 1p Input Voltage (V) FIGURE 2-39: Chip Select (CS) to Amplifier Output Response Time (MCP623 only). FIGURE 2-42: Measured Input Current vs. Input Voltage (below V SS ). 29 Microchip Technology Inc. DS21685D-page 13

14 NOTES: DS21685D-page Microchip Technology Inc.

15 3. PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE MCP621 MCP621R MCP622 MCP623 MCP624 Symbol Description PDIP, SOIC, MSOP, TSSOP (Note 1) SOT-23-5 SOT-23-5 (Note 2) PDIP, SOIC, TSSOP PDIP, SOIC, TSSOP PDIP, SOIC, TSSOP V OUT,V OUTA Analog Output (op amp A) V IN, V INA Inverting Input (op amp A) V IN +, V INA + Non-inverting Input (op amp A) V DD Positive Power Supply 5 5 V INB + Non-inverting Input (op amp B) 6 6 V INB Inverting Input (op amp B) 7 7 V OUTB Analog Output (op amp B) 8 V OUTC Analog Output (op amp C) 9 V INC Inverting Input (op amp C) 1 V INC + Non-inverting Input (op amp C) V SS Negative Power Supply 12 V IND + Non-inverting Input (op amp D) 13 V IND Inverting Input (op amp D) 14 V OUTD Analog Output (op amp D) 5 5 V REF Reference Voltage 8 CS Chip Select 1, 8 1 NC No Internal Connection Note 1: The MCP621 in the 8-pin TSSOP package is only available for I-temp (Industrial Temperature) parts. 2: The MCP621R is only available in the 5-pin SOT-23 package, and for E-temp (Extended Temperature) parts. 3.1 Analog Outputs The op amp output pins are low-impedance voltage sources. 3.2 Analog Inputs The op amp non-inverting and inverting inputs are highimpedance CMOS inputs with low bias currents. 3.3 Reference Voltage (V REF, ) MCP621 and MCP623 Mid-supply reference voltage provided by the single op amps (except in SOT-23-5 package). This is an unbuffered, resistor voltage divider internal to the part. 3.4 Chip Select Digital Input (CS) This is a CMOS, Schmitt-triggered input that places the part into a low power mode of operation. 3.5 Power Supply (V SS and V DD ) The positive power supply pin (V DD ) is 2.5V to 6.V higher than the negative power supply pin (V SS ). For normal operation, the other pins are at voltages between V SS and V DD. Typically, these parts are used in a single (positive) supply configuration. In this case, V SS is connected to ground and V DD is connected to the supply. V DD will need a bypass capacitor. 29 Microchip Technology Inc. DS21685D-page 15

16 NOTES: DS21685D-page Microchip Technology Inc.

17 4. APPLICATIONS INFORMATION The MCP621/1R/2/3/4 family of operational amplifiers are fabricated on Microchip s state-of-the-art CMOS process. They are unity-gain stable and suitable for a wide range of general-purpose applications. V 1 D 1 D 2 V DD 4.1 Rail-to-Rail Input R 1 MCP62X PHASE REVERSAL The MCP621/1R/2/3/4 op amp is designed to prevent phase reversal when the input pins exceed the supply voltages. Figure 2-42 shows the input voltage exceeding the supply voltage without any phase reversal INPUT VOLTAGE AND CURRENT LIMITS The ESD protection on the inputs can be depicted as shown in Figure 4-1. This structure was chosen to protect the input transistors, and to minimize input bias current (I B ). The input ESD diodes clamp the inputs when they try to go more than one diode drop below V SS. They also clamp any voltages that go too far above V DD ; their breakdown voltage is high enough to allow normal operation, and low enough to bypass quick ESD events within the specified limits. V DD V IN + V SS Bond Pad Bond Pad Bond Pad FIGURE 4-1: Structures. Input Stage Bond Pad V IN Simplified Analog Input ESD In order to prevent damage and/or improper operation of these op amps, the circuit they are in must limit the currents and voltages at the V IN + and V IN pins (see Absolute Maximum Ratings at the beginning of Section 1. Electrical Characteristics ). Figure 4-2 shows the recommended approach to protecting these inputs. The internal ESD diodes prevent the input pins (V IN + and V IN ) from going too far below ground, and the resistors R 1 and R 2 limit the possible current drawn out of the input pins. Diodes D 1 and D 2 prevent the input pins (V IN + and V IN ) from going too far above V DD, and dump any currents onto V DD. When implemented as shown, resistors R 1 and R 2 also limit the current through D 1 and D 2. V 2 R 2 FIGURE 4-2: Inputs. R 3 R 1 > V SS (minimum expected V 1 ) 2mA R 2 > V SS (minimum expected V 2 ) 2mA Protecting the Analog It is also possible to connect the diodes to the left of resistors R 1 and R 2. In this case, current through the diodes D 1 and D 2 needs to be limited by some other mechanism. The resistors then serve as in-rush current limiters; the DC current into the input pins (V IN + and V IN ) should be very small. A significant amount of current can flow out of the inputs when the common mode voltage (V CM ) is below ground (V SS ); see Figure Applications that are high impedance may need to limit the useable voltage range NORMAL OPERATION The input stage of the MCP621/1R/2/3/4 op amps use two differential CMOS input stages in parallel. One operates at low common mode input voltage (V CM ), while the other operates at high V CM. WIth this topology, the device operates with Vcm up to.3v above V DD and.3v below V SS. 4.2 Rail-to-Rail Output The Maximum Output Voltage Swing is the maximum swing possible under a particular output load. According to the specification table, the output can reach within 2 mv of either supply rail when R L =1kΩ. See Figure 2-31 and Figure 2-34 for more information concerning typical performance. 4.3 Capacitive Loads Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop s phase margin decreases, and the closed loop bandwidth is reduced. This produces gain-peaking in the frequency response, with overshoot and ringing in the step response. 29 Microchip Technology Inc. DS21685D-page 17

18 When driving large capacitive loads with these op amps (e.g., > 6 pf when G = +1), a small series resistor at the output (R ISO in Figure 4-3) improves the feedback loop s phase margin (stability) by making the load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. 1 V/V (unity gain). C G also reduces the phase margin of the feedback loop for both non-inverting and inverting gains. V IN V OUT V IN MCP62X R ISO V OUT C G R G R F C L FIGURE 4-3: Output Resistor R ISO Stabilizes Large Capacitive Loads. Figure 4-4 gives recommended R ISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (C L /G N ), where G N is the circuit s noise gain. For non-inverting gains, G N and the Signal Gain are equal. For inverting gains, G N is 1+ Signal Gain (e.g., -1 V/V gives G N = +2 V/V). Recommended R ISO (Ω) 1, 1 1 G N , 1, Normalized Capacitance; C L /G N (pf) FIGURE 4-4: Recommended R ISO values for capacitive loads. After selecting R ISO for your circuit, double-check the resulting frequency response peaking and step response overshoot. Modify R ISO s value until the response is reasonable. Evaluation on the bench and simulations with the MCP621/1R/2/3/4 Spice macro model are helpful. 4.4 Gain Peaking Figure 2-35 and Figure 2-36 use R F =1kΩ to avoid (frequency response) gain peaking and (step response) overshoot. The capacitance to ground at the inverting input (C G ) is the op amp s common mode input capacitance plus board parasitic capacitance. C G is in parallel with R G, which causes an increase in gain at high frequencies for non-inverting gains greater than FIGURE 4-5: Non-inverting Gain Circuit with Parasitic Capacitance. The largest value of R F in Figure 4-5 that should be used is a function of noise gain (see G N in Section 4.3 Capacitive Loads ) and C G. Figure 4-6 shows results for various conditions. Other compensation techniques may be used, but they tend to be more complicated to the design. Maximum R F (Ω) 1.E+5 1k 1.E+4 1k 1.E+3 1k 1.E+2 1 G N > +1 V/V C G = 7 pf C G = 2 pf 1 1 Noise Gain; G N (V/V) FIGURE 4-6: Non-inverting gain circuit with parasitic capacitance. 4.5 MCP623 Chip Select (CS) C G = 5 pf C G = 1 pf The MCP623 is a single amplifier with chip select (CS). When CS is pulled high, the supply current drops to 1 na (typical) and flows through the CS pin to V SS. When this happens, the amplifier output is put into a high-impedance state. By pulling CS low, the amplifier is enabled. The CS pin has an internal 5 MΩ (typical) pulldown resistor connected to V SS, so it will go low if the CS pin is left floating. Figure 1-1 and Figure 2-39 show the output voltage and supply current response to a CS pulse. DS21685D-page Microchip Technology Inc.

19 4.6 MCP621 and MCP623 Reference Voltage The single op amps (MCP621 and MCP623), not in the SOT-23-5 package, have an internal mid-supply reference voltage connected to the V REF pin (see Figure 4-7). The MCP621 has CS internally tied to V SS, which always keeps the op amp on and always provides a mid-supply reference. With the MCP623, taking the CS pin high conserves power by shutting down both the op amp and the V REF circuitry. Taking the CS pin low turns on the op amp and V REF circuitry. V REF CS 5MΩ V DD V SS 5 kω 5 kω (CS tied internally to V SS for MCP621) FIGURE 4-7: Simplified internal V REF circuit (MCP621 and MCP623 only). See Figure 4-8 for a non-inverting gain circuit using the internal mid-supply reference. The DC-blocking capacitor (C B ) also reduces noise by coupling the op amp input to the source. V IN R G R F V OUT FIGURE 4-9: Inverting gain circuit using V REF (MCP621 and MCP623 only). If you don t need the mid-supply reference, leave the V REF pin open. 4.7 Supply Bypass With this family of operational amplifiers, the power supply pin (V DD for single supply) should have a local bypass capacitor (i.e.,.1 µf to.1 µf) within 2 mm for good, high-frequency performance. It also needs a bulk capacitor (i.e., 1 µf or larger) within 1 mm to provide large, slow currents. This bulk capacitor can be shared with nearby analog parts. 4.8 Unused Op Amps V REF C B An unused op amp in a quad package (MCP624) should be configured as shown in Figure 4-1. These circuits prevent the output from toggling and causing crosstalk. Circuits A sets the op amp at its minimum noise gain. The resistor divider produces any desired reference voltage within the output voltage range of the op amp; the op amp buffers that reference voltage. Circuit B uses the minimum number of components and operates as a comparator, but it may draw more current. R G R F ¼ MCP624 (A) ¼ MCP624 (B) V DD V DD C B V REF V OUT R 1 V DD V IN FIGURE 4-8: Non-inverting gain circuit using V REF (MCP621 and MCP623 only). To use the internal mid-supply reference for an inverting gain circuit, connect the V REF pin to the non-inverting input, as shown in Figure 4-9. The capacitor C B helps reduce power supply noise on the output. V R REF 2 R 2 V REF = V DD R 1 + R 2 FIGURE 4-1: Unused Op Amps. 29 Microchip Technology Inc. DS21685D-page 19

20 4.9 PCB Surface Leakage In applications where low input bias current is critical, PCB (printed circuit board) surface-leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1 12 Ω. A 5V difference would cause 5 pa of current to flow, which is greater than the MCP621/1R/2/3/4 family s bias current at +25 C (1 pa, typical). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. Figure 4-11 shows an example of this type of layout. FIGURE 4-11: Layout. Guard Ring V IN V IN + Example Guard Ring 1. Non-inverting Gain and Unity-Gain Buffer. a) Connect the guard ring to the inverting input pin (V IN ); this biases the guard ring to the common mode input voltage. b) Connect the non-inverting pin (V IN +) to the input with a wire that does not touch the PCB surface. 2. Inverting (Figure 4-11) and Transimpedance Gain Amplifiers (convert current to voltage, such as photo detectors). a) Connect the guard ring to the non-inverting input pin (V IN +). This biases the guard ring to the same reference voltage as the op amp s input (e.g., V DD /2 or ground). b) Connect the inverting pin (V IN ) to the input with a wire that does not touch the PCB surface. Separate digital from analog, low speed from high speed and low power from high power. This will reduce interference. Keep sensitive traces short and straight. Separating them from interfering components and traces. This is especially important for high-frequency (low rise-time) signals. Sometimes it helps to place guard traces next to victim traces. They should be on both sides of the victim trace, and as close as possible. Connect the guard trace to ground plane at both ends, and in the middle for long traces. Use coax cables (or low inductance wiring) to route signal and power to and from the PCB Typical Applications A/D CONVERTER DRIVER AND ANTI-ALIASING FILTER Figure 4-12 shows a third-order Butterworth filter that can be used as an A/D converter driver. It has a bandwidth of 2 khz and a reasonable step response. It will work well for conversion rates of 8 ksps and greater (it has 29 db attenuation at 6 khz) kω 1.2 nf 1. nf 14.7 kω 33.2 kω 1 pf MCP62X FIGURE 4-12: A/D Converter Driver and Anti-aliasing Filter with a 2 khz Cutoff Frequency. This filter can easily be adjusted to another bandwidth by multiplying all capacitors by the same factor. Alternatively, the resistors can all be scaled by another common factor to adjust the bandwidth. 4.1 High Speed PCB Layout Due to their speed capabilities, a little extra care in the PCB (Printed Circuit Board) layout can make a significant difference in the performance of these op amps. Good PC board layout techniques will help you achieve the performance shown in Section 1. Electrical Characteristics and Section 2. Typical Performance Curves, while also helping you minimize EMC (Electro-Magnetic Compatibility) issues. Use a solid ground plane and connect the bypass local capacitor(s) to this plane with minimal length traces. This cuts down inductive and capacitive crosstalk. DS21685D-page 2 29 Microchip Technology Inc.

21 OPTICAL DETECTOR AMPLIFIER Figure 4-13 shows the MCP621 op amp used as a transimpedance amplifier in a photo detector circuit. The photo detector looks like a capacitive current source, so the 1 kω resistor gains the input signal to a reasonable level. The 5.6 pf capacitor stabilizes this circuit and produces a flat frequency response with a bandwidth of 37 khz. Photo Detector 5.6 pf 1 kω 1 pf MCP621 V DD /2 FIGURE 4-13: Transimpedance Amplifier for an Optical Detector. 29 Microchip Technology Inc. DS21685D-page 21

22 NOTES: DS21685D-page Microchip Technology Inc.

23 5. DESIGN AIDS Microchip provides the basic design tools needed for the MCP621/1R/2/3/4 family of op amps. 5.1 SPICE Macro Model The latest SPICE macro model available for the MCP621/1R/2/3/4 op amps is on Microchip s web site at This model is intended as an initial design tool that works well in the op amp s linear region of operation at room temperature. Within the macro model file is information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 5.2 FilterLab Software Microchip s FilterLab software is an innovative software tool that simplifies analog active filter (using op amps) design. Available at no cost from the Microchip web site at the FilterLab design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance. 5.3 Mindi Circuit Designer & Simulator Microchip s Mindi Circuit Designer & Simulator aids in the design of various circuits useful for active filter, amplifier and power-management applications. It is a free online circuit designer & simulator available from the Microchip web site at This interactive circuit designer & simulator enables designers to quickly generate circuit diagrams, simulate circuits. Circuits developed using the Mindi Circuit Designer & Simulator can be downloaded to a personal computer or workstation. 5.4 Microchip Advanced Part Selector (MAPS) MAPS is a software tool that helps semiconductor professionals efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip web site at maps, the MAPS is an overall selection tool for Microchip s product portfolio that includes Analog, Memory, MCUs and DSCs. Using this tool you can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. Helpful links are also provided for Data sheets, Purchase, and Sampling of Microchip parts. 5.5 Analog Demonstration and Evaluation Boards Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to help you achieve faster time to market. For a complete listing of these boards and their corresponding user s guides and technical information, visit the Microchip web site at Some boards that are especially useful are: MCP6XXX Amplifier Evaluation Board 1 MCP6XXX Amplifier Evaluation Board 2 MCP6XXX Amplifier Evaluation Board 3 MCP6XXX Amplifier Evaluation Board 4 Active Filter Demo Board Kit 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board, P/N: SOIC8EV 14-Pin SOIC/TSSOP/DIP Evaluation Board, P/N: SOIC14EV 5.6 Application Notes The following Microchip Application Notes are available on the Microchip web site at com/ appnotes and are recommended as supplemental reference resources. ADN3: Select the Right Operational Amplifier for your Filtering Circuits, DS21821 AN722: Operational Amplifier Topologies and DC Specifications, DS722 AN723: Operational Amplifier AC Specifications and Applications, DS723 AN884: Driving Capacitive Loads With Op Amps, DS884 AN99: Analog Sensor Conditioning Circuits An Overview, DS99 AN1177: Op Amp Precision Design: DC Errors, DS1177 AN1228: Op Amp Precision Design: Random Noise, DS1228 These application notes and others are listed in the design guide: Signal Chain Design Guide, DS Microchip Technology Inc. DS21685D-page 23

24 NOTES: DS21685D-page Microchip Technology Inc.

25 6. PACKAGING INFORMATION 6.1 Package Marking Information 5-Lead SOT-23 (MCP621/MCP621R) Example: (E-temp) XXNN Device E-Temp Code MCP621 EYNN MCP621R EZNN Note: Applies to 5-Lead SOT-23 EY25 8-Lead PDIP (3 mil) XXXXXXXX XXXXXNNN YYWW Example: MCP621 I/P MCP621 OR E/P^^256 e Lead SOIC (15 mil) Example: XXXXXXXX XXXXYYWW NNN MCP621 I/SN MCP621E OR SN^^93 e Lead MSOP XXXXXX YWWNNN Example: 621E Lead TSSOP XXXX YYWW NNN Example: 621 E Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week 1 ) NNN e3 Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 29 Microchip Technology Inc. DS21685D-page 25

26 Package Marking Information (Continued) 14-Lead PDIP (3 mil) (MCP624) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN MCP624-I/P XXXXXXXXXXXXXX OR MCP624 E/P^^ e Lead SOIC (15 mil) (MCP624) Example: XXXXXXXXXX XXXXXXXXXX YYWWNNN MCP624ISL XXXXXXXXXX OR MCP624 E/SL^^ e Lead TSSOP (MCP624) Example: XXXXXX YYWW NNN 624E DS21685D-page Microchip Technology Inc.

27 N b E E e e1 D A A2 c φ A1 L L1 29 Microchip Technology Inc. DS21685D-page 27

28 N NOTE 1 E D E A A2 A1 L c b1 b e eb DS21685D-page Microchip Technology Inc.

29 D N e E E1 NOTE b h h α A A2 φ c A1 L L1 β 29 Microchip Technology Inc. DS21685D-page 29

30 DS21685D-page 3 29 Microchip Technology Inc.

31 D N E1 E NOTE e b A A2 c φ A1 L1 L 29 Microchip Technology Inc. DS21685D-page 31

32 N NOTE 1 E D E A A2 L c A1 b1 b e eb DS21685D-page Microchip Technology Inc.

33 D N E E1 NOTE b e h h α A A2 φ c A1 L L1 β 29 Microchip Technology Inc. DS21685D-page 33

34 DS21685D-page Microchip Technology Inc.

35 D N E1 E NOTE b e A A2 c φ A1 L1 L 29 Microchip Technology Inc. DS21685D-page 35

36 NOTES: DS21685D-page Microchip Technology Inc.

37 APPENDIX A: Revision D (February 29) REVISION HISTORY The following is the list of modifications: 1. Changed all references to 6.V back to 5.5V throughout document. 2. Design Aids: Name change for Mindi Simulation Tool. 3. Section 1. Electrical Characteristics, DC Electrical Specifications: Corrected Maximum Output Voltage Swing condition from.9v Input Overdrive to.5v Input Overdrive. 4. Section 1. Electrical Characteristics, AC Electrical Specifications: Changed Phase Margin condition from G = +1 to G= +1 V/V. 5. Section 1. Electrical Characteristics, AC Electrical Specifications: Changed Settling Time,.2% condition from G = +1 to G = +1 V/V. 6. Section 1. Electrical Characteristics : Added Section 1.1 Test Circuits. 7. Section 5. Design AIDS : Name change for Mindi Simulation Tool. Added new boards to Section 5.5 Analog Demonstration and Evaluation Boards and new application notes to Section 5.6 Application Notes. 8. Updates Appendix A: Revision History Revision B (November 23) Second Release of this Document Revision A (November 21) Original Release of this Document. Revision C (March 26) The following is the list of modifications: 1. Added SOT-23-5 package option for single op amps MCP621 and MCP621R (E-temp only). 2. Added MSOP-8 package option for E-temp single op amp (MCP621). 3. Corrected package drawing on front page for dual op amp (MCP622). 4. Clarified spec conditions (I SC, PM and THD+N) in Section 2. Typical Performance Curves. 5. Added Section 3. Pin Descriptions. 6. Updated Section 4. Applications information for THD+N, unused op amps, and gain peaking discussions. 7. Corrected and updated package marking information in Section 6. Packaging Information. 8. Added Appendix A: Revision History. 29 Microchip Technology Inc. DS21685D-page 37

38 NOTES: DS21685D-page Microchip Technology Inc.

39 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Device Temperature Range Package Device: MCP621 Single Op Amp MCP621T Single Op Amp (Tape and Reel for SOT-23, SOIC, TSSOP, MSOP) MCP621R Single Op Amp MCP621RT Single Op Amp (Tape and Reel for SOT-23) MCP622 Dual Op Amp MCP622T Dual Op Amp (Tape and Reel for SOIC and TSSOP) MCP623 Single Op Amp w/ CS MCP623T Single Op Amp w/ CS (Tape and Reel for SOIC and TSSOP) MCP624 Quad Op Amp MCP624T Quad Op Amp (Tape and Reel for SOIC and TSSOP) Temperature Range: I = -4 C to +85 C E = -4 C to +125 C Examples: a) MCP621T-E/OT: Tape and Reel, Extended temperature, 5LD SOT-23. b) MCP621-E/P: Extended temperature, 8LD PDIP. c) MCP621-E/SN: Extended temperature, 8LD SOIC. a) MCP621RT-E/OT:Tape and Reel, Extended temperature, 5LD SOT-23. a) MCP622-I/P: Industrial temperature, 8LD PDIP. b) MCP622-E/P: Extended temperature, 8LD PDIP. c) MCP622T-E/ST: Tape and Reel, Extended temperature, 8LD TSSOP. a) MCP623-I/P: Industrial temperature, 8LD PDIP. b) MCP623-E/P: Extended temperature, 8LD PDIP. c) MCP623-E/SN: Extended temperature, 8LD SOIC. Package: OT = Plastic Small Outline Transistor (SOT-23), 5-lead (MCP621, E-Temp; MCP621R, E-Temp) MS = Plastic MSOP, 8-lead (MCP621, E-Temp) P = Plastic DIP (3 mil Body), 8-lead, 14-lead SN = Plastic SOIC (15mil Body), 8-lead SL = Plastic SOIC (15 mil Body), 14-lead ST = Plastic TSSOP, 8-lead (MCP621,I-Temp; MCP622, I-Temp, E-Temp; MCP623, I-Temp, E-Temp;) ST = Plastic TSSOP, 14-lead a) MCP624-I/SL: Industrial temperature, 14LD SOIC. b) MCP624-E/SL: Extended temperature, 14LD SOIC. c) MCP624T-E/ST: Tape and Reel, Extended temperature, 14LD TSSOP. 29 Microchip Technology Inc. DS21685D-page 39

40 NOTES: DS21685D-page 4 29 Microchip Technology Inc.

41 Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as unbreakable. Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dspic, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfpic, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dspicdem, dspicdem.net, dspicworks, dsspeak, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mtouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC 32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rflab, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. 29, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:22 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company s quality system processes and procedures are for its PIC MCUs and dspic DSCs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip s quality system for the design and manufacture of development systems is ISO 91:2 certified. 29 Microchip Technology Inc. DS21685D-page 41

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