AN884. Driving Capacitive Loads With Op Amps INTRODUCTION LINEAR RESPONSE. Simplified Op Amp AC Model. Overview. Purpose OP AMP MODEL EQUATION 1:

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1 Driving Capacitive Loads With Op Amps AN884 Author: INTRODUCTION Overview Operational amplifiers (op amps) that drive large capacitive loads may produce undesired results. This application note discusses these potential problems. It also offers simple, practical solutions to each of these problems. The circuit descriptions and mathematics are kept to a minimum, with emphasis on understanding rather than completeness. Simple models of op amp behavior help achieve these goals. Simple equations are included to help connect circuit design to overall circuit behavior. Simple examples illustrate the concepts discussed. They give concrete results that can be used to better understand the theory. They are also practical to help develop a feel for real world designs. Purpose Kumen Blake Microchip Technology Inc. This application note is for circuit designers using op amps that drive capacitive loads. It assumes only a basic understanding of circuit analysis. This application note has the goal of helping circuit designers quickly and effectively resolve capacitive loading issues in op amp circuits. It focuses on building a fundamental understanding of why problems occur, and how to resolve these problems. LINEAR RESPONSE Capacitive loads affect an op amp s linear response. They change the transfer function, which affects AC response and step response. If the capacitance is large enough, it becomes necessary to compensate the op amp circuit to keep it stable, and to avoid AC response peaking and step response overshoot and ringing. An op amp s linear response is also critical in understanding how it interacts with sampling capacitors. These sampling capacitors present a nonlinear, reactive load to an op amp. For instance, many A/D converters (e.g., low frequency SAR and Delta- Sigma) have sampling capacitors at their inputs. Simplified Op Amp AC Model In order to understand how capacitive loads affect op amps, we must look at the op amp s output impedance and bandwidth. The feedback network modifies the op amp s behavior; its effects are included in an equivalent circuit model. OP AMP MODEL Figure shows a simplified AC model of a voltage feedback op amp. The open-loop gain is represented by the dependent source with gain A OL (s), where s=jω =jπf. The output stage is represented by the resistor R O (open-loop output resistance). P M FIGURE : V E Op Amp AC Model. We will include gain bandwidth product (f GBP ), the open-loop gain s second pole (f P ) in our open-loop gain (A OL (s)) model. Low frequency effects are left out for simplicity. f P models the open-loop gain s reduced phase (< -90 ) at high frequencies due to internal parasitics (see Section B. Estimating f P for more information). EQUATION : R O V E A OL (s) ω GBP A OL ( s) s ( + s ω P ) 008 Microchip Technology Inc. DS00884B-page

2 CIRCUIT MODEL Figure shows the op amp in a non-inverting gain, and Figure 3 in an inverting gain. These circuits cover the majority of applications. FIGURE : FIGURE 3: R G R G MCP6XXX Non-inverting Gain Circuit. Inverting Gain Circuit. These circuits have different DC gains (K) and a DC noise gain (G N ). G N can be defined to be the gain from the input pins to the output set by the feedback network. It is also useful in describing the stability of op amp circuits. These gains are: R F MCP6XXX R F Figure 4 shows Z OUT s behavior. At low frequencies, it is constant because the open-loop gain is constant. As the open-loop gain decreases with frequency, Z OUT increases. Past A, the feedback loop has no more effect, and Z OUT stays at R O. The peaking at G N =+ is caused by the reduced phase margin due to f P. Output Impedance ( ) MCP E- 0..E+.E+ 0.E+ 00.E+ k.e+ 0k 00k.E+.E+ M.E+ 0M Frequency 0 03 (Hz) FIGURE 4: MCP67 s Closed-Loop Output Impedance vs. Frequency. Figure 5 shows a simple AC model that approximates this behavior. The amplifier models the no load gain and bandwidth, while the inductor and resistor model the output impedance vs. frequency. MCP6XXX G N = + G N = +0 G N = +00 EQUATION : K = + R F R G, non-inverting K = R F R G, inverting G N = + R F R G K +s/ω 3dBA L OUT R OUT Z OUT Note: Some applications do not have constant G N due to reactive elements (e.g., capacitors). More sophisticated design techniques, or simulations, are required in that case. The op amp feedback loop (R F and R G ) causes its closed-loop behavior to be different from its open-loop behavior. Gain bandwidth product (f GBP ) and openloop output impedance (R O ) are modified by G N to give closed-loop bandwidth (A ) and output impedance (Z OUT ). We can analyze the circuits in Figure, Figure and Figure 3 to give: FIGURE 5: Model. Simplified Op Amp AC R OUT is larger than R O because it includes f P s phase shift effects, which are especially noticeable at low gain (G N ). The equations for L OUT and R OUT are: EQUATION 4: L OUT = R O ( πa ) R OUT R O max( A f P, /) EQUATION 3: A f GBP G N Z OUT = R O A OL ( s) G N DS00884B-page 008 Microchip Technology Inc.

3 Uncompensated AC Behavior This section shows the effect load capacitance has on op amp gain circuits. These results help distinguish between circuit that need compensation and those that do not. THEORY Figure 6 shows a non-inverting gain circuit with an uncompensated capacitive load. The inverting gain circuit is a simple modification of this circuit. For small capacitive loads and high noise gains (typically /G N < 00 pf), this circuit works quite well. FIGURE 6: Load. R G Uncompensated Capacitive The feedback network (R F and R G ) also presents a load to the op amp output. This load (R FL ) depends on whether the gain is non-inverting or inverting: EQUATION 5: Replacing the op amp in Figure 6 with the simplified op amp AC model gives an LC resonant circuit (L OUT and ). When becomes large enough, R OUT R FL does a poor job of dampening the LC resonance, which causes peaking and step response overshoot. This happens because the feedback loop s phase margin is reduced by both f P and. A simplified transfer function is: EQUATION 6: MCP6XXX R F R FL = R F + R G, non-inverting gain R FL = R F, inverting gain K s ω P s ω P G N = + R F R G K = G N, non-inverting K = GN, inverting ω P = πf P = L OUT We can now use the equations in Appendix A: nd Order System Response Model to estimate the overall bandwidth ( ), frequency response peaking (H PK /G N ), and step response overshoot (x max ). Note that is not the same as the op amp s no load, -3dB bandwidth (A ). MCP67 EXAMPLE The equations above were used to generate the curves in Figure 7 and Figure 8 for Microchip s MCP67 op amp. The parameters used are from TABLE B-: Estimates of Typical Microchip Op Amp Parameters. Gain (db) MCP67 G N = + = 0 nf = nf = 00 pf = 0 pf -0 0k 00k M 0M 00M.E+04.E+05.E+06.E+07.E+08 Frequency (Hz) FIGURE 7: Estimate of MCP67 s AC Response with G N = +. Gain (db) = 00 nf = 0 nf = nf = 00 pf MCP67 G N = k.E+04 00k.E+05 M.E+06 0M.E+07 00M.E+08 Frequency (Hz) FIGURE 8: Estimate of MCP67 s AC Response with G N = +0. The peaking (H PK /G N ) should be near 0 db for the best overall performance. Keeping the peaking below 3 db usually gives enough design margin for changes in op amp, resistor, and capacitor parameters over temperature and process. However, the performance is degraded. = ( R OUT R FL ) L OUT 008 Microchip Technology Inc. DS00884B-page 3

4 For this example, our formulas give the estimated results shown in Table. As increases, and gain decreases, there is more peaking. TABLE : G N (V/V) Circuit (F) RESPONSE ESTIMATES f P (Hz) ( ) Response (Hz) Series Resistor Compensation H PK /K (db) x max (%).0 0p 9.3M 0.3.3M p.9M M n 0.93M.3.4M n 0.9M M p 930k 0. k n 94k k n 93k. 39k n 9k k A series resistor (R ISO ) is inserted to reduce resonant peaking. It draws no extra DC current and does not affect DC gain accuracy when there is no load resistance. This compensation method only costs one resistor. THEORY Figure 9 shows the series resistor R ISO loading the resonant circuit at the op amp s output, reducing frequency response peaking. The inverting gain circuit is very similar. The transfer function now includes R ISO : EQUATION 7: K s s ω P We can now find a reasonable R ISO value. When =/, the response has the highest possible bandwidth without peaking, and the equations are in their simplest form: ω P G N = + R F R G K = G N, K GN non-inverting ω P = πf P = R L OUT ISO R OUT L ω OUT = P R ISO R OUT R FL EQUATION 8: R ISO = 0, C X C X R ISO = ( R OUT R FL ) C X = C X L OUT R OUT R FL = ( ) R FL , > C X MCP6XXX R ISO R G FIGURE 9: Load. R F Compensated Capacitive DS00884B-page Microchip Technology Inc.

5 MCP67 EXAMPLE These equations were used to compensate the MCP67 circuit in Figure 9. The results are shown in Figure 0 and Figure (compare to Figure 7 and Figure 8). Gain (db) MCP67 G N = + = 0 nf R ISO = 76.8 = nf R ISO = 3 = 00 pf R ISO = 87 = 0 pf R ISO = 0-0 0k 00k M 0M 00M.E+04.E+05.E+06.E+07.E+08 Frequency (Hz) FIGURE 0: Estimate of MCP67 s Compensated AC Response with G = +. Gain (db) MCP67 G N = +0 = 0 nf R ISO = 76.8 = 0 nf R ISO = 6 = nf R ISO = 0 = 00 pf R ISO = 0 0 0k.E+04 00k.E+05 M.E+06 0M.E+07 00M.E+08 Frequency (Hz) FIGURE : Estimate of MCP67 s Compensated AC Response with G = +0. Our formulas give the estimated results shown in Table. R ISO has limited the gain peaking. These results are much better than before (see Table ). TABLE : G N (V/V) Circuit (F) RESPONSE ESTIMATES (NOTE ) Figure shows the estimated R ISO values for the MCP67 (see Equation 8). The x-axis is normalized load capacitance ( /G N ) for ease of interpretation. FIGURE : MCP67. R ISO (Ω) f P (Hz) Response ( ) (Hz) Estimated R ISO for the x max (%).0 0p 0 9.3M 0.3.3M 0 00p 87.4M 0.7.4M 4 n M M 4 0n M M p 0 930k 0. k 0 n 0 94k k 4 0n 6 73k k 4 00n k 0.7 7k 4 Note : H PK /K = 0 db for all of these compensated examples.,000 k MCP67 Estimated R ISO ( ) 00 G N = + G N p 00p n 0n 00n.E-.E-0.E-09.E-08.E-07 Normalized Load Capacitance; /G N (F) 008 Microchip Technology Inc. DS00884B-page 5

6 Shunt Resistor Compensation A shunt resistor (R SH ) is placed on the output to reduce resonant peaking. A series capacitor (C SH ) can be included to prevent R SH from drawing extra DC current, which reduces DC gain accuracy. The cost of this implementation is one resistor and (usually) one capacitor. R SH and C SH together can be considered an R-C snubber circuit. THEORY Figure 9 shows the shunt resistor R SH loading the resonant circuit at the op amp s output, reducing frequency response peaking. C SH blocks DC, which overcomes this approach s limitations. The inverting gain circuit is very similar. R G FIGURE 3: Load. Compensated Capacitive The transfer function with R SH only (C SH is shorted) is: =/ gives a reasonable R SH value: EQUATION 0: MCP6XXX R F RSH C SH EQUATION 9: K s s ω P ω P C SH = short G N = + R F R G K = G N, non-inverting K = GN, inverting ω P = πf P = L OUT = ( R OUT R FL R SH ) L OUT To keep the design simple, calculate C SH so that it has minimal interaction with the resonant circuit: EQUATION : C SH = open, R SH = open 0 C SH , R ω P R SH < SH MCP67 EXAMPLE These equations were used to compensate the MCP67 circuits in Figure. The results are shown in Figure 4 and Figure 5 (compare to Figure 7 and Figure 8); C SH is not shown for convenience. Gain (db) FIGURE 4: Estimate of MCP67 s Compensated AC Response with G = +. Gain (db) k 00k M 0M 00M.E+04.E+05.E+06.E+07.E+08 Frequency (Hz) MCP67 G N = + MCP67 G N = +0 = 0 nf R SH = 43. = 0 nf R SH = 4. = 0 nf R SH = 8 = nf R SH = 74 = nf R SH = open = 00 pf R SH =.7 k = 0 pf R SH = open = 00 pf R SH = open 0 0k 00k M 0M 00M.E+04.E+05.E+06.E+07.E+08 Frequency (Hz) FIGURE 5: Estimate of MCP67 s Compensated AC Response with G = +0. G XX R SH = = C L L OUT R OUT R SH = open, G XX 0 C SH R FL G XX, G XX > 0 = short = DS00884B-page Microchip Technology Inc.

7 Our formulas give the estimated results in Table 3; they include C SH values at each design point. As can be seen, R SH has limited the gain peaking. These results are much better than before (see Table ). TABLE 3: G N (V/V) (F) Circuit RESPONSE ESTIMATES (NOTE ) The R SH and C SH values for the MCP67, estimated by Equation 0, are shown in Figure 6. It shows normalized load capacitance ( /G N ) and normalized shunt capacitance (C SN /G N ) for convenience. FIGURE 6: MCP67. R SH (Ω) C SH (F) f P (Hz) Response ( ) (Hz) Estimated R SH for the x max (%).0 0p open open 9.3M 0.3.3M 0 00p.7k 47p.9M 0.7.9M 4 n 74 0n 0.93M M 4 0n 4. 0n 0.9M M p open open 930k 0. k 0 n open open 94k k 4 0n 8 00n 93k k 4 00n 43..µ 9k 0.7 9k 4 Note : H PK /K = 0 db for all of these compensated examples. Estimated R SH ( ) 00,000 00k 0,000 0k k, R SH : G N = + G N + MCP67 0µ.E-05 µ.e-06 00n.E-07 0n.E-08 C SH /G N : 0 n G N = +.E-09 G N + 00p.E-0 0p 00p n 0n 00n.E-.E-0.E-09.E-08.E-07 Normalized Load Capacitance; /G N (F) Estimated C SH /G N (F) DRIVING A/D CONVERTERS Microchip s SAR and Delta-Sigma A/D converters (ADCs) use sampling capacitors at their inputs. Near DC, these switched capacitors interact with other internal capacitors as if they were large resistors. At high frequencies, their behavior is more complicated. The ADCs input impedance, as seen by other components in a circuit, is non-linear; it has Fourier components to very high frequencies. This section shows different ways to analyze this phenomenon. It also gives simple design fixes. Incorrect DC Analysis An A/D converter input is usually described (modeled) as an input resistance. Unlike resistors, switched capacitors do not react to low frequency (i.e., DC) impedances; they react to high frequency impedances seen at the input. Note: An op amp that drives an ADC with a sampling capacitor input may not behave as expected. The op amp s low frequency behavior does not determine circuit behavior; not even for DC applications. EXAMPLE A typical example of an incorrect circuit analysis is shown here. A MCP603 op amp, at unity gain, drives the MCP34 Delta-Sigma ADC; see Figure 7. The MCP34 has a typical data rate between 3.75 SPS (8 bits) and 40 SPS ( bits); it appears to operate at DC. For this reason, the MCP603 seems like a good choice as a driver; it has low quiescent current (I Q = 0.9 µa), low offset voltage (V OS ±50 µv), and low DC output resistance (see Table B-): EQUATION : Switched capacitors do not present a DC resistance to the circuit driving them. R ODC = G N ( R O A OL ) = 0.3Ω MCP603 Z IND.5 MΩ MCP34 R ODC 0.3Ω Δ Σ FIGURE 7: Driving the MCP34; Incorrect Model of Interaction. It would appear that the gain error caused by the interaction between R ODC and Z IND is about ppm. Reality is very different from this simple model. 008 Microchip Technology Inc. DS00884B-page 7

8 AC Analysis The simplest useable model for the interaction between the op amp and ADC uses the op amp s gain and closed-loop output impedance (at the ADC s sampling rate), and the ADC s equivalent input resistance. We will ignore other harmonics to simplify the analysis. FIRST EXAMPLE The MCP34 s input sampling capacitor switches at a much higher rate than the data rate (by the oversampling ratio). This sampling rate (f SMP ) is about 6 ksps when in the 8-bit mode. This is higher than the MCP603 s bandwidth (0 khz). For this particular circuit, we can use the MCP603 s open-loop output resistance (R O ) to estimate the DC gain accuracy; Z O is constant at f SMP and above. Because Z O is constant, there is no need for more sophisticated analyses. Figure 8 shows this model of how the op amp and ADC interact. FIGURE 8: Driving the MCP34; Improved Model of Interaction. Thus, the DC gain error is about -3%. This size of error is unacceptable; it is about 900 times larger than the MCP34 s maximum specified INL. Bench measurements (-5%) are close to this result. SECOND EXAMPLE FASTER OP AMP A faster op amp is better in two ways. The equivalent output inductance is smaller because the open-loop output resistance is smaller and the gain bandwidth product is higher. If it is fast enough to be inductive at the ADC s sampling rate, its contribution to the error budget is greatly reduced. Note: MCP603 A faster op amp can avoid many of the problems listed earlier. Replacing the op amp with a MCP606 gives (see Figure 9 and Table B-): R O = 4.0 kω f GBP = 55 khz f P = 673 khz G N = K = V/V A 55 khz L OUT 4.3 mh R OUT 5.46 kω Z OUT =R O 7.8 kω f f SMP Z IND.5 MΩ MCP34 Δ Σ MCP606 FIGURE 9: a faster op amp. Driving the MCP34; using An AC analysis of this circuit is quick and easy to do. At the MCP34 sample rate (f SMP ) of 6 ksps, the MCP606 s output impedance is approximately: EQUATION 3: The gain error can be roughly approximated by a ratio of complex impedances. The fact that they are almost 90 out of phase greatly reduces the error: EQUATION 4: Both the DC gain error and the phase shift (time delay) are negligible. The cost for these improvements is using an op amp with a V OS of ±50 µv (was ±50 µv), and an I Q of 8.7 µa (from 0.9 µa). Step Response Analysis Z IND.5 MΩ Z OUT (7Ω) (87.7 ) Z OUT = R OUT ( jπf SMP L OUT ) Z OUT = ( 5.46 kω) j( 7Ω) = ( 7Ω) 87.7 Z OUT Z IND Z IND + Z OUT Z IND Z IND + Z OUT MCP34 Δ Σ = (.5 MΩ) (.5 MΩ) + ( 8.7 Ω) + j( 7 Ω) = ( 3.9 ppm) A step response analysis of this circuit is more accurate and informative than an AC analysis. To see how this circuit behaves when it switches, place a step function at the input and see how quickly the output settles to the desired accuracy. The settling time must be short enough to allow the ADC to settle accurately. DS00884B-page Microchip Technology Inc.

9 FIRST EXAMPLE Figure 0 models this circuit in the time domain for the MCP603 op amp. SECOND EXAMPLE Figure models this circuit in the time domain for the MCP606 Op Amp. MCP603 MCP606 K +s/ω 3dBA L OUT.6 H R OUT 80.7 kω MCP34 Δ Σ K +s/ω 3dBA L OUT 4.3 mh R OUT 5.46 kω MCP34 Δ Σ Z IND = ADC s differential input impedance 8 pf switched at f SMP 6 ksps FIGURE 0: Op Amp and ADC Models for Time Domain Analysis. We now estimate the step response settling time using 8 pf as the load capacitance (see Equation 9, Equation A-5, and Equation A-5): /(f SMP Z IND ) 8 pf f P 7.9 khz khz t set 30 µs, x set = 0% t set 56 µs, x set = % t set 83 µs, x set = 0.% t set 0 µs, x set = 0.0% Since the f SMP is about 6 ksps, the sample period (T SMP ) is about 6.5 µs. Notice that each decade of increase in x set gives an increase of 7 µs in t set, so a 5% error would happen at: t set 38 µs, x set = 5% This means that about 6% of T SMP may have been used for the ADC s settling when the bench results were measured. The MCP603 op amp is too slow for this application, unless we compensate it. Z IND = ADC s differential input impedance 8 pf switched at f SMP 6 ksps FIGURE : Op Amp and ADC Models for Time Domain Analysis. We now estimate the step response settling time using 8 pf as the load capacitance (see Equation 9, Equation A-5, and Equation A-5): /(f SMP Z IND ) 8 pf f P 458 khz khz t set 3.0 µs, x set = 0% t set 5.5 µs, x set = % t set 8.0 µs, x set = 0.% t set 0.5 µs, x set = 0.0% From the first example, we know that T SMP is about 38 µs. Each decade of x set gives an increase of.5 µs in t set, so x set at 38 µs should be roughly 8.3 decades below 0.0%; the settling error should be negligible. It is also encouraging that the pole quality factor ( ) is low; the MCP606 should be a good fit for this application without any compensation. 008 Microchip Technology Inc. DS00884B-page 9

10 Improved Design Using R-C Snubber A R SH and C SH snubber reduces the output impedance of an op amp at higher frequencies, which reduces the resistor gain error at the ADC s sampling rate. The snubber can be designed to maintain feedback stability and greatly reduce output resistance at the ADC s sampling rate (and its harmonics). The cost for this improvement is low. Best of all, we avoided using an op amp with higher supply current. EXAMPLE The R ISO and values for the MCP603, estimated by Equation 8, are shown in Figure. It shows normalized load capacitance ( /G N ) for convenience. 00,000 00k Estimated R ISO ( ) 0,000 0k,000 k 0p 00p n 0n 00n µ.e-.e-0.e-09.e-08.e-07.e-06 Normalized Load Capacitance; /G N (F) FIGURE : MCP603. G N = + G N + MCP603 Estimated R ISO for the The capacitive load presented by the ADC in Figure 3 is small (8 pf); we don't need to stabilize the op amp for this load. This circuit, however, uses a snubber (R SH and C SH ) to reduce the output resistance at the switching frequency, which improves the step response (reduces the Q of the resonant circuit). Figure helps us select R SH and C SH values that will keep the op amp stable (C SH acts as a capacitive load), while selecting a reasonable value of R SH : R SH ( R ISO ) was selected to be kω in order to reduce the resistor gain error to about % C SH ( ) was selected as the largest corresponding capacitance (. µf) in Figure The pole set by R SH and C SH (7 Hz) is much smaller than the ADC s sampling rate (6 ksps). Thus, the ADC s input sees a constant impedance at the sample rate (and its harmonics). Figure 3 includes a resistor to balance the impedance at the ADC s inputs (R BAL ) at the sampling frequency; it may not be needed in all designs. MCP603 FIGURE 3: an R-C Snubber..00 kω R SH.00 kω C SH. µf Z IND.5 MΩ Driving the MCP34; using We now investigate the step response settling time with a load capacitance of 8 pf; C SH is a short circuit (see Equation 9, Equation A-5, and Equation A-6): =. µf f P 99.6 Hz Hz t set 0 µs, x set = 0% t set 0 µs, x set = % t set 30 µs, x set = 0.% t set 40 µs, x set = 0.0% MCP34 Δ Σ R BAL.00 kω Since the amplifier is now much slower than the ADC s sampling rate, and the snubber looks like a constant resistance at the sample rate, the amplifier s output impedance dominates the performance. The DC error should be about % as we expected. Since we have a double pole, any crosstalk at 6 khz will be rejected by 88 db. C SH will need to be larger when the MCP34 is run at lower precision (lower sampling rate, but higher data rates). See Appendix C: MCP34 Sampling Rates for more information. DS00884B-page Microchip Technology Inc.

11 NON-LINEAR RESPONSE Capacitive loads can cause a non-linear response when they demand more current than the op amp s output can produce. This non-linearity imposes a limit on the output voltage slew rate (not the op amp s internal slew rate specified in its data sheet). Physical Cause Of Slew Rate Limitation The op amp produces an output current (I OUT ) that goes into a capacitive load ( ); see Figure 4. Since I OUT cannot exceed the op amp s output short circuit current (I SC ), and the voltage on ( ) changes at a rate proportional to I OUT, is slew rate limited (SR CL ). SR CL is physically independent of the op amp s internally set slew rate (SR); the slower of the two will dominate circuit behavior. R G MCP6XXX R F I OUT FIGURE 4: I OUT,, and. We can derive SR CL (units of V/s) as follows: One solution is to low-pass filter the signal before it reaches ; see Figure 5. The filter (LPF) bandwidth (BW) at the input needs to satisfy: EQUATION 8: LPF FIGURE 5: Low-pass Filter that Prevents SR CL Limitations. Another solution is to add R ISO as shown in Figure 6. This both limits I OUT and adds an output low-pass filter. The maximum current occurs when (t) = 0; at this point the voltage across R ISO is V M. Thus, we need: EQUATION 9: BW min SR CL < (, SR) πv M R G MCP6XXX I OUT R F R ISO > V M I SC EQUATION 5: d () t I OUT () t = dt SR CL max d = () t = dt I SC R G MCP6XXX R F RISO I OUT Slew Rate and Sine Waves Sine waves with edge rates faster than SR CL or SR cause signal distortion. The maximum edge rate is: EQUATION 6: max d () t dt = πfv M DESIGN To avoid slew rate limitations, we need: EQUATION 7: () t = V M sin( πft) πfv M < min( SR CL, SR) FIGURE 6: Isolation Resistor (R ISO ) that Limits Output Current (I OUT ) and Bandwidth (BW). This choice will reduce the signal bandwidth at to: EQUATION 0: I SC SR CL BW = < = πr ISO πv M πv M This solution gives a result similar to Equation 8, but does not avoid the limitations imposed by the op amp s internal SR. This latter limitation can only be prevented before the op amp, not after. These design equations, and those in Appendix A: nd Order System Response Model, can be used to find the resulting performance as long as the signal s slew rate does not exceed SR or SR CL. 008 Microchip Technology Inc. DS00884B-page

12 EXAMPLE Let s look at the MCP67 with G = + V/V and =.0 µf. In Table B- we find SR = 0.9 V/µs and I SC = 5 ma, giving: SR CL This is much lower than SR. With a maximum peak voltage of.5v PK, we need an input signal with a bandwidth less than.8 khz. If we use R ISO to limit the output current, then it needs to be > 00 Ω. Setting R ISO = 30 Ω gives: If we used the R ISO value for response peaking elimination (7.6 Ω for =/ ), we would achieve a wider bandwidth (9 khz), but would need to keep V M <0.5V PK to avoid output current limiting and severe signal distortion. Slew Rate and Square Waves Square waves with fast edges can also cause problems with capacitive loads. The maximum edge rate of a square wave with a rise time (0% to 90%) of t r, and a peak-to-peak voltage of V PP, is approximately: DESIGN = 0.08 V/µs = =. khz EQUATION : max d () t 0.8V PP dt t r To avoid slew rate limited rise times, we need square waves with lower edge rates (lower V PP and higher t r ): EXAMPLE Let s use the MCP67 with G = + V/V and = 00 nf. In Table B- we find SR = 0.9 V/µs and I SC = 5 ma. We can then calculate: SR CL = 0.5 V/µs which is significantly slower than SR. With a maximum voltage swing of 5.0V PP, we need an input signal with a rise time > 6 µs. Filtering the input square wave at the input of the op amp would require a bandwidth less than khz. If we use R ISO to limit the output current (with a maximum voltage swing of 5.0V PP and an input rise time of 0 µs), then we need R ISO >75Ω. Setting R ISO =00Ω gives: = 0.8 = 6 khz Note that if we used the R ISO value for response peaking elimination (4.0Ω for =/ ), we would achieve a wider small signal bandwidth (9 khz), but would need to keep V PP <3.7V PP to avoid output current limiting and reduced rise and fall times. POWER DISSIPATION Reactive elements (ideal capacitors and inductors) do not dissipate power. An op amp driving a reactive load, however, does dissipate power; load current in the output stage is rectified by the output transistors. Figure 7 shows the circuit under discussion. There will be no DC load current because blocks DC. At low frequencies, I Q (op amp s quiescent current) and will dominate. At high frequencies, R ISO will dominate. EQUATION : 0.8V PP < min( SR t CL, SR) r MCP6XXX RISO I OUT Low-pass filtering the square waves at the input, with a BW = 0.35/t r (see Figure 5), limits the edge rates. Using slower logic gates also reduces t r. The edge rate can be limited at the output by using R ISO (see Figure 6). The maximum I OUT occurs when the ideal output just reaches the new level and (t) is still slew rate limited. To keep I OUT <I SC, we need: EQUATION 3: V PP ( t r 0.8)min( SR CL, SR) R ISO > I SC Using R ISO will both slow the edges down and change the shape of the transitions. R G R F FIGURE 7: I OUT,, and. At low (sine wave) frequencies, the average op amp power dissipated is: EQUATION 4: P OA ( V DD V SS )( I Q + V M f ) () t = V M sin( πft) f « πr ISO The power dissipation increases with frequency because dominates the load. DS00884B-page 008 Microchip Technology Inc.

13 At high frequencies, the average power dissipated by the op amp becomes constant because R ISO dominates: EQUATION 5: V P OA ( V DD V SS ) I M Q f» πr ISO πr ISO In the frequency range where neither or R ISO dominates the load (f /(πr ISO )), estimate P OA as the minimum value from the two formulas above. P OA is actually a little lower than this estimate. MISCELLANEOUS TOPICS V M R ISO Driving Large Capacitors Quickly When capacitive loads are too large to be driven quickly by our op amps, it may pay to look at Microchip s line of Power MOSFET Drivers ( They have very large bandwidths, rise times, and slew rates; they are designed for capacitive loads. Design Verification We recommend that you always verify the performance of your circuit design with SPICE simulations, and by breadboarding it on the bench. Use standard design practices to guard band against unusual events and conditions. SPICE macro models of Microchip s op amps are available on our web site ( for your convenience. Simplifications Made in This Application Note This application note s scope has been limited to keep the results simple to understand and apply. These simplifications include: The models (and equations) are simplified - Actual circuits have higher order system responses (e.g., 4 th -order); possibly including transmission zeros - Component variations with process, temperature, operating voltages, and time The data in Table B- is for guidance only Only the most common issues and solutions are included Driving Multiple Loads Sometimes op amps are used to drive multiple loads. There can be significant parasitic capacitance at each load, including: PCB trace capacitance Wiring or coax capacitance Capacitors for RFI (EMC) suppression Load s input capacitance These loads can have a significant affect, since there are multiple load points. It may pay to add R ISO on the PCB (at the op amp s output), even when it does not appear to be needed. R ISO can be populated with a very low resistance until the design is tried out in real world conditions. 008 Microchip Technology Inc. DS00884B-page 3

14 SUMMARY When op amps drive large capacitive loads, they tend to show peaking or oscillation, reduced bandwidth, lower output slew rate, and higher power consumption. Switched capacitors interact with the op amp s output impedance at the switching frequency, causing DC gain errors and other artifacts. These problems exist even in DC applications. The output short circuit current causes a limited rate of change in the output voltage. Adding one resistor (and some times one capacitor) to the circuit can greatly improve the performance. Two different implementations are shown with different trade-offs. Simple formulas are given that allow a circuit designer to quickly evaluate the impact of capacitive loads. Simulation tools and evaluation on the bench were also covered. Alternate parts for designs with stringent requirements were mentioned. REFERENCES Op Amps [] Bonnie Baker, AN73 - Operational Amplifier AC Specifications and Applications, Microchip Technology Inc., DS0073, 000. [] Adel Sedra and Kenneth Smith, Microelectronic Circuits, 3 rd ed., Saunders College Publishing, 99, Chapter 8. [3] Paul R. Gray and Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, nd ed., John Wiley & Sons, 984. Second Order System Response [4] Charles Phillips and H. Troy Nagle, Digital Control System Analysis and Design, nd ed., Prentice Hall, 990, pp 9-3. [5] Benjamin Kuo, Automatic Control Systems, 5 th ed., Prentice Hall, 987. DS00884B-page Microchip Technology Inc.

15 APPENDIX A: ND ORDER SYSTEM RESPONSE MODEL In this application note, we have seen second order transfer functions with no zeros. This type of transfer function models the op amp circuits in this application note reasonably well. This appendix will show equivalent forms of the transfer function that are useful. It also shows some simple formulas for sine wave and step responses which help evaluate the performance of the circuits in this application note [, 4, 5]. Suggestions on extracting these parameters from measurements is also given. It is sometimes useful to reverse this process: EQUATION A-4: ω P ω P ω P A. Sine Wave Response = = ω P ω P ω P ω P Figure A- shows a typical frequency (sine wave) response. + A. Equivalent Transfer Functions The form of the transfer function used in the body of this application note is: EQUATION A-: K s ω P s ω P H PK K K/ / (log scale) f (log scale) In many engineering fields, including control theory, this transfer function would also be written with the damping coefficient (ζ). This form is useful because ζ divides the response cases into under-damped (0 < ζ <), critically damped (ζ = ), and over-damped (ζ > ). See reference [ 5] for more information. EQUATION A-: s K + ζ ω P ζ = damping coefficient = s ω P FIGURE A-: Frequency Response. These exact equations for are set up to minimize numerical truncation or rounding errors: EQUATION A-5: f PK f P Q P =, Q P -- Q 4 + P + Q P f P = + +, > When /, it is useful to factor the denominator into two real poles: EQUATION A-3: 0 V OUT K s s ω P ω P / f P 0. ω P A = = ω P A ω P = ω P A FIGURE A-: vs.. Normalized -3 db Bandwidth 008 Microchip Technology Inc. DS00884B-page 5

16 The peak gain (H PK ) occurs at the frequency f PK. Gain peaking (H PK /K) is a normalized parameter: EQUATION A-6: EQUATION A-7: f PK / f P FIGURE A-3: vs.. f PK = 0, f PK = f P , > H PK =, Q K P H PK = Q K P , > Normalized Peak Frequency A.3 Square Wave Response Figure A-5 shows a typical step (square wave) response; is normalized by the gain K. The parameters shown are: overshoot (x max ), settling accuracy (x set ), 0% time (t 0 ), delay (50%) time (t d ), 90% time (t 90 ), time to peak overshoot (t max ), and settling time (t set ). +x max FIGURE A-5: /K Step Response. The unit step response formulas for under-damped, critically damped, and over-damped responses are: EQUATION A-8: 0 t 0 t d t 90 t max t set V OUT = [ At ()] u() t K < () t = u() t At () +x set x set ω P exp( ω P t) ω P exp( ω P t) = ω P ω P t H PK / K 0 FIGURE A-4: vs Normalized Peak Magnitude EQUATION A-9: V OUT = [ B () t ] u() t K = () t = u() t Bt () = ( + ω P t) exp( ω P t) DS00884B-page Microchip Technology Inc.

17 EQUATION A-0: V OUT = [ Ct ()] u() t K > -- () t = u() t A = φ = acos ω P t exp Q Ct () P sin( ω At + φ ) P = A The delay time (t d = 50% time) is roughly: EQUATION A-: t Q + P 0.089Q +0.98Q 3 P P d , -- t d Q 3 P Q P , > -- t r FIGURE A-7:. Normalized Rise Time vs. When > /, the step response exhibits overshoot (x max ). x max and the time to the peak overshoot (t max ) are: EQUATION A-3: x max = 0%, x max = ( 00% ) exp( π ( 4 ) ), > EQUATION A-4: t max = 0, t d FIGURE A-6:. Normalized Delay Time vs. The 0% to 90% rise time (t r ) is approximately: EQUATION A-: t r = t 90 t t r , -- t r Q 3 P Q P , > -- t max f P t max = ( f P 4 ), >.E % FIGURE A-8: Time vs.. t max f P x max.e+00 00%.E-0 0% x max.e-0 % Normalized Peak Overshoot 008 Microchip Technology Inc. DS00884B-page 7

18 Given a desired settling accuracy (x set ), it is possible to estimate the corresponding settling time (t set ). When /, the following approximations are useful: EQUATION A-5: t set , x set = 0% t set , x set = % t set , x set = 0.% t set , -- x set = 0.0% Note: Figure A-9 shows t set when /, and shows t env when > /. t set may actually be smaller than t env in the latter region. A.4 Extracting a nd Order Model From Measurements When frequency response measurements contain little noise and the response is very close to nd order, it is simple to extract K, f P, and. Extract from / (in units of ) - f P where the phase is -90 Extract from / (in units of V/V) - Gain K at low frequencies (f << ) - Gain K at the resonant frequency (f = f P ) When there is significant noise, or the response is not approximately quadratic, more sophisticated methods may are needed to fit the data over many frequency points. A least means square fit will be good enough in most cases. Emphasize the fit at frequencies near to the -3 db bandwidth; this region has the most influence on stability and signal response shape. When > /, it is hard to calculate the settling time (t set ) exactly; the ringing creates discrete jumps in t set as x set is varied. Instead, we estimate the time until the ringing s envelop (t env ) reaches the accuracy x set : EQUATION A-6: t env = ln x set ω P t set t env > xset: 0.0% 0.% % 0% t set FIGURE A-9: vs.. Normalized Settling Time DS00884B-page Microchip Technology Inc.

19 APPENDIX B: MICROCHIP OP AMPS B. Estimating f P To estimate f P for the op amp model, find the frequency in the data sheet s Open-Loop Gain plot where the phase is -35 (f -35 ). Adjust f -35 for the typical capacitive load (typ ) used in that plot (usually 60 pf in our data sheets): B. Op Amp Performance The performance parameters of some Microchip op amps shown in Table B- were extracted from the parts data sheets. These data sheets contain the officially supported specifications, and can be found on our web site ( EQUATION B-: φ CLtyp atan( πf 35 R O typ ) f P f 35 tan( 45 min( φ CLtyp, 40 )) TABLE B-: Part G N_MIN (V/V) Specified ESTIMATES OF TYPICAL MICROCHIP OP AMP PARAMETERS f GBP (Hz) Typ SR (V/µs) Typ f -35 (Hz) Typ B.3 MCP6V0//3 and MCP6V06/7/8 Op Amps These auto-zeroed op amps have an output impedance that is more complex than the simple model shown in Figure 5. To stabilize these op amps, see the information in their data sheets. I SC at min V DD (ma) Typ I SC at max V DD (ma) Typ R O (Ω) Meas Φ CLtyp ( ) Typ MCP604 4k k 0 0k 4 63k MCP k k 0 08k 3 6.k MCP603 0k k k 3 0k TC034 60k k k M (Note ) MCP606 55k k k 3 673k MCP66 90k k k 30.0M MCP63 300k k 6 3.6k M MCP64 550k M k M MCP600.00M G G MCP67.00M M M MCP60.80M.3 3.0M M MCP M.5.0M M MCP69 0.0M M M MCP60 0.0M M M Note : The TC034 parameters also apply to the TC06, TC09, TC030, and TC035. f P (Hz) Typ 008 Microchip Technology Inc. DS00884B-page 9

20 APPENDIX C: MCP34 SAMPLING RATES The current MCP34 data sheet (as of November 008) does not directly include information on its sampling rate. The data rate is related to the sampling rate; it includes overhead for communication to the microcontroller. TABLE C-: Precision (bit) Selected MCP34 SAMPLING RATES Data Rate (SPS) Typ Sampling Rate (SPS) Typ (Note ) Note : The data sheet is the official source of specifications; this table is for information only. DS00884B-page Microchip Technology Inc.

21 Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as unbreakable. Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dspic, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfpic, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dspicdem, dspicdem.net, dspicworks, dsspeak, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mtouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC 3 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rflab, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. 008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-6949:00 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company s quality system processes and procedures are for its PIC MCUs and dspic DSCs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip s quality system for the design and manufacture of development systems is ISO 900:000 certified. 008 Microchip Technology Inc. DS00884B-page

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