CLASSIC Modelling, Specification, and Verification
|
|
|
- Brendan Camron Rich
- 8 years ago
- Views:
Transcription
1 CLASSIC Modelling Specification and Verification using UPPAAL Kim Guldstrand Larsen
2 Modelling using Finite State Machines
3 Modelling processes UC b A process is the execution of a sequential program. modeled as a finite state machine LTS transits from state to state by executing a sequence of atomic actions. a light switch LTS on off on off on off. a sequence of actions or trace Kim G. Larsen 3
4 Modelling Choices UC b Who or what makes the choice? Is there a difference between input and output actions? Kim G. Larsen 4
5 Non-deterministic Choice UC b Tossing a coin Possible traces? Both outcomes possible Nothing said about relative frequency If coin is fair the outcome is 50/50 Kim G. Larsen 5
6 Non-Deterministic Choice modelling failure UC b How do we model an unreliable communication channel which accepts packets and if a failure occurs produces no output otherwise delivers the packet to the receiver? Use non-determinism... Kim G. Larsen 6
7 Internal-Actions UC b Spontaneous actions Internal actions Tau-actions Internal transitions can be taken on the initiative of a single machine without communication with others Kim G. Larsen 7
8 Extended FSM UC b EFSM = FSM + variables + enabling conditions + assignments Transition still atomic Can be translated into FSM if variables have bounded domain State: control location + variable values: stateamountcapacity s0510 Kim G. Larsen 8
9 Parallel Composition: interleaving UC b Flipper 2 states Speaker 3 states 2*3 states Lecturer = Speaker Flipper from Flipper Kim G. Larsen from Speaker 9
10 Process Interaction! = Output? = Input Handshake communication Two-way Coffee Machine Lecturer UC b University= Coffee Machine Lecturer LTS? How many states? Traces? 4 states 4 states synchronization results in internal actions 4 states:interaction constrain overall behavior Kim G. Larsen 10
11 Adding Time
12 Wang Yi Paul Pettersson John Håkansson Anders Hessel Pavel Krcal Leonid Mokrushin Kim G Larsen Gerd Behrman Arne Skou Brian Nielsen Alexandre David Jacob I. Rasmussen Marius Mikucionis Thomas Chatain Emmanuel Fleury Didier Lime Johan Bengtsson Fredrik Larsson Kåre J Kristoffersen Tobias Amnell Thomas Hune Oliver Möller Elena Fersman Carsten Weise David Griffioen Ansgar Fehnker Frits Vandraager Theo Ruys Pedro D Argenio J-P Katoen Jan Tretmans Judi Romijn Ed Brinksma Martijn Hendriks Klaus Havelund Franck Cassez Magnus Lindahl Francois Laroussinie Patricia Bouyer Augusto Burgueno H. Bowmann D. Latella M. Massink G. Faconti Kristina Lundqvist Lars Asplund Justin Pearson...
13 Real Time Systems Plant Continuous Eg.: Realtime Protocols Pump Control Air Bags Robots Cruise Control ABS CD Players Production Lines sensors actuators Controller Program Discrete Real Time System A system where correctness not not only only depends on on the the logical order of of events but but also also on on their their timing!!
14 Real Time Model Checking Plant Continuous Model of environment user-supplied / non-determinism b a c b a c sensors actuators UPPAAL Model 4 Controller Program Discrete Model of tasks automatic? 1 2 SAT φ a?? b c 3 4
15 Real Time Control Synthesis Plant Continuous Model of environment user-supplied b a c b a c sensors actuators Controller Program Discrete?? Partial UPPAAL Model Synthesis of tasks/scheduler automatic SAT φ!! SAT a φ!! b c
16 Real-time Model-Based Testing Plant Continuous Test generation offline or online wrt. Design Model b a c b a c sensors actuators inputs outputs UPPAAL Model 3 4 Controller Program Discrete Conforms-to? 4 4 b a c
17 UPPAAL Graphical Design Tool Tool timed automata = state machines + clocks communication datatypes user user defined functions cost cost variable
18 UPPAAL Graphical Simulator visualization and and recording inexpensive fault fault detection inspection of of error traces Message Sequence Charts Gannt Charts
19 UPPAAL Verifier Exhaustive & automatic checking of of requirements.... including validating safety liveness bounded liveness and and response properties.... generation of of debugging information for for visualisation in in simulator. Optimal scheduling for for cost cost models
20 Impact UPPAAL downloads y = 3236x x Date UPPAAL downloads Year Google: UPPAAL: SPIN Verifier: nusmv: > Google Scholar Citations Rhapsody/Esterel < Downloads per month Total number of Dowloads
21 Impact Academic DTU MCI IT-U DK Chalmers LinköpingLund Chalmers Mälardalarn S Nijmegen Twente CWI NL Upenn NorthumbriaUS Braunschweig Oldenborg Marktoberdorf D Tsinghua Shanghai ISS NUS Asia
22 Impact Tutorials Estonian School 01 IPA Fall Days 01 FTRTFT 02 CPN 02 SFM 02 MOVEP 02 DISC School 03 MOVEP 04 PRISE 04 PDMC 05 ARTIST2 05 EMSOFT 05 RTSS 05 TECS week 06 TAROT 06 ARTS 06 GLOBAN 06 ARTIST ASIAN SCH 07
23 Impact Company Downloads Mecel Jet Symantec SRI Relogic Realwork NASA Verified Systems Microsoft ABB Airbus PSA Saab Siemens Volvo Lucent Technologies
24 Timed Automata Alur & Dill 1989
25 Dumb Light Control Off Light Bright WANT: if press is issued twice quickly then the light will get brighter; otherwise the light is turned off.
26 Dumb Light Control Alur & Dill 1990 x:=0 Off Light Bright x>3 x 3 Solution: Add real-valued clock x
27 Timed Automata review Alur & Dill 1990 Action used for synchronization n x<=5 & y>3 a x := 0 m Discrete Trans Delay Trans Clocks: x y Transitions Guard Boolean combination of integer bounds on clocks Reset Action performed on clocks State location x=v y=u where vu are in R n x=2.4 y= a m x=0 y= n x=2.4 y= e1.1 n x=3.5 y=4.2415
28 Timed Automata Alur & Dill 1990 Reset x:=0 Off Light Bright x: realvalued clock States: States: location location x=v x=v where where v R v R x>3 x 3 Synchronizing action Guard Conjunctions of x~n Transitions: Transitions: Off Off x=0 x=0 delay delay Off Off x=4.32 x=4.32 Light Light x=0 x=0 delay delay Light Light x=2.51 x=2.51 Bright Bright x=2.51 x=2.51
29 Timed Automata Alur & Dill 1990 Reset x:=0 Off Light Bright x: realvalued clock States: States: location location x=v x=v where where v R v R x>3 x 3 Synchronizing action Guard Conjunctions of x~n Transitions: Transitions: Off Off x=0 x=0 delay delay Off Off x=4.32 x=4.32 Light Light x=0 x=0 delay delay Light Light x=2.51 x=2.51 Bright Bright x=2.51 x=2.51
30 Timed Automata Alur & Dill 1990 Reset x:=0 Off Light Bright x: realvalued clock States: States: location location x=v x=v where where v R v R x>3 x 3 Synchronizing action Guard Conjunctions of x~n Transitions: Transitions: Off Off x=0 x=0 delay delay Off Off x=4.32 x=4.32 Light Light x=0 x=0 delay delay Light Light x=2.51 x=2.51 Bright Bright x=2.51 x=2.51
31 Timed Automata Alur & Dill 1990 Reset x:=0 Off Light Bright x: realvalued clock States: States: location location x=v x=v where where v R v R x>3 x 3 Synchronizing action Guard Conjunctions of x~n Transitions: Transitions: Off Off x=0 x=0 delay delay Off Off x=4.32 x=4.32 Light Light x=0 x=0 delay delay Light Light x=2.51 x=2.51 Bright Bright x=2.51 x=2.51
32 Timed Automata Alur & Dill 1990 Reset x:=0 Off Light Bright x: realvalued clock States: States: location location x=v x=v where where v R v R x>3 x 3 Synchronizing action Guard Conjunctions of x~n Transitions: Transitions: Off Off x=0 x=0 delay delay Off Off x=4.32 x=4.32 Light Light x=0 x=0 delay delay Light Light x=2.51 x=2.51 Bright Bright x=2.51 x=2.51
33 Intelligent Light Control Using Invariants x:=0 Off Light Bright x:=0 x:=0 x=100 x 100 x 3 x:=0 x>3 x:=0 x=100 X:=0 x 100 X<=3 x:=0 Off Light Bright X>3
34 Timed Automata review Invariants Location Invariants n x<=5 x<=5 & y>3 a x := 0 m y<=10 g4 g1 g2 g3 Clocks: x y Transitions n x=2.4 y= e3.2 e1.1 n x=2.4 y= n x=3.5 y= Invariants ensure progress!!
35 Intelligent Light Control Using Invariants x:=0 x=100 x:=0 Off Light Bright x:=0 x=100 Transitions: Transitions: Off Off x=0 x=0 delay delay Off Off x=4.32 x=4.32 Light Light x=0 x=0 delay delay Light Light x=4.51 x=4.51 Light Light x=0 x=0 delay delay Light Light x=100 x=100 τ Off Off x=0 x=0 τ x 100 x 3 x:=0 x>3 x:=0 x 100 x:=0 X Note: Note: Light Light x=0 x=0 delay delay Invariants ensures progress
36 Example With two clocks a b c Reachable?
37 Example With two clocks y a c b L0x=0y=0 x Reachable?
38 Example With two clocks y a c b ε1.4 L0x=0y=0 ε1.4 L0x=1.4y=1.4 x Reachable?
39 Example With two clocks y a c b ε1.4a L0x=0y=0 ε1.4 L0x=1.4y=1.4 a L0x=1.4y=0 x Reachable?
40 Example With two clocks y a c Reachable? b ε1.4a a ε1.6 L0x=0y=0 ε1.4 L0x=1.4y=1.4 a L0x=1.4y=0 ε1.6 L0x=3.0y=1.6 a L0x=3.0y=0 x
41 Networks x:=0 Light Controller & User x=100 Off Light Bright Rest x:=0 Synchronization y 10 y:=0 x:=0 press! press! x=100 x 100 y:=0 Busy y 10 x 3 x:=0 x>3 x:=0 x 100 x:=0 Transitions: Transitions: Off Off Rest Rest x=0 x=0 y=0 y=0 delay delay Off Off Rest Rest x=20 x=20 y=20 y=20!! Light Light Busy Busy x=0 x=0 y=0 y=0 delay delay 2 2 Light Light Busy Busy x=2 x=2 y=2 y=2!! Bright Bright Rest Rest x=0 x=0 y=0 y=0
42 Networks of Timed Automata a la CCS l1 m1 x>=2 y<=4 a! a? x := 0 l2 m2 Example transitions. Two-way Two-way synchronization synchronization on on complementary complementary actions. actions. Closed Closed Systems! Systems! l1 m1 x=2 y=3.5.. tau l2m2..x=0 y= l1m1 x=2.2 y=3.7.. If a URGENT CHANNEL
43 Timed Automata Formally
44
45
46
47
48 Timed Automata: Example location action guard a reset-set
49 Timed Automata: Example guard location action a reset-set a a
50 Timed Automata: Example x 3 a Invariant
51 Timed Automata: Example x 3 a a a a Invariant
52 Brick Sorting
53 LEGO Mindstorms/RCX Sensors: temperature light rotation pressure. Actuators: motors lamps Virtual machine: 10 tasks 4 timers 16 integers. Several Programming Languages: 3 output ports 1 infra-red port NotQuiteC Mindstorm Robotics legos etc. 3 input ports
54 A Real Real Timed System The Plant Conveyor Belt & Bricks Controller Program LEGO MINDSTORM
55 First UPPAAL model Sorting of Lego Boxes Ken Tindell Boxes Conveyer Belt Blck Yel Controller MAIN PUSH eject remove Black Piston 99 Red Exercise: Design Controller so that black boxes are being pushed out
56 NQC programs int int active; active; int int DELAY; DELAY; int int LIGHT_LEVEL; LIGHT_LEVEL; task task MAIN{ MAIN{ DELAY=75; DELAY=75; LIGHT_LEVEL=35; LIGHT_LEVEL=35; active=0; active=0; task task PUSH{ PUSH{ SensorIN_1 SensorIN_1 IN_LIGHT; IN_LIGHT; whiletrue{ whiletrue{ FwdOUT_A1; FwdOUT_A1; waittimer1>delay && && active==1; active==1; Display1; Display1; active=0; active=0; RevOUT_C1; RevOUT_C1; start start PUSH; PUSH; Sleep8; Sleep8; FwdOUT_C1; FwdOUT_C1; whiletrue{ whiletrue{ Sleep12; Sleep12; OffOUT_C; OffOUT_C; waitin_1<=light_level; } ClearTimer1; ClearTimer1; } active=1; active=1; PlaySound1; PlaySound1; waitin_1>light_level; } }
57 A Black Brick
58 Control Tasks & Piston GLOBAL DECLARATIONS: const int ctime = 75; int[01] active; clock x time; chan eject ok; urgent chan blck red remove go;
59 From RCX to UPPAAL and back Model includes Round-Robin Scheduler. Compilation of RCX tasks into TA models. Presented at ECRTS 2000 in Stockholm. From UPPAAL to RCX: Martijn Hendriks. Task MAIN
60 The Production Cell in LEGO Course at DTU Copenhagen Production Cell Rasmus Crüger Lund Simon Tune Riemanni
61 Light Control Interface
62 Light Control Interface User release? release? Interface Light touch! touch! starthold! starthold! endhold! endhold! Control Program L++/L--/L:=0 L++/L--/L:=0
63 Light Control Interface User release? release? touch! touch! starthold! starthold! endhold! endhold! Control Program L++/L--/L:=0 L++/L--/L:=0
64 Networks of Timed Automata a la CCS l1 m1 x>=2 y<=4 a! a? x := 0 l2 m2 Example transitions. Two-way Two-way synchronization synchronization on on complementary complementary actions. actions. Closed Closed Systems! Systems! l1 m1 x=2 y=3.5.. tau l2m2..x=0 y= l1m1 x=2.2 y=3.7.. If a URGENT CHANNEL
65 Network Semantics s T1 X T2 = S1 S2 s 0 X μ s1 1 s 1 μ 1 X s2 s 1 X s 2 s s 1 1 s 1 s 2 0 s a! a? 1 s 1 s2 τ X 2 ed s 1 X s s s 1 1 where X A s X s s s 2 s 1 ed s 2 1 X 2 s X s s s 2 ed 2 2 μ s 2 2 μ s X 2
66 Network Semantics URGENT synchronization s T1 X T2 = S1 S2 s 0 X μ s1 1 s 1 μ 1 X s2 s 1 X s 2 s s 1 1 s 1 s 2 0 s a! a? 1 s 1 s2 τ X 2 ed s 1 X s s s 1 1 where X A s X s s s 2 s 1 ed s 2 + Urgent synchronization 1 X 2 s X s s s 2 ed 2 2 μ s 2 2 μ s X 2 d < d u UAct: ed u? ed u! s 1 s 2
67 Light Control Network release? release? touch! touch! starthold! starthold! endhold! endhold! Control Program
68 Validation Light Controller
69 Druzba: The Shower Problem
70 The Druzba MUTEX Problem Kim Gerd
71 The Druzba MUTEX Problem
72 The Druzba MUTEX Problem Using the light as semaphor
73 Overview of the UPPAAL Toolkit
74 UPPAAL s architecture Linux Windows Solaris MacOS
75 GUI Editor Simulator Verifier
76 Train Crossing Queue Stopable Area [715] [1020] Gate [35] Crossing River
77 Train Crossing Communication via channels and shared variable. appr stop Stopable Area [715] go [1020] el el [35] Crossing leave Queue empty nonempty hd addrem Gate River
78 Timed Automata in UPPAAL
79 Declarations Constants Bounded integers Channels Clocks Clocks Arrays Arrays Templates Processes Systems
80 Declarations in UPPAAL The syntax used for declarations in UPPAAL is similar to the syntax used in the C programming language. Clocks: Syntax: clock x1 xn ; Example: clock x y; Declares two clocks: x and y.
81 Declarations in UPPAAL cont. Data variables Syntax: int n1 ; Integer with default domain. int[lu] n1 ; Integer with domain l to u. int n1[m] ; Integer array w. elements n1[0] to n1[m-1]. Example: int a b; int[01] a b[5][6];
82 Declarations in UPPAAL cont. Actions or channels: Syntax: chan a ; Ordinary channels. urgent chan b ; Urgent actions see later Example: chan a b; urgent chan c;
83 Declarations UPPAAL cont. Constants Syntax: const int c1 = n1; Example: const int[01] YES = 1; const bool NO = false;
84 Timed Automata in UPPAAL Discrete Variables Resets invariants Guards Synchronizations
85 Timed Automata in UPPAAL i: = Expr Expr :: = i i[expr] n Expr Expr Discrete + Variables Expr Expr Expr Expr * Expr Expr/Expr g d?expr : Expr Resets x := Expr inv :: = x < Expr x <= Expr invinv invariants Guards g:: = g g gg c d g:: c = x Expr x y+ Expr g::expropexpr d = Synchronizations <<===>=> { } op { < <= == >= >! = }
86 Expressions used used in in guards invariants assignments synchronizations properties
87 Expressions
88 Operators
89 Guards Invariants Assignments Guards: It is side-effect free type correct and evaluates to boolean Only clock variables integer variables constants are referenced or arrays of such Clocks and differences are only compared to integer expressions Guards over clocks are essentially conjunctions I.e. disjunctions are only allowed over integer conditions Assignments It has a side effect and is type correct Only clock variable integer variables and constants are referenced or arrays of such Only integer are assigned to clocks Invariants It forms conjunctions of conditions of the form x<e or x<=e where x is a clock reference and e evaluates to an integer
90 Synchronization Binary Synchronization Broadcast Synchronization Declared like: chan a b c[3]; If a is channel then: a! = Emmision a? = Reception Two edges in different processes can synchronize if one is emitting and the other is receiving on the same channel. Declared like broadcast chan a b c[2]; If a is a broadcast channel: a! = Emmision of broadcast a? = Reception of broadcast A set of edges in different processes can synchronize if one is emitting and the others are receiving on the same b.c. channle. A process can always emit. Receivers MUST synchronize if they can. No blocking.
91 More on Types Multi dimensional arrays e.g. int b[4][2]; Array initialiser: e.g. int b[4] := { }; Arrays of channels clocks constants. e.g. chan a[3]; clock c[3]; const k[3] { }; Broadcast channels. e.g. broadcast chan a;
92 Templates Templates may be parameterised: int v; const min; const max int[0n] e; const id Templates are instantiated to form processes: P:= Ai15; Q:= Aj04; Train1:=Trainel 1; Train2:=Trainel 2;
93 Extensions Select statement Forall / Exists expressions models a non-deterministic choise x : int[042] Types Record types Type declarations Meta variables: not stored with state meta int x; forall x:int[042] expr true if expr is true for all values in [042] of x exists x:int[04] expr true if expr is true for some values in [042] of x Example: forall x:int[04]array[x];
94 Urgency & Commitment Urgent Channels Urgent Locations No delay if the synchronization edges can be taken! No clock guard allowed. Guards on data-variables. Declarations: urgent chan a b c[3]; No delay time is freezed! May reduce number of clocks! Committed Locations No delay. Next transition MUST involve edge in one of the processes in committed location May reduce considerably state space
95 Queries : Specification Language
96 Logical Specifications Validation Properties Possibly: E<> P Safety Properties Invariant: A[] P Pos. Inv.: E[] P Liveness Properties Eventually: A<> P Leadsto: P Q Bounded Liveness Leads to within: P t Q The expressions P and Q must be type safe side effect free and evaluate to a boolean. Only references to integer variables constants clocks and locations are allowed and arrays of these.
97 Logical Specifications Validation Properties Possibly: E<> P Safety Properties Invariant: A[] P Pos. Inv.: E[] P Liveness Properties Eventually: A<> P Leadsto: P Q Bounded Liveness Leads to within: P t Q
98 Logical Specifications Validation Properties Possibly: E<> P Safety Properties Invariant: A[] P Pos. Inv.: E[] P Liveness Properties Eventually: A<> P Leadsto: P Q Bounded Liveness Leads to within: P t Q
99 Logical Specifications Validation Properties Possibly: E<> P Safety Properties Invariant: A[] P Pos. Inv.: E[] P Liveness Properties Eventually: A<> P Leadsto: P Q Bounded Liveness Leads to within: P t Q
100 Logical Specifications Validation Properties Possibly: E<> P Safety Properties Invariant: A[] P Pos. Inv.: E[] P Liveness Properties Eventually: A<> P Leadsto: P Q Bounded Liveness Leads to within: P t Q t t
101 Train Crossing Communication via channels and shared variable. appr stop Stopable Area [715] go [1020] el el [35] Crossing leave Queue empty nonempty hd addrem Gate River
102 Gear Controller with MECEL AB Lindahl Pettersson Yi 1998 GearControl Clutch Volvo Saab Network Canbus GearBox Engine Interface Flowgraph
103 Gear Controller with MECEL AB Volvo Saab GearControl Clutch Interface Requirements GearBox Engine
104 UPPAAL 3.4 Gate Template int[0n] list[n] len i; IntQueue
105 UPPAAL with C-Code Gate Template Gate Declaration
106 Case-Studies: Controllers Gearbox Controller [TACAS 98] Bang & Olufsen Power Controller [RTPS 99FTRTFT 2k] SIDMAR Steel Production Plant [RTCSA 99 DSVV 2k] Real-Time RCX Control-Programs [ECRTS 2k] Experimental Batch Plant 2000 RCX Production Cell 2000 Terma Verification of Memory Management for Radar 2001 Scheduling Lacquer Production 2005 Memory Arbiter Synthesis and Verification for a Radar Memory Interface Card [NJC 05]
107 Case Studies: Protocols Philips Audio Protocol [HS 95 CAV 95 RTSS 95 CAV 96] Collision-Avoidance Protocol [SPIN 95] Bounded Retransmission Protocol [TACAS 97] Bang & Olufsen Audio/Video Protocol [RTSS 97] TDMA Protocol [PRFTS 97] Lip-Synchronization Protocol [FMICS 97] Multimedia Streams [DSVIS 98] ATM ABR Protocol [CAV 99] ABB Fieldbus Protocol [ECRTS 2k] IEEE 1394 Firewire Root Contention 2000 Distributed Agreement Protocol [Formats05] Leader Election for Mobile Ad Hoc Networks [Charme05]
108
Vorlesung Methoden des Software Engineering
Vorlesung Methoden des Software Engineering Block F Formale Methoden F 2 Einführung in Uppaal Christian Prehofer in Zusammenarbeit mit Christian Kroiß unter Verwendung von Materialien von Alexandre David,
Model Checking Web Services
Model Checking Web Services Amit Shrigondekar, Lalindra De Silva, and Aravindan Thulasinathan School of Computing, University of Utah {amitss,alnds,aravi}@cs.utah.edu https://sites.google.com/site/modelcheckingwebservices/
0 0-10 5-30 8-39. Rover. ats gotorock getrock gotos. same time compatibility. Rock. withrover 8-39 TIME
Verication of plan models using UPPAAL Lina Khatib 1, Nicola Muscettola, and Klaus Havelund 2 NASA Ames Research Center, MS 269-2 Moett Field, CA 94035 1 QSS Group, Inc. 2 RECOM Technologies flina,mus,havelundg@ptolemy.arc.nasa.gov
A Tutorial on Uppaal 4.0
A Tutorial on Uppaal 4.0 Updated November 28, 2006 Gerd Behrmann, Alexandre David, and Kim G. Larsen Department of Computer Science, Aalborg University, Denmark {behrmann,adavid,kgl}@cs.auc.dk. Abstract.
A Static Analyzer for Large Safety-Critical Software. Considered Programs and Semantics. Automatic Program Verification by Abstract Interpretation
PLDI 03 A Static Analyzer for Large Safety-Critical Software B. Blanchet, P. Cousot, R. Cousot, J. Feret L. Mauborgne, A. Miné, D. Monniaux,. Rival CNRS École normale supérieure École polytechnique Paris
Online Checking of a Hybrid Laser Tracheotomy Model in UPPAAL-SMC
Master Thesis Xintao Ma Online Checking of a Hybrid Laser Tracheotomy Model in UPPAAL-SMC Date 06. June, 2013-06. December, 2013 supervised by: Prof. Dr. Sibylle Schupp Prof. Dr. Alexander Schlaefer Jonas
Overview Motivating Examples Interleaving Model Semantics of Correctness Testing, Debugging, and Verification
Introduction Overview Motivating Examples Interleaving Model Semantics of Correctness Testing, Debugging, and Verification Advanced Topics in Software Engineering 1 Concurrent Programs Characterized by
Extending a Real-Time Model-Checker to a Test-Case Generation Tool Using libcoverage
Uppsala Master s Thesis in Computing Science Examensarbete DV3 20 poäng Datavetenskapligt program, 160 poäng November 21, 2007 Extending a Real-Time Model-Checker to a Test-Case Generation Tool Using libcoverage
Mutation-based Testing Criteria for Timeliness
Mutation-based Testing Criteria for Timeliness Robert Nilsson Department of Computer Science University of Skövde, Box 408SE 541 28 Skövde, Sweden {robert,sten}@ida.his.se Jeff Offutt Sten F. Andler Department
Program Synthesis is a Game
Program Synthesis is a Game Barbara Jobstmann CNRS/Verimag, Grenoble, France Outline Synthesis using automata- based game theory. MoBvaBon, comparison with MC and LTL. Basics Terminology Reachability/Safety
INF5140: Specification and Verification of Parallel Systems
INF5140: Specification and Verification of Parallel Systems Lecture 7 LTL into Automata and Introduction to Promela Gerardo Schneider Department of Informatics University of Oslo INF5140, Spring 2007 Gerardo
Formal verification of contracts for synchronous software components using NuSMV
Formal verification of contracts for synchronous software components using NuSMV Tobias Polzer Lehrstuhl für Informatik 8 Bachelorarbeit 13.05.2014 1 / 19 Problem description and goals Problem description
PROGRAMMABLE LOGIC CONTROLLERS Unit code: A/601/1625 QCF level: 4 Credit value: 15 OUTCOME 3 PART 1
UNIT 22: PROGRAMMABLE LOGIC CONTROLLERS Unit code: A/601/1625 QCF level: 4 Credit value: 15 OUTCOME 3 PART 1 This work covers part of outcome 3 of the Edexcel standard module: Outcome 3 is the most demanding
StateFlow Hands On Tutorial
StateFlow Hands On Tutorial HS/PDEEC 2010 03 04 José Pinto zepinto@fe.up.pt Session Outline Simulink and Stateflow Numerical Simulation of ODEs Initial Value Problem (Hands on) ODEs with resets (Hands
PETRI NET BASED SUPERVISORY CONTROL OF FLEXIBLE BATCH PLANTS. G. Mušič and D. Matko
PETRI NET BASED SUPERVISORY CONTROL OF FLEXIBLE BATCH PLANTS G. Mušič and D. Matko Faculty of Electrical Engineering, University of Ljubljana, Slovenia. E-mail: gasper.music@fe.uni-lj.si Abstract: The
Algorithmic Software Verification
Algorithmic Software Verification (LTL Model Checking) Azadeh Farzan What is Verification Anyway? Proving (in a formal way) that program satisfies a specification written in a logical language. Formal
Introduction to SPIN. Acknowledgments. Parts of the slides are based on an earlier lecture by Radu Iosif, Verimag. Ralf Huuck. Features PROMELA/SPIN
Acknowledgments Introduction to SPIN Parts of the slides are based on an earlier lecture by Radu Iosif, Verimag. Ralf Huuck Ralf Huuck COMP 4152 1 Ralf Huuck COMP 4152 2 PROMELA/SPIN PROMELA (PROcess MEta
Eastern Washington University Department of Computer Science. Questionnaire for Prospective Masters in Computer Science Students
Eastern Washington University Department of Computer Science Questionnaire for Prospective Masters in Computer Science Students I. Personal Information Name: Last First M.I. Mailing Address: Permanent
The Model Checker SPIN
The Model Checker SPIN Author: Gerard J. Holzmann Presented By: Maulik Patel Outline Introduction Structure Foundation Algorithms Memory management Example/Demo SPIN-Introduction Introduction SPIN (Simple(
Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill
Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill Objectives: Analyze the operation of sequential logic circuits. Understand the operation of digital counters.
Automatic Translation from UPPAAL to C
1 Automatic Translation from UPPAAL to C JESPER KRISTENSEN ARNE MEJLHOLM SØREN PEDERSEN Department of Computer Science, Aalborg University Fredrik Bajers Vej 7E, 9220 Aalborg Ø, Denmark {cableman mejlholm
Application Unit, MDRC AB/S 1.1, GH Q631 0030 R0111
, GH Q631 0030 R0111 SK 0010 B 98 The application unit is a DIN rail mounted device for insertion in the distribution board. The connection to the EIB is established via a bus connecting terminal at the
Business Process Verification: The Application of Model Checking and Timed Automata
Business Process Verification: The Application of Model Checking and Timed Automata Luis E. Mendoza Morales Processes and Systems Department, Simón Bolívar University, P.O. box 89000, Baruta, Venezuela,
Doctor of Philosophy in Computer Science
Doctor of Philosophy in Computer Science Background/Rationale The program aims to develop computer scientists who are armed with methods, tools and techniques from both theoretical and systems aspects
Department of Computer Systems, Uppsala University, SWEDEN. Abstract. Uppaal is a tool suite for automatic verication of safety and
UPPAAL a Tool Suite for Automatic Verication of Real{Time Systems? Johan Bengtsson 2 Kim Larsen 1 Fredrik Larsson 2 Paul Pettersson 2 Wang Yi??2 2 1 BRICS???, Aalborg University, DENMARK Department of
Lecture 9 verifying temporal logic
Basics of advanced software systems Lecture 9 verifying temporal logic formulae with SPIN 21/01/2013 1 Outline for today 1. Introduction: motivations for formal methods, use in industry 2. Developing models
PROGRAMMABLE LOGIC CONTROLLERS Unit code: A/601/1625 QCF level: 4 Credit value: 15
UNIT 22: PROGRAMMABLE LOGIC CONTROLLERS Unit code: A/601/1625 QCF level: 4 Credit value: 15 ASSIGNMENT 3 DESIGN AND OPERATIONAL CHARACTERISTICS NAME: I agree to the assessment as contained in this assignment.
Software Modeling and Verification
Software Modeling and Verification Alessandro Aldini DiSBeF - Sezione STI University of Urbino Carlo Bo Italy 3-4 February 2015 Algorithmic verification Correctness problem Is the software/hardware system
Master of Science in Computer Science
Master of Science in Computer Science Background/Rationale The MSCS program aims to provide both breadth and depth of knowledge in the concepts and techniques related to the theory, design, implementation,
ABB i-bus EIB Logic Module LM/S 1.1
Product Manual ABB i-bus EIB Logic Module LM/S 1.1 Intelligent Installation System Contents page 1 General... 3 1.1 About this manual... 3 1.2 Product and functional overview... 3 2 Device technology...
Optimal Scheduling. Kim G. Larsen DENMARK
Priced Timed Automata Optimal Scheduling Kim G. Larsen Aalborg University it DENMARK Overview Timed Automata Scheduling Priced Timed Automata Optimal Reachability Optimal Infinite Scheduling Multi Objectives
Kim G. Larsen. Aalborg University DENMARK
Energistyring og -Optimering i Intelligente Bygninger Kim G. Larsen Arne Skou Aalborg University DENMARK CISS - Center For Embedded Software Systems Regional ICT Center (2003- ) 3 research groups Computer
Professional Organization Checklist for the Computer Science Curriculum Updates. Association of Computing Machinery Computing Curricula 2008
Professional Organization Checklist for the Computer Science Curriculum Updates Association of Computing Machinery Computing Curricula 2008 The curriculum guidelines can be found in Appendix C of the report
Ulrik M. Nyman - Curriculum Vitæ
Ulrik M. Nyman - Curriculum Vitæ Personal Information Ulrik Mathias Nyman Phone: 40 89 21 56 Doravej 45 st. th. Email: ulrik@cs.aau.dk 9000 Aalborg Born: 2nd of December 1978 Married to Tina, Father of
School of Computer Science
School of Computer Science Computer Science - Honours Level - 2014/15 October 2014 General degree students wishing to enter 3000- level modules and non- graduating students wishing to enter 3000- level
Introduction to Promela and SPIN. LACL, Université Paris 12
Introduction to Promela and SPIN LACL, Université Paris 12 Promela = Process Meta Language A specification language! No programming language! Used for system description : Specify an abstraction of the
Candle Plant process automation based on ABB 800xA Distributed Control Systems
Candle Plant process automation based on ABB 800xA Distributed Control Systems Yousef Iskandarani and Karina Nohammer Department of Engineering University of Agder Jon Lilletuns vei 9, 4879 Grimstad Norway
Fundamentals of Software Engineering
Fundamentals of Software Engineering Model Checking with Temporal Logic Ina Schaefer Institute for Software Systems Engineering TU Braunschweig, Germany Slides by Wolfgang Ahrendt, Richard Bubel, Reiner
On the Modeling and Verification of Security-Aware and Process-Aware Information Systems
On the Modeling and Verification of Security-Aware and Process-Aware Information Systems 29 August 2011 What are workflows to us? Plans or schedules that map users or resources to tasks Such mappings may
Formal Verification by Model Checking
Formal Verification by Model Checking Natasha Sharygina Carnegie Mellon University Guest Lectures at the Analysis of Software Artifacts Class, Spring 2005 1 Outline Lecture 1: Overview of Model Checking
System Modelingg Models of Computation and their Applications Axel Jantsch Laboratory for Electronics and Computer Systems (LECS) Royal Institute of Technology, Stockholm, Sweden February 4, 2005 System
Model Checking based Software Verification
Model Checking based Software Verification 18.5-2006 Keijo Heljanko Keijo.Heljanko@tkk.fi Department of Computer Science and Engineering Helsinki University of Technology http://www.tcs.tkk.fi/~kepa/ 1/24
Classes of multimedia Applications
Classes of multimedia Applications Streaming Stored Audio and Video Streaming Live Audio and Video Real-Time Interactive Audio and Video Others Class: Streaming Stored Audio and Video The multimedia content
Real Time Programming: Concepts
Real Time Programming: Concepts Radek Pelánek Plan at first we will study basic concepts related to real time programming then we will have a look at specific programming languages and study how they realize
Specification and Analysis of Contracts Lecture 1 Introduction
Specification and Analysis of Contracts Lecture 1 Introduction Gerardo Schneider gerardo@ifi.uio.no http://folk.uio.no/gerardo/ Department of Informatics, University of Oslo SEFM School, Oct. 27 - Nov.
IPC series IP camera user manual
IPC series IP camera user manual 1. Product introduction IPC series IP camera applied embedded RTOS system design, Dual-core T architecture 32-bit TI Da Vinci chip (DSP), Super storage capability, which
THE UNIVERSITY OF AUCKLAND
THE UNIVERSITY OF AUCKLAND 07.340 T07.340 EXAMINATION FOR BA BSc ETC 1995 COMPUTER SCIENCE Operating Systems ( Time allowed : THREE hours ) NOTES: Answer SIX questions. The total mark for each question
Register File, Finite State Machines & Hardware Control Language
Register File, Finite State Machines & Hardware Control Language Avin R. Lebeck Some slides based on those developed by Gershon Kedem, and by Randy Bryant and ave O Hallaron Compsci 04 Administrivia Homework
Cassandra. References:
Cassandra References: Becker, Moritz; Sewell, Peter. Cassandra: Flexible Trust Management, Applied to Electronic Health Records. 2004. Li, Ninghui; Mitchell, John. Datalog with Constraints: A Foundation
EZ DUPE DVD/CD Duplicator
EZ DUPE DVD/CD Duplicator User s Manual Version 3.0 0 TABLE OF CONTENTS Introduction 2 Setup 11 LCD Front Panel Overview 2 o Auto Start Time 11 Menu Overview 3-5 o Display Mode 12 Functions 6 o Button
15-466 Computer Game Programming Intelligence I: Basic Decision-Making Mechanisms
15-466 Computer Game Programming Intelligence I: Basic Decision-Making Mechanisms Maxim Likhachev Robotics Institute Carnegie Mellon University AI Architecture from Artificial Intelligence for Games by
From Hybrid Data-Flow Languages to Hybrid Automata: A Complete Translation
From Hybrid Data-Flow Languages to Hybrid Automata: A Complete Translation Peter Schrammel peter.schrammel@inria.fr (joint work with Bertrand Jeannet) INRIA Grenoble Rhône-Alpes INRIA large-scale initiative
A Real Time, Object Oriented Fieldbus Management System
A Real Time, Object Oriented Fieldbus Management System Mr. Ole Cramer Nielsen Managing Director PROCES-DATA Supervisor International P-NET User Organisation Navervej 8 8600 Silkeborg Denmark pd@post4.tele.dk
Software Engineering
Software Engineering Lecture 04: The B Specification Method Peter Thiemann University of Freiburg, Germany SS 2013 Peter Thiemann (Univ. Freiburg) Software Engineering SWT 1 / 50 The B specification method
Partitioning under the hood in MySQL 5.5
Partitioning under the hood in MySQL 5.5 Mattias Jonsson, Partitioning developer Mikael Ronström, Partitioning author Who are we? Mikael is a founder of the technology behind NDB
CS 141: Introduction to (Java) Programming: Exam 1 Jenny Orr Willamette University Fall 2013
Oct 4, 2013, p 1 Name: CS 141: Introduction to (Java) Programming: Exam 1 Jenny Orr Willamette University Fall 2013 1. (max 18) 4. (max 16) 2. (max 12) 5. (max 12) 3. (max 24) 6. (max 18) Total: (max 100)
Automatic Verification of the TLS HandShake Protocol
Automatic Verification of the TLS HandShake Protocol Gregorio Díaz, Fernando Cuartero, Valentín Valero and Fernando Pelayo Formal Methods Concurrency Research Group University of Castilla-La Mancha Campus
Modeling and Validation of a Data Process Unit Control for Space Applications
Modeling and Validation of a Data Process Unit Control for Space Applications Wan Hai, Huang Chongdi, Wang Yuhui, He Fei and Gu Ming Key Lab of ISS of MOE, TNList, School of Software, Tsinghua University,
Programming LEGO NXT Robots using NXC
Programming LEGO NXT Robots using NXC This text programming language derived from C language is bended together with IDE BricxCC on standard firmware LEGO Mindstorms. This can be very convenient for those,
DIABLO VALLEY COLLEGE CATALOG 2014-2015
COMPUTER SCIENCE COMSC The computer science department offers courses in three general areas, each targeted to serve students with specific needs: 1. General education students seeking a computer literacy
The Timing Definition Language (TDL)
The Timing Definition Language (TDL) Prof. Dr. Wolfgang Pree Dr. (ETH) Josef Templ Department of Computer Science Universität Salzburg cs.uni-salzburg.at MoDECS.cc PREEtec.com Overview TDL programming
Development of global specification for dynamically adaptive software
Development of global specification for dynamically adaptive software Yongwang Zhao School of Computer Science & Engineering Beihang University zhaoyw@act.buaa.edu.cn 22/02/2013 1 2 About me Assistant
introduction to program monitoring
introduction to program monitoring CS 119 part II beyond assert and print course website http://www.runtime-verification.org/course09 action standing order: sell when price drops more than 2% within 1
Advanced Programming with LEGO NXT MindStorms
Advanced Programming with LEGO NXT MindStorms Presented by Tom Bickford Executive Director Maine Robotics Advanced topics in MindStorms Loops Switches Nested Loops and Switches Data Wires Program view
My home. Mobile phone application. Instructions for use and installation. For DELTA DORE GSM transmitters and transmitter control units.
My home Mobile phone application For DELTA DORE GSM transmitters and transmitter control units Instructions for use and installation My home Alarm Heating Bedroom Dining room Kitchen Garage Absence Messages
NSPK Protocol Security Model Checking System Builder
, pp.307-316 http://dx.doi.org/10.14257/ijsia.2015.9.7.28 NSPK Protocol Security Model Checking System Builder Wang Yan, Liu Ying Information Engineering College, Zhongzhou University, Zhengzhou 450044;
Lecture Notes on Linear Search
Lecture Notes on Linear Search 15-122: Principles of Imperative Computation Frank Pfenning Lecture 5 January 29, 2013 1 Introduction One of the fundamental and recurring problems in computer science is
Formal Specification and Verification
Formal Specification and Verification Stefan Ratschan Katedra číslicového návrhu Fakulta informačních technologíı České vysoké učení technické v Praze 2. 5. 2011 Stefan Ratschan (FIT ČVUT) PI-PSC 4 2.
Expat kiss_fft gsoap smartgwt Linux Qt md5 zlig log 4cpp sqlite gcc/g++/libc/libc++ gwt
1 FAG Industrial Services GmbH Kaiserstraße 100 52134 Herzogenrath Germany +49 (0) 2407 9149-66 +49 (0) 2407 9149-59 industrial-services@schaeffler.com Web www.schaeffler.comservices All rights reserved.
Lecture 8: Safety and Liveness Properties
Concurrent Programming 19530-V (WS01) 1 Lecture 8: Safety and Liveness Properties Dr. Richard S. Hall rickhall@inf.fu-berlin.de Concurrent programming December 11, 2001 Safety Properties 2 A safety property
Center for Hybrid and Embedded Software Systems
Center for Hybrid and Embedded Software Systems College of Engineering, University of California at Berkeley Presented by: Edward A. Lee, EECS, UC Berkeley Citris Founding Corporate Members Meeting, Feb.
University of Paderborn Software Engineering Group II-25. Dr. Holger Giese. University of Paderborn Software Engineering Group. External facilities
II.2 Life Cycle and Safety Safety Life Cycle: The necessary activities involving safety-related systems, occurring during a period of time that starts at the concept phase of a project and finishes when
Compiler Construction
Compiler Construction Regular expressions Scanning Görel Hedin Reviderad 2013 01 23.a 2013 Compiler Construction 2013 F02-1 Compiler overview source code lexical analysis tokens intermediate code generation
The BSN Hardware and Software Platform: Enabling Easy Development of Body Sensor Network Applications
The BSN Hardware and Software Platform: Enabling Easy Development of Body Sensor Network Applications Joshua Ellul jellul@imperial.ac.uk Overview Brief introduction to Body Sensor Networks BSN Hardware
TMS Phone Books Troubleshoot Guide
TMS Phone Books Troubleshoot Guide Document ID: 118705 Contributed by Adam Wamsley and Magnus Ohm, Cisco TAC Engineers. Jan 05, 2015 Contents Introduction Prerequisites Requirements Components Used Related
fakultät für informatik informatik 12 technische universität dortmund Data flow models Peter Marwedel Informatik 12 TU Dortmund Germany
12 Data flow models Peter Marwedel Informatik 12 TU Dortmund Germany Models of computation considered in this course Communication/ local computations Communicating finite state machines Data flow model
VSE II - Hybrid Automata to Express Realtime Properties
From: FLAIRS-01 Proceedings. Copyright 2001, AAAI (www.aaai.org). All rights reserved. Using Hybrid Automata to Express Realtime Properties in VSE-II Andreas Nonnengart Georg Rock Werner Stephan* Deutsches
School of Computer Science
Computer Science Honours Level 2013/14 August 2013 School of Computer Science Computer Science (CS) Modules CS3051 Software Engineering SCOTCAT Credits: 15 SCQF Level 9 Semester: 1 This module gives a
RAPID PROTOTYPING OF DIGITAL SYSTEMS Second Edition
RAPID PROTOTYPING OF DIGITAL SYSTEMS Second Edition A Tutorial Approach James O. Hamblen Georgia Institute of Technology Michael D. Furman Georgia Institute of Technology KLUWER ACADEMIC PUBLISHERS Boston
How To Get A Computer Engineering Degree
COMPUTER ENGINEERING GRADUTE PROGRAM FOR MASTER S DEGREE (With Thesis) PREPARATORY PROGRAM* COME 27 Advanced Object Oriented Programming 5 COME 21 Data Structures and Algorithms COME 22 COME 1 COME 1 COME
School of Computer Science
School of Computer Science Computer Science - Honours Level - 2015/6 - August 2015 General degree students wishing to enter 3000- level modules and non- graduating students wishing to enter 3000- level
Introduction to Basics of Communication Protocol
Network Model Introduction to Basics of Communication Protocol Prof Pallapa. Venkataram Department of Electrical Communication Engineering Indian Institute of Science Bangalore 560012, India Physical Communication
EasyC. Programming Tips
EasyC Programming Tips PART 1: EASYC PROGRAMMING ENVIRONMENT The EasyC package is an integrated development environment for creating C Programs and loading them to run on the Vex Control System. Its Opening
Name: Class: Date: 9. The compiler ignores all comments they are there strictly for the convenience of anyone reading the program.
Name: Class: Date: Exam #1 - Prep True/False Indicate whether the statement is true or false. 1. Programming is the process of writing a computer program in a language that the computer can respond to
COCOVILA Compiler-Compiler for Visual Languages
LDTA 2005 Preliminary Version COCOVILA Compiler-Compiler for Visual Languages Pavel Grigorenko, Ando Saabas and Enn Tyugu 1 Institute of Cybernetics, Tallinn University of Technology Akadeemia tee 21 12618
Workload Models for System-Level Timing Analysis: Expressiveness vs. Analysis Efficiency
Workload Models for System-Level Timing Analysis: Expressiveness vs. Analysis Efficiency Nan Guan, Martin Stigge and Wang Yi Uppsala University, Sweden Uppsala University, China Complex Real-Time Systems
Compliance and Requirement Traceability for SysML v.1.0a
1. Introduction: Compliance and Traceability for SysML v.1.0a This document provides a formal statement of compliance and associated requirement traceability for the SysML v. 1.0 alpha specification, which
Runtime Enforcement of Timed Properties
Runtime Enforcement of Timed Properties Srinivas Pinisetty 1,Yliès Falcone 2, Thierry Jéron 1, Hervé Marchand 1, Antoine Rollet 3 and Omer Nguena Timo 3 INRIA Rennes - Bretagne Atlantique, France LIG,
IEC 61131-3. The Fast Guide to Open Control Software
IEC 61131-3 The Fast Guide to Open Control Software 1 IEC 61131-3 The Fast Guide to Open Control Software Introduction IEC 61131-3 is the first vendor-independent standardized programming language for
Investigating a File Transfer Protocol Using CSP and B
Noname manuscript No. (will be inserted by the editor) Investigating a File Transfer Protocol Using CSP and B Neil Evans, Helen Treharne Department of Computer Science, Royal Holloway, University of London
Sample Project List. Software Reverse Engineering
Sample Project List Software Reverse Engineering Automotive Computing Electronic power steering Embedded flash memory Inkjet printer software Laptop computers Laptop computers PC application software Software
A Logic Approach for LTL System Modification
A Logic Approach for LTL System Modification Yulin Ding and Yan Zhang School of Computing & Information Technology University of Western Sydney Kingswood, N.S.W. 1797, Australia email: {yding,yan}@cit.uws.edu.au
Softstarters. Type PST/PSTB Fieldbus communication CANopen for PST sw CU 06.00.00. 1SFC132070M0201 February 2011 1SFC132070M0201 1
Softstarters Type PST/PSTB Fieldbus communication CANopen for PST sw CU 06.00.00 1SFC132070M0201 February 2011 1SFC132070M0201 1 CANopen The CANopen protocol is a fieldbus protocol that provides full control
Multi-core architectures. Jernej Barbic 15-213, Spring 2007 May 3, 2007
Multi-core architectures Jernej Barbic 15-213, Spring 2007 May 3, 2007 1 Single-core computer 2 Single-core CPU chip the single core 3 Multi-core architectures This lecture is about a new trend in computer
Figure 1: Graphical example of a mergesort 1.
CSE 30321 Computer Architecture I Fall 2011 Lab 02: Procedure Calls in MIPS Assembly Programming and Performance Total Points: 100 points due to its complexity, this lab will weight more heavily in your
Reducing Clocks in Timed Automata while Preserving Bisimulation
Reducing Clocks in Timed Automata while Preserving Bisimulation Shibashis Guha Chinmay Narayan S. Arun-Kumar Indian Institute of Technology Delhi {shibashis, chinmay, sak}@cse.iitd.ac.in arxiv:1404.6613v2
http://aejm.ca Journal of Mathematics http://rema.ca Volume 1, Number 1, Summer 2006 pp. 69 86
Atlantic Electronic http://aejm.ca Journal of Mathematics http://rema.ca Volume 1, Number 1, Summer 2006 pp. 69 86 AUTOMATED RECOGNITION OF STUTTER INVARIANCE OF LTL FORMULAS Jeffrey Dallien 1 and Wendy
tutorial: hardware and software model checking
tutorial: hardware and software model checking gerard holzmann and anuj puri { gerard anuj } @research.bell-labs.com Bell Labs, USA outline introduction (15 mins) theory and algorithms system modeling
Design and Verification of Nine port Network Router
Design and Verification of Nine port Network Router G. Sri Lakshmi 1, A Ganga Mani 2 1 Assistant Professor, Department of Electronics and Communication Engineering, Pragathi Engineering College, Andhra
ROBOTICS AND AUTONOMOUS SYSTEMS
ROBOTICS AND AUTONOMOUS SYSTEMS Simon Parsons Department of Computer Science University of Liverpool LECTURE 3 PROGRAMMING ROBOTS comp329-2013-parsons-lect03 2/50 Today Before the labs start on Monday,