Power Analysis of Link Level and End-to-end Protection in Networks on Chip

Transcription

1 Power Analysis of Link Level and End-to-end Protection in Networks on Chip Axel Jantsch, Robert Lauter, Arseni Vitkowski Royal Institute of Technology, tockholm May 2005

2 ICA

3 ICA Overview Assumptions Experimental etup Link Level Low Power Encoding Link Level Data Protection End-to-end Data Protection Conclusion

4 ICA Boundary Conditions and Assumptions Nostrum NoC: Deflective routing with no internal buffers bit 2mm switch to switch links

5 ICA Boundary Conditions and Assumptions Nostrum NoC: Deflective routing with no internal buffers bit 2mm switch to switch links 65 nm technology scaled from UMC 18 (180 nm)

6 ICA Boundary Conditions and Assumptions Nostrum NoC: Deflective routing with no internal buffers bit 2mm switch to switch links 65 nm technology scaled from UMC 18 (180 nm) Power consumption of switch and logic is analysed with ynopsys Power Compiler

7 ICA Boundary Conditions and Assumptions Nostrum NoC: Deflective routing with no internal buffers bit 2mm switch to switch links 65 nm technology scaled from UMC 18 (180 nm) Power consumption of switch and logic is analysed with ynopsys Power Compiler Link power consumption: P Link = 1 2 α128c W V 2 ddf

8 ICA Boundary Conditions and Assumptions Nostrum NoC: Deflective routing with no internal buffers bit 2mm switch to switch links 65 nm technology scaled from UMC 18 (180 nm) Power consumption of switch and logic is analysed with ynopsys Power Compiler Link power consumption: P Link = 1 2 α128c W V 2 ddf Random, uncorrelated traffic

9 ICA Boundary Conditions and Assumptions Nostrum NoC: Deflective routing with no internal buffers bit 2mm switch to switch links 65 nm technology scaled from UMC 18 (180 nm) Power consumption of switch and logic is analysed with ynopsys Power Compiler Link power consumption: P Link = 1 2 α128c W V 2 ddf Random, uncorrelated traffic We consider faults on long wires only

10 ICA Link Level Low Power Encoding Requirements: Low area overhead Fast and short critical path Low power consumption Configuration A: Reference configuration with no low power encoding Configuration B: Bus invert encoding (P1BI) Configuration C: 2 partition bus invert encoding (P2BI)

11 ICA Delay and Clock Period for Link Level Encoding Conf. Block delay [ns] total delay frequency A witch 0.42ns 0.42 ns 2.38 GHz Link 0.08ns B witch Enc. Dec. Link 0.42ns 2.43ns 0.01ns 0.08ns 2.52 ns 0.39 GHz C witch Enc. Dec. Link 0.42ns 1.28ns 0.01ns 0.08ns 1.37 ns 0.73 GHz

12 ICA Power Consumption Normalized with Respect to Performance Conf. V dd Block witching activity % A 0.51 witch 4 links Total B 0.90 witch 4 Enc. 4 Dec 4 links Total C 0.70 witch 4 Enc. 4 Dec 4 links Total Power consumption [mw]

13 ICA Error Protection for Low Power Communication Lowering voltage saves power

14 ICA Error Protection for Low Power Communication Lowering voltage saves power Lowering voltage increases fault probability

15 ICA Error Protection for Low Power Communication Lowering voltage saves power Lowering voltage increases fault probability Error protecting codes allow to tolerate faults

16 ICA Error Protection for Low Power Communication Lowering voltage saves power Lowering voltage increases fault probability Error protecting codes allow to tolerate faults Encoders and decoders consume power

17 ICA Error Protection for Low Power Communication Lowering voltage saves power Lowering voltage increases fault probability Error protecting codes allow to tolerate faults Encoders and decoders consume power What is most power efficient:

18 ICA Error Protection for Low Power Communication Lowering voltage saves power Lowering voltage increases fault probability Error protecting codes allow to tolerate faults Encoders and decoders consume power What is most power efficient: cenario I: No error protection

19 ICA Error Protection for Low Power Communication Lowering voltage saves power Lowering voltage increases fault probability Error protecting codes allow to tolerate faults Encoders and decoders consume power What is most power efficient: cenario I: No error protection cenario II: Link level (switch-to-switch) error protection

20 ICA Error Protection for Low Power Communication Lowering voltage saves power Lowering voltage increases fault probability Error protecting codes allow to tolerate faults Encoders and decoders consume power What is most power efficient: cenario I: No error protection cenario II: Link level (switch-to-switch) error protection cenario III: Network level (end-to-end) error protection

21 ICA Link Layer Protection

22 ICA End-to-end Layer Protection

23 ICA Error Protection for Low Power cenario I: 8 8 network 80 bits payload 15 bits header cenario II: Link layer error protection Block code with DED/EC capability 20 payload bits and 5 protection bits per block; 80 payload bits 15 header bits 30 protecting bits 125 total bits cenario III: End-to-end protection Header is protected at the link layer as in cenario II Payload is protected by a block code with EC/DED capability 80 payload bits 15 header bits 24 protecting bits 119 total bits

24 ICA errors per packet Errors per Packet Errors per packet depending on the voltage c.i: No error protection c.ii: Link layer c.iii: Network layer Voltage [V]

25 ICA Power Consumption per Useful Bit Power consumption per useful bit depending on the voltage 5.5e-10 5e e-10 C.I: No error protection c.ii: Link layer c.iii: Network layer power [Joule] 4e e-10 3e e-10 2e e Voltage [V]

26 ICA Power Consumption vs. Error Rate 2.8e e-10 power consumption vs error rate c.i: No error protection c. II: Link layer c. III: Network layer power [Joule] 2.4e e-10 2e e e-10 1e Errors per packet

27 ICA Conclusion Low power bus encoding is of limited value and probably increases the overall power consumption. Link-level error protection to allow for lower voltage does not give significant improvements. End-to-end data protection decreases power consumption for 8 8 networks, with slowly increasing gain for larger networks.