Power Analysis of Link Level and End-to-end Protection in Networks on Chip

Save this PDF as:
 WORD  PNG  TXT  JPG

Size: px
Start display at page:

Download "Power Analysis of Link Level and End-to-end Protection in Networks on Chip"

Transcription

1 Power Analysis of Link Level and End-to-end Protection in Networks on Chip Axel Jantsch, Robert Lauter, Arseni Vitkowski Royal Institute of Technology, tockholm May 2005

2 ICA

3 ICA Overview Assumptions Experimental etup Link Level Low Power Encoding Link Level Data Protection End-to-end Data Protection Conclusion

4 ICA Boundary Conditions and Assumptions Nostrum NoC: Deflective routing with no internal buffers bit 2mm switch to switch links

5 ICA Boundary Conditions and Assumptions Nostrum NoC: Deflective routing with no internal buffers bit 2mm switch to switch links 65 nm technology scaled from UMC 18 (180 nm)

6 ICA Boundary Conditions and Assumptions Nostrum NoC: Deflective routing with no internal buffers bit 2mm switch to switch links 65 nm technology scaled from UMC 18 (180 nm) Power consumption of switch and logic is analysed with ynopsys Power Compiler

7 ICA Boundary Conditions and Assumptions Nostrum NoC: Deflective routing with no internal buffers bit 2mm switch to switch links 65 nm technology scaled from UMC 18 (180 nm) Power consumption of switch and logic is analysed with ynopsys Power Compiler Link power consumption: P Link = 1 2 α128c W V 2 ddf

8 ICA Boundary Conditions and Assumptions Nostrum NoC: Deflective routing with no internal buffers bit 2mm switch to switch links 65 nm technology scaled from UMC 18 (180 nm) Power consumption of switch and logic is analysed with ynopsys Power Compiler Link power consumption: P Link = 1 2 α128c W V 2 ddf Random, uncorrelated traffic

9 ICA Boundary Conditions and Assumptions Nostrum NoC: Deflective routing with no internal buffers bit 2mm switch to switch links 65 nm technology scaled from UMC 18 (180 nm) Power consumption of switch and logic is analysed with ynopsys Power Compiler Link power consumption: P Link = 1 2 α128c W V 2 ddf Random, uncorrelated traffic We consider faults on long wires only

10 ICA Link Level Low Power Encoding Requirements: Low area overhead Fast and short critical path Low power consumption Configuration A: Reference configuration with no low power encoding Configuration B: Bus invert encoding (P1BI) Configuration C: 2 partition bus invert encoding (P2BI)

11 ICA Delay and Clock Period for Link Level Encoding Conf. Block delay [ns] total delay frequency A witch 0.42ns 0.42 ns 2.38 GHz Link 0.08ns B witch Enc. Dec. Link 0.42ns 2.43ns 0.01ns 0.08ns 2.52 ns 0.39 GHz C witch Enc. Dec. Link 0.42ns 1.28ns 0.01ns 0.08ns 1.37 ns 0.73 GHz

12 ICA Power Consumption Normalized with Respect to Performance Conf. V dd Block witching activity % A 0.51 witch 4 links Total B 0.90 witch 4 Enc. 4 Dec 4 links Total C 0.70 witch 4 Enc. 4 Dec 4 links Total Power consumption [mw]

13 ICA Error Protection for Low Power Communication Lowering voltage saves power

14 ICA Error Protection for Low Power Communication Lowering voltage saves power Lowering voltage increases fault probability

15 ICA Error Protection for Low Power Communication Lowering voltage saves power Lowering voltage increases fault probability Error protecting codes allow to tolerate faults

16 ICA Error Protection for Low Power Communication Lowering voltage saves power Lowering voltage increases fault probability Error protecting codes allow to tolerate faults Encoders and decoders consume power

17 ICA Error Protection for Low Power Communication Lowering voltage saves power Lowering voltage increases fault probability Error protecting codes allow to tolerate faults Encoders and decoders consume power What is most power efficient:

18 ICA Error Protection for Low Power Communication Lowering voltage saves power Lowering voltage increases fault probability Error protecting codes allow to tolerate faults Encoders and decoders consume power What is most power efficient: cenario I: No error protection

19 ICA Error Protection for Low Power Communication Lowering voltage saves power Lowering voltage increases fault probability Error protecting codes allow to tolerate faults Encoders and decoders consume power What is most power efficient: cenario I: No error protection cenario II: Link level (switch-to-switch) error protection

20 ICA Error Protection for Low Power Communication Lowering voltage saves power Lowering voltage increases fault probability Error protecting codes allow to tolerate faults Encoders and decoders consume power What is most power efficient: cenario I: No error protection cenario II: Link level (switch-to-switch) error protection cenario III: Network level (end-to-end) error protection

21 ICA Link Layer Protection

22 ICA End-to-end Layer Protection

23 ICA Error Protection for Low Power cenario I: 8 8 network 80 bits payload 15 bits header cenario II: Link layer error protection Block code with DED/EC capability 20 payload bits and 5 protection bits per block; 80 payload bits 15 header bits 30 protecting bits 125 total bits cenario III: End-to-end protection Header is protected at the link layer as in cenario II Payload is protected by a block code with EC/DED capability 80 payload bits 15 header bits 24 protecting bits 119 total bits

24 ICA errors per packet Errors per Packet Errors per packet depending on the voltage c.i: No error protection c.ii: Link layer c.iii: Network layer Voltage [V]

25 ICA Power Consumption per Useful Bit Power consumption per useful bit depending on the voltage 5.5e-10 5e e-10 C.I: No error protection c.ii: Link layer c.iii: Network layer power [Joule] 4e e-10 3e e-10 2e e Voltage [V]

26 ICA Power Consumption vs. Error Rate 2.8e e-10 power consumption vs error rate c.i: No error protection c. II: Link layer c. III: Network layer power [Joule] 2.4e e-10 2e e e-10 1e Errors per packet

27 ICA Conclusion Low power bus encoding is of limited value and probably increases the overall power consumption. Link-level error protection to allow for lower voltage does not give significant improvements. End-to-end data protection decreases power consumption for 8 8 networks, with slowly increasing gain for larger networks.

AE64 TELECOMMUNICATION SWITCHING SYSTEMS

AE64 TELECOMMUNICATION SWITCHING SYSTEMS Q2. a. Draw the schematic of a 1000 line strowger switching system and explain how subscribers get connected. Ans: (Page: 61 of Text book 1 and 56 of Text book 2) b. Explain the various design parameters

More information

Mobile IP Network Layer Lesson 01 OSI (open systems interconnection) Seven Layer Model and Internet Protocol Layers

Mobile IP Network Layer Lesson 01 OSI (open systems interconnection) Seven Layer Model and Internet Protocol Layers Mobile IP Network Layer Lesson 01 OSI (open systems interconnection) Seven Layer Model and Internet Protocol Layers Oxford University Press 2007. All rights reserved. 1 OSI (open systems interconnection)

More information

3D Network Structures using Circuit Switches and Packet Switches for on-chip Data. Centers

3D Network Structures using Circuit Switches and Packet Switches for on-chip Data. Centers 3D Network Structures using Circuit Switches and Packet Switches for on-chip Data Centers Takahide Ikeda, Yuichi Ohsita, and Masayuki Murata Graduate School of Information Science and Technology, Osaka

More information

Protocol Stack: ISO OSI Model. Layer 2: Data Link Layer. Layer 1: Physical Layer. Layer 4: Transport Layer. Layer 3: Network Layer

Protocol Stack: ISO OSI Model. Layer 2: Data Link Layer. Layer 1: Physical Layer. Layer 4: Transport Layer. Layer 3: Network Layer Protocol Stack: ISO OSI Model CSCE 515: Computer Programming OSI Models & layer Wenyuan Xu Department of Computer Science and Engineering University of South Carolina Some slides are made by Dave Hollinger

More information

OPTICAL NETWORKS. Optical Packet Switching Optical Burst Switching. A. Gençata İTÜ, Dept. Computer Engineering 2005

OPTICAL NETWORKS. Optical Packet Switching Optical Burst Switching. A. Gençata İTÜ, Dept. Computer Engineering 2005 OPTICAL NETWORKS Optical Packet Switching Optical Burst Switching A. Gençata İTÜ, Dept. Computer Engineering 2005 Optical Packet Switching OPS 2 Optical Packet Switching An optical cross-connect (OXC)

More information

VLSI Design Verification and Testing

VLSI Design Verification and Testing VLSI Design Verification and Testing Instructor Chintan Patel (Contact using email: cpatel2@cs.umbc.edu). Text Michael L. Bushnell and Vishwani D. Agrawal, Essentials of Electronic Testing, for Digital,

More information

Simulation and Evaluation for a Network on Chip Architecture Using Ns-2

Simulation and Evaluation for a Network on Chip Architecture Using Ns-2 Simulation and Evaluation for a Network on Chip Architecture Using Ns-2 Yi-Ran Sun, Shashi Kumar, Axel Jantsch the Lab of Electronics and Computer Systems (LECS), the Department of Microelectronics & Information

More information

Transparent D Flip-Flop

Transparent D Flip-Flop Transparent Flip-Flop The RS flip-flop forms the basis of a number of 1-bit storage devices in digital electronics. ne such device is shown in the figure, where extra combinational logic converts the input

More information

Analysis (III) Low Power Design. Kai Huang

Analysis (III) Low Power Design. Kai Huang Analysis (III) Low Power Design Kai Huang Chinese new year: 1.3 billion urban exodus 1/28/2014 Kai.Huang@tum 2 The interactive map, which is updated hourly The thicker, brighter lines are the busiest routes.

More information

Analysis of Error Recovery Schemes for Networks-on-Chips

Analysis of Error Recovery Schemes for Networks-on-Chips Analysis of Error Recovery Schemes for Networks-on-Chips 1 Srinivasan Murali, Theocharis Theocharides, Luca Benini, Giovanni De Micheli, N. Vijaykrishnan, Mary Jane Irwin Abstract Network on Chip (NoC)

More information

Stress Testing Switches and Routers

Stress Testing Switches and Routers Stress Testing Switches and Routers Rev 4 How to perform a simple stress test on a Layer 2 switch device step-by-step. APPLICATION NOTE The Xena testers can verify traffic forwarding performance, protocol

More information

Local Interconnect Network Training. Local Interconnect Network Training. Overview

Local Interconnect Network Training. Local Interconnect Network Training. Overview Overview Local Interconnect Network Training History and introduction Technical features The ISO/OSI reference model and LIN Frames Message Frames Communication concept of LIN Command Frames and Extended

More information

Introduction, Rate and Latency

Introduction, Rate and Latency Introduction, Rate and Latency Communication Networks Why communicate? Necessary to support some application. Example Applications Audio communication Radio, Telephone Text communication Email, SMS (text

More information

The OSI & Internet layering models

The OSI & Internet layering models CSE 123 Computer Networks Fall 2009 Lecture 2: Protocols & Layering Today What s a protocol? Organizing protocols via layering Encoding layers in packets The OSI & Internet layering models The end-to-end

More information

SONET. Raj Jain. Professor of CIS. The Ohio State University

SONET. Raj Jain. Professor of CIS. The Ohio State University SONET Professor of CIS Columbus, OH 43210 jain@acm.org These slides are available at: http://www.cis.ohio-state.edu/~jain/cis777-00/ 1 Overview What is SONET? Physical Components SONET Protocols STS-1

More information

Networked AV Systems Pretest

Networked AV Systems Pretest Networked AV Systems Pretest Instructions Choose the best answer for each question. Score your pretest using the key on the last page. If you miss three or more out of questions 1 11, consider taking Essentials

More information

ISO OSI Reference Model for Layers. Mapping Layers onto Routers and Hosts. Encapsulation. OSI Model Concepts. Layering: Internet

ISO OSI Reference Model for Layers. Mapping Layers onto Routers and Hosts. Encapsulation. OSI Model Concepts. Layering: Internet ISO OSI Reference Model for Layers CS 194: Distributed Systems Communication Protocols, RPC Computer Science Division Department of Electrical Engineering and Computer Sciences University of California,

More information

Performance Evaluation of AODV, OLSR Routing Protocol in VOIP Over Ad Hoc

Performance Evaluation of AODV, OLSR Routing Protocol in VOIP Over Ad Hoc (International Journal of Computer Science & Management Studies) Vol. 17, Issue 01 Performance Evaluation of AODV, OLSR Routing Protocol in VOIP Over Ad Hoc Dr. Khalid Hamid Bilal Khartoum, Sudan dr.khalidbilal@hotmail.com

More information

Performance Prediction of Throughput-Centric Pipelined Global Interconnects with Voltage Scaling

Performance Prediction of Throughput-Centric Pipelined Global Interconnects with Voltage Scaling Performance Prediction of Throughput-Centric Pipelined Global Interconnects with Voltage Scaling Yulei Zhang 1, James F. Buckwalter 1, and Chung-Kuan Cheng 2 1 Dept. of ECE, 2 Dept. of CSE, UC San Diego,

More information

Internet Routing and MPLS

Internet Routing and MPLS Internet Routing and MPLS N. C. State University CSC557 Multimedia Computing and Networking Fall 2001 Lecture # 27 Roadmap for Multimedia Networking 2 1. Introduction why QoS? what are the problems? 2.

More information

NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter

NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter Description: The NTE2053 is a CMOS 8 bit successive approximation Analog to Digital converter in a 20 Lead DIP type package which uses a differential

More information

Power Reduction Techniques in the SoC Clock Network. Clock Power

Power Reduction Techniques in the SoC Clock Network. Clock Power Power Reduction Techniques in the SoC Network Low Power Design for SoCs ASIC Tutorial SoC.1 Power Why clock power is important/large» Generally the signal with the highest frequency» Typically drives a

More information

3D On-chip Data Center Networks Using Circuit Switches and Packet Switches

3D On-chip Data Center Networks Using Circuit Switches and Packet Switches 3D On-chip Data Center Networks Using Circuit Switches and Packet Switches Takahide Ikeda Yuichi Ohsita, and Masayuki Murata Graduate School of Information Science and Technology, Osaka University Osaka,

More information

Interconnection Network Design

Interconnection Network Design Interconnection Network Design Vida Vukašinović 1 Introduction Parallel computer networks are interesting topic, but they are also difficult to understand in an overall sense. The topological structure

More information

Silicon Memories. Why store things in silicon? It s fast!!! Compatible with logic devices (mostly) The main goal is to be cheap

Silicon Memories. Why store things in silicon? It s fast!!! Compatible with logic devices (mostly) The main goal is to be cheap Silicon Memories Why store things in silicon? It s fast!!! Compatible with logic devices (mostly) The main goal is to be cheap Dense -- The smaller the bits, the less area you need, and the more bits you

More information

Outline. Power and Energy Dynamic Power Static Power. 4th Ed.

Outline. Power and Energy Dynamic Power Static Power. 4th Ed. Lecture 7: Power Outline Power and Energy Dynamic Power Static Power 2 Power and Energy Power is drawn from a voltage source attached to the V DD pin(s) of a chip. Instantaneous Power: Energy: Average

More information

The Internet. Charging for Internet. What does 1000M and 200M mean? Dr. Hayden Kwok-Hay So

The Internet. Charging for Internet. What does 1000M and 200M mean? Dr. Hayden Kwok-Hay So The Internet CCST9015 Feb 6, 2013 What does 1000M and 200M mean? Dr. Hayden Kwok-Hay So Department of Electrical and Electronic Engineering 2 Charging for Internet One is charging for speed (How fast the

More information

Memory Architecture and Management in a NoC Platform

Memory Architecture and Management in a NoC Platform Architecture and Management in a NoC Platform Axel Jantsch Xiaowen Chen Zhonghai Lu Chaochao Feng Abdul Nameed Yuang Zhang Ahmed Hemani DATE 2011 Overview Motivation State of the Art Data Management Engine

More information

Switch Fabric Implementation Using Shared Memory

Switch Fabric Implementation Using Shared Memory Order this document by /D Switch Fabric Implementation Using Shared Memory Prepared by: Lakshmi Mandyam and B. Kinney INTRODUCTION Whether it be for the World Wide Web or for an intra office network, today

More information

SONET. Raj Jain. Professor of CIS. The Ohio State University. Columbus, OH Raj Jain

SONET. Raj Jain. Professor of CIS. The Ohio State University. Columbus, OH Raj Jain SONET Professor of CIS Columbus, OH 43210 http://www.cis.ohio-state.edu/~jain/ 1 What is SONET? Synchronous optical network Standard for digital optical transmission (bit pipe) Developed originally by

More information

Architectural Level Power Consumption of Network on Chip. Presenter: YUAN Zheng

Architectural Level Power Consumption of Network on Chip. Presenter: YUAN Zheng Architectural Level Power Consumption of Network Presenter: YUAN Zheng Why Architectural Low Power Design? High-speed and large volume communication among different parts on a chip Problem: Power consumption

More information

Hardware Implementation of Improved Adaptive NoC Router with Flit Flow History based Load Balancing Selection Strategy

Hardware Implementation of Improved Adaptive NoC Router with Flit Flow History based Load Balancing Selection Strategy Hardware Implementation of Improved Adaptive NoC Rer with Flit Flow History based Load Balancing Selection Strategy Parag Parandkar 1, Sumant Katiyal 2, Geetesh Kwatra 3 1,3 Research Scholar, School of

More information

Intel Atom Processor. Michelle McDaniel and Jonathan Dorn

Intel Atom Processor. Michelle McDaniel and Jonathan Dorn Intel Atom Processor Michelle McDaniel and Jonathan Dorn Introduction Completely new microarchitecture with very little in common with other Intel PC processors Designed with 3 primary goals: Dramatically

More information

VOIP over Space Networks

VOIP over Space Networks VOIP over Space Networks C. Okino, W. Kwong, J. Pang, J. Gao, and L. Clare Jet Propulsion Laboratory California Institute of Technology Presented at The Fifth Space Internetworking Workshop 2006 Hanover,

More information

Lecture Notes: Memory Systems

Lecture Notes: Memory Systems Lecture Notes: Memory Systems Rajeev Balasubramonian March 29, 2012 1 DRAM vs. SRAM On a processor chip, data is typically stored in SRAM caches. However, an SRAM cell is large enough that a single processor

More information

ESSENTIALS. Understanding Ethernet Switches and Routers. April 2011 VOLUME 3 ISSUE 1 A TECHNICAL SUPPLEMENT TO CONTROL NETWORK

ESSENTIALS. Understanding Ethernet Switches and Routers. April 2011 VOLUME 3 ISSUE 1 A TECHNICAL SUPPLEMENT TO CONTROL NETWORK VOLUME 3 ISSUE 1 A TECHNICAL SUPPLEMENT TO CONTROL NETWORK Contemporary Control Systems, Inc. Understanding Ethernet Switches and Routers This extended article was based on a two-part article that was

More information

Time-Domain Approach to Energy: Network Elements in Design

Time-Domain Approach to Energy: Network Elements in Design Time-Domain Approach to Energy: Network Elements in Design If printed, please share or recycle this slide deck after use dkh@juniper.net 1 Energy Efficiency Basics Energy Efficiency (def.) : Using less

More information

Service and Resource Discovery in Smart Spaces Composed of Low Capacity Devices

Service and Resource Discovery in Smart Spaces Composed of Low Capacity Devices Service and Resource Discovery in Smart Spaces Composed of Low Capacity Devices Önder Uzun, Tanır Özçelebi, Johan Lukkien, Remi Bosman System Architecture and Networking Department of Mathematics and Computer

More information

SPADIC: CBM TRD Readout ASIC

SPADIC: CBM TRD Readout ASIC SPADIC: CBM TRD Readout ASIC Tim Armbruster tim.armbruster@ziti.uni-heidelberg.de HIC for FAIR, Darmstadt Schaltungstechnik Schaltungstechnik und und February 2011 Visit http://spadic.uni-hd.de 1. Introduction

More information

8 by 8 dot matrix LED displays with Cascadable Serial driver B32CDM8 B48CDM8 B64CDM8 General Description

8 by 8 dot matrix LED displays with Cascadable Serial driver B32CDM8 B48CDM8 B64CDM8 General Description 8 by 8 dot matrix LED displays with Cascadable Serial driver B32CDM8 B48CDM8 B64CDM8 General Description The B32CDM8, B48CDM8 and the B64CDM8 are 8 by 8 (row by column) dot matrix LED displays combined

More information

CSE 3461: Introduction to Computer Networking and Internet Technologies. Packet Switching. Presentation G

CSE 3461: Introduction to Computer Networking and Internet Technologies. Packet Switching. Presentation G CSE 3461: Introduction to Computer Networking and Internet Technologies Packet Switching Presentation G Study: 10.5, 10.6, 12.1, 12.2, 13.1, 13.2, 18.3, 18.4 Gojko Babić 10-09-2012 The Network Core mesh

More information

Hyper Node Torus: A New Interconnection Network for High Speed Packet Processors

Hyper Node Torus: A New Interconnection Network for High Speed Packet Processors 2011 International Symposium on Computer Networks and Distributed Systems (CNDS), February 23-24, 2011 Hyper Node Torus: A New Interconnection Network for High Speed Packet Processors Atefeh Khosravi,

More information

Intercom over IP The Communications Engineer s Guide to Integrate IP into Comms

Intercom over IP The Communications Engineer s Guide to Integrate IP into Comms Intercom over IP The Communications Engineer s Guide to Integrate IP into Comms Convergence is one of the biggest topics in multimedia applications. Moving from analog production to a fully integrated

More information

Lecture 15 Seven segment display

Lecture 15 Seven segment display Lecture 5 Seven segment display Decoding BCD to seven segment The seven-segment LED display http://commons.wikimedia.org/wiki/file:seven_segment_display-gallery.png Robert R. McLeod, University of Colorado

More information

Packet Switching Technologies (Part I)

Packet Switching Technologies (Part I) Packet Switching Technologies (Part I) Adapted from notes by Prof. Dileeka Dias Department of Electronic & Telecommunication Engineering University of Moratuwa A Switching Network Circuit Switching Call

More information

Packet over SONET/SDH (POS) functional testing

Packet over SONET/SDH (POS) functional testing Packet over SONET/SDH (POS) functional testing Product note Testing the hardware components that enable efficient transport of data over SONET/SDH transmission networks Introduction Packet over SONET/SDH

More information

A Novel Low Power Fault Tolerant Full Adder for Deep Submicron Technology

A Novel Low Power Fault Tolerant Full Adder for Deep Submicron Technology International Journal of Computer Sciences and Engineering Open Access Research Paper Volume-4, Issue-1 E-ISSN: 2347-2693 A Novel Low Power Fault Tolerant Full Adder for Deep Submicron Technology Zahra

More information

Networking Virtualization Using FPGAs

Networking Virtualization Using FPGAs Networking Virtualization Using FPGAs Russell Tessier, Deepak Unnikrishnan, Dong Yin, and Lixin Gao Reconfigurable Computing Group Department of Electrical and Computer Engineering University of Massachusetts,

More information

A 2-Slot Time-Division Multiplexing (TDM) Interconnect Network for Gigascale Integration (GSI)

A 2-Slot Time-Division Multiplexing (TDM) Interconnect Network for Gigascale Integration (GSI) A 2-Slot Time-Division Multiplexing (TDM) Interconnect Network for Gigascale Integration (GSI) Ajay Joshi and Jeff Davis AIMD Research Group Georgia Institute of Technology Sponsored by: NSF # 0092450

More information

Overview of Changes to PCI Express 2.1 and 3.0

Overview of Changes to PCI Express 2.1 and 3.0 Overview of Changes to PCI Express 2.1 and 3.0 By Mike Jackson, Senior Staff Architect, MindShare, Inc. The PCISIG has released the 2.1 specification whereas the 3.0 specification release has been delayed

More information

Figure 1 120Ω 120Ω. Page 1 of 8 32# Transceiver. Transceiver. Transceiver. Transceiver

Figure 1 120Ω 120Ω. Page 1 of 8 32# Transceiver. Transceiver. Transceiver. Transceiver I. RS Bus Basics 1 RS Basic Characteristics of the Bus According to RS Industrial Bus Standards, RS industrial buses use differential method to transmit signal. This half-duplex communication bus has a

More information

18. ASIC Design Guidelines

18. ASIC Design Guidelines 18. ASIC Design Guidelines Systems Introduction The following design guidelines have been adapted from [2]: European Silicon Structures (ES2), Zone Industrielle, 13106 France. Solo 2030 User Guide, e02a02

More information

Combinational Logic Building Blocks and Bus Structure

Combinational Logic Building Blocks and Bus Structure Combinational Logic Building Blocks and Bus Structure ECE 5A Winter 0 Reading Assignment Brown and Vranesic Implementation Technology.8 Practical Aspects.8.7 Passing s and 0s Through Transistor Switches.8.8

More information

Lab 1 Physics 430 Laboratory Manual 1. LAB 1 Logic Gates, Flip Flops and Registers

Lab 1 Physics 430 Laboratory Manual 1. LAB 1 Logic Gates, Flip Flops and Registers Lab Physics 430 Laboratory Manual LAB Logic Gates, Flip Flops and Registers In this first lab we assume that you know a little about logic gates and using them. The first experiment is an exericse to help

More information

Switched Interconnect for System-on-a-Chip Designs

Switched Interconnect for System-on-a-Chip Designs witched Interconnect for ystem-on-a-chip Designs Abstract Daniel iklund and Dake Liu Dept. of Physics and Measurement Technology Linköping University -581 83 Linköping {danwi,dake}@ifm.liu.se ith the increased

More information

ISTANBUL. 1.1 MPLS overview. Alcatel Certified Business Network Specialist Part 2

ISTANBUL. 1.1 MPLS overview. Alcatel Certified Business Network Specialist Part 2 1 ISTANBUL 1.1 MPLS overview 1 1.1.1 Principle Use of a ATM core network 2 Overlay Network One Virtual Circuit per communication No routing protocol Scalability problem 2 1.1.1 Principle Weakness of overlay

More information

Circuit vs. Packet Switching

Circuit vs. Packet Switching Circuit vs. Packet Switching 1 Taxonomy of Switched Wide Area Networks WAN Telecommunication Systems intelligent core dumb nodes Circuit-Switched Networks (e.g. telephone networks) dumb core intelligent

More information

Adhoc Contributors. Nader Vijeh

Adhoc Contributors. Nader Vijeh PHY DEFINITIONS Adhoc Contributors Brad Booth Ben Brown Steve Haddock Jeff Lynch Stuart Robinson Nader Vijeh Paul Bottorff Roy Bynum David Law David Martin Geoff Thompson Some definitions for us from 802.3

More information

The Role of NMS in Intelligent Optical Networks

The Role of NMS in Intelligent Optical Networks The Role of NMS in Intelligent Optical Networks Ann Von Lehmen Telcordia Technologies May 1, 2002 An SAIC Company Intelligent Optical Networking The technology itself is maturing... Intelligence in the

More information

CN1047 INTRODUCTION TO COMPUTER NETWORKING CHAPTER 2 OSI MODEL

CN1047 INTRODUCTION TO COMPUTER NETWORKING CHAPTER 2 OSI MODEL CN1047 INTRODUCTION TO COMPUTER NETWORKING CHAPTER 2 OSI MODEL OSI Model The Open Systems Interconnection model (OSI Model) is a conceptual model that characterizes and standardizes the communication functions

More information

Computer Network. Interconnected collection of autonomous computers that are able to exchange information

Computer Network. Interconnected collection of autonomous computers that are able to exchange information Introduction Computer Network. Interconnected collection of autonomous computers that are able to exchange information No master/slave relationship between the computers in the network Data Communications.

More information

Switched Multimegabit Data Service

Switched Multimegabit Data Service CHAPTER 14 Switched Multimegabit Data Service Background Switched Multimegabit Data Service (SMDS) is a packet-switched datagram service designed for very high-speed wide-area data communications. SMDS

More information

Circuit Switching and Packet Switching

Circuit Switching and Packet Switching Chapter 9: Circuit Switching and Packet Switching CS420/520 Axel Krings Page 1 Switching Networks Long distance transmission is typically done over a network of switched nodes Nodes not concerned with

More information

1. LAN ARCHITECTURE. LAN Protocol Architecture

1. LAN ARCHITECTURE. LAN Protocol Architecture Chap. 12 LAN Technology 1 1. LAN ARCHITECTURE LAN Protocol Architecture LAN protocol architectures are specified by IEEE 802 reference model In IEEE 802 reference model, there are two separate layers corresponding

More information

surface mount components with less than 100 mil pin spacing double-sided component mounting I/O buffer w/ BS cell BS chain

surface mount components with less than 100 mil pin spacing double-sided component mounting I/O buffer w/ BS cell BS chain Boundary Scan Developed to test interconnect between chips on PCB Originally referred to as JTAG (Joint Test Action Group) Uses scan design approach to test external interconnect No-contact probe overcomes

More information

512B/513B Transcoding and FEC for 100 Gb/s Backplane and Copper Links

512B/513B Transcoding and FEC for 100 Gb/s Backplane and Copper Links 512B/513B Transcoding and FEC for 0 Gb/s Backplane and Copper Links IEEE 802.3 0 Gb/s Backplane and Copper Cable Study Group Chicago, September 13-14, 2011 Roy Cideciyan - Motivation for 512B/513B transcoding

More information

CMOS Power Consumption

CMOS Power Consumption CMOS Power Consumption Lecture 13 18-322 Fall 2003 Textbook: [Sections 5.5 5.6 6.2 (p. 257-263) 11.7.1 ] Overview Low-power design Motivation Sources of power dissipation in CMOS Power modeling Optimization

More information

EITF25 Internet Techniques and Applications L5: Wide Area Networks (WAN) Stefan Höst

EITF25 Internet Techniques and Applications L5: Wide Area Networks (WAN) Stefan Höst EITF25 Internet Techniques and Applications L5: Wide Area Networks (WAN) Stefan Höst Data communication in reality In reality, the source and destination hosts are very seldom on the same network, for

More information

Router Architecture Overview. Input Port Functions. Switching Via Memory. Three types of switching fabrics. Switching Via a Bus

Router Architecture Overview. Input Port Functions. Switching Via Memory. Three types of switching fabrics. Switching Via a Bus Router Architecture Overview Two key router functions: run routing algorithms/protocol (RIP, OSPF, BGP) forwarding grams from incoming to outgoing link Input Port Functions Physical layer: bit-level reception

More information

From Bus and Crossbar to Network-On-Chip. Arteris S.A.

From Bus and Crossbar to Network-On-Chip. Arteris S.A. From Bus and Crossbar to Network-On-Chip Arteris S.A. Copyright 2009 Arteris S.A. All rights reserved. Contact information Corporate Headquarters Arteris, Inc. 1741 Technology Drive, Suite 250 San Jose,

More information

Energy and Bandwidth Efficiency in Wireless Networks. Changhun Bae Wayne Stark University of Michigan

Energy and Bandwidth Efficiency in Wireless Networks. Changhun Bae Wayne Stark University of Michigan Energy and Bandwidth Efficiency in Wireless Networks Changhun Bae Wayne Stark University of Michigan Outline Introduction/Background Device/Physical Layer/Network Layer Models Performance Measure Numerical

More information

Protocol Hierarchies Design Issues for the Layers Connection-Oriented and Connectionless Services Service Primitives The Relationship of Services to

Protocol Hierarchies Design Issues for the Layers Connection-Oriented and Connectionless Services Service Primitives The Relationship of Services to LAYERING ARCHITECTURE OF NETWORKS Network Software Protocol Hierarchies Design Issues for the Layers Connection-Oriented and Connectionless Services Service Primitives The Relationship of Services to Protocols

More information

MultiPath TCP (MPTCP)

MultiPath TCP (MPTCP) פרויקטים בתקשורת מחשבים - 236340 - סמסטר אביב 2016 MultiPath TCP (MPTCP) MultiPath TCP (MPTCP) is an ongoing effort of the Internet Engineering Task Force's (IETF) Multipath TCP working group, which aims

More information

Course Description. Students Will Learn

Course Description. Students Will Learn Course Description The next generation of telecommunications networks will deliver broadband data and multimedia services to users. The Ethernet interface is becoming the interface of preference for user

More information

Introduction to Local Area Networks

Introduction to Local Area Networks For Summer Training on Computer Networking visit Introduction to Local Area Networks Prepared by : Swapan Purkait Director Nettech Private Limited swapan@nettech.in + 91 93315 90003 Introduction A local

More information

Communications. Wired Communications Protocols

Communications. Wired Communications Protocols Communications Wired Communications Protocols Wired Communications Goal: Allow discrete devices (processors, controllers, sensors, etc ) to communicate with each other Data transfer or synchronization

More information

Mobile IP Network Layer Lesson 02 TCP/IP Suite and IP Protocol

Mobile IP Network Layer Lesson 02 TCP/IP Suite and IP Protocol Mobile IP Network Layer Lesson 02 TCP/IP Suite and IP Protocol 1 TCP/IP protocol suite A suite of protocols for networking for the Internet Transmission control protocol (TCP) or User Datagram protocol

More information

Lecture-46 INTEL 8253: Programmable Timer

Lecture-46 INTEL 8253: Programmable Timer Lecture-46 INTEL 8253: Programmable Timer INTEL 8253 programmable Timer/ counter is a specially designed chip for µc applications which require timing and counting operation. These timing and counting

More information

ISO-OSI 7-Layer Network Architecture

ISO-OSI 7-Layer Network Architecture ISO-OSI 7-Layer Network Architecture This lecture introduces the ISO-OSI layered architecture of Networks. According to the ISO standards, networks have been divided into 7 layers depending on the complexity

More information

Understand the OSI Model

Understand the OSI Model Understand the OSI Model Part 2 Lesson Overview In this lesson, you will learn information about: Frames Packets Segments TCP TCP/IP Model Well-known ports for most-used purposes Anticipatory Set Review

More information

Transport-Layer Support for Interactive Multimedia Applications. Stephen McQuistin Colin Perkins

Transport-Layer Support for Interactive Multimedia Applications. Stephen McQuistin Colin Perkins Transport-Layer Support for Interactive Multimedia Applications Stephen McQuistin Colin Perkins Interactive Multimedia Applications Multimedia traffic comprises the majority of Internet traffic: 57% in

More information

Lecture 2: Protocols and Layering. CSE 123: Computer Networks Stefan Savage

Lecture 2: Protocols and Layering. CSE 123: Computer Networks Stefan Savage Lecture 2: Protocols and Layering CSE 123: Computer Networks Stefan Savage Last time Bandwidth, latency, overhead, message size, error rate Bandwidth-delay product Delay Bandwidth High-level run through

More information

- Hubs vs. Switches vs. Routers -

- Hubs vs. Switches vs. Routers - 1 Layered Communication - Hubs vs. Switches vs. Routers - Network communication models are generally organized into layers. The OSI model specifically consists of seven layers, with each layer representing

More information

Pope Paul VI College Information and Communication Technology

Pope Paul VI College Information and Communication Technology Pope Paul VI College Information and Communication Technology CPU - Central processing unit (CPU) is the brain of a computer which and instructions of a computer program. - It executes computer instructions

More information

Multiplexing, Circuit Switching and Packet Switching. Circuit Switching

Multiplexing, Circuit Switching and Packet Switching. Circuit Switching Multiplexing, Circuit Switching and Packet Switching Circuit Switching Old telephone technology For each connection, physical switches are set in the telephone network to create a physical circuit That

More information

1. Memory technology & Hierarchy

1. Memory technology & Hierarchy 1. Memory technology & Hierarchy RAM types Advances in Computer Architecture Andy D. Pimentel Memory wall Memory wall = divergence between CPU and RAM speed We can increase bandwidth by introducing concurrency

More information

Introduction. What is a computer network?

Introduction. What is a computer network? Introduction What is a computer network? Components of a computer network: host devices (PCs, servers, laptops, handhelds) routers & switches (IP router, Ethernet switch, WiFi routers) links (wired, wireless,

More information

Photonic Networks for Data Centres and High Performance Computing

Photonic Networks for Data Centres and High Performance Computing Photonic Networks for Data Centres and High Performance Computing Philip Watts Department of Electronic Engineering, UCL Yury Audzevich, Nick Barrow-Williams, Robert Mullins, Simon Moore, Andrew Moore

More information

Point-to-Point Vs. Shared Channel Communication In LANs Point-to-point:

Point-to-Point Vs. Shared Channel Communication In LANs Point-to-point: Point-to-Point Vs. Shared Channel Communication In LANs Point-to-point: Computers connected by communication channels that each connect exactly two computers with access to full channel bandwidth. Forms

More information

Implementing VoIP over CDMA2000 1xEV- DO Rev A; Understanding System Performance and Requirements

Implementing VoIP over CDMA2000 1xEV- DO Rev A; Understanding System Performance and Requirements Implementing VoIP over CDMA2000 1xEV- DO Rev A; Understanding System Performance and Requirements CDG Tech Forum on VoIP November 4, 2004 Ivan N. Vukovic Motorola, Inc. Global Telecommunication Systems

More information

VLSI IMPLEMENTATION OF INTERNET CHECKSUM CALCULATION FOR 10 GIGABIT ETHERNET

VLSI IMPLEMENTATION OF INTERNET CHECKSUM CALCULATION FOR 10 GIGABIT ETHERNET VLSI IMPLEMENTATION OF INTERNET CHECKSUM CALCULATION FOR 10 GIGABIT ETHERNET Tomas Henriksson, Niklas Persson and Dake Liu Department of Electrical Engineering, Linköpings universitet SE-581 83 Linköping

More information

PCI Express Controller Design Challenges at 16GT/s Richard Solomon Synopsys

PCI Express Controller Design Challenges at 16GT/s Richard Solomon Synopsys PCI Express Controller Design Challenges at 16GT/s Richard Solomon Synopsys Copyright 2015, PCI-SIG, All Rights Reserved 1 Disclaimer Presentation Disclaimer: All opinions, judgments, recommendations,

More information

Hitless Protection Switching Method for Passive Optical Network

Hitless Protection Switching Method for Passive Optical Network Hitless Protection Switching Method for Passive Optical Network Hiromi UEDA Toshinori TSUBOI Hiroyuki KASAI School of Computer Science, Tokyo University of Technology 1404-1 Katakura-cho, Hachioji-shi,

More information

RAM & ROM Based Digital Design. ECE 152A Winter 2012

RAM & ROM Based Digital Design. ECE 152A Winter 2012 RAM & ROM Based Digital Design ECE 152A Winter 212 Reading Assignment Brown and Vranesic 1 Digital System Design 1.1 Building Block Circuits 1.1.3 Static Random Access Memory (SRAM) 1.1.4 SRAM Blocks in

More information

A CDMA Based Scalable Hierarchical Architecture for Network- On-Chip

A CDMA Based Scalable Hierarchical Architecture for Network- On-Chip www.ijcsi.org 241 A CDMA Based Scalable Hierarchical Architecture for Network- On-Chip Ahmed A. El Badry 1 and Mohamed A. Abd El Ghany 2 1 Communications Engineering Dept., German University in Cairo,

More information

Board Notes on Virtual Memory

Board Notes on Virtual Memory Board Notes on Virtual Memory Part A: Why Virtual Memory? - Letʼs user program size exceed the size of the physical address space - Supports protection o Donʼt know which program might share memory at

More information

Low-Power Design Using NoC Technology

Low-Power Design Using NoC Technology By Linley Gwennap Principal Analyst May 2015 www.linleygroup.com By Linley Gwennap, Principal Analyst, The Linley Group Network-on-a-chip (NoC) technology is not just for high-performance SoC designs.

More information

Interconnection Networks. Interconnection Networks. Interconnection networks are used everywhere!

Interconnection Networks. Interconnection Networks. Interconnection networks are used everywhere! Interconnection Networks Interconnection Networks Interconnection networks are used everywhere! Supercomputers connecting the processors Routers connecting the ports can consider a router as a parallel

More information

Central Processing Unit (CPU)

Central Processing Unit (CPU) Central Processing Unit (CPU) CPU is the heart and brain It interprets and executes machine level instructions Controls data transfer from/to Main Memory (MM) and CPU Detects any errors In the following

More information

3 Address Spaces & Transaction Routing. The Previous Chapter. This Chapter. The Next Chapter

3 Address Spaces & Transaction Routing. The Previous Chapter. This Chapter. The Next Chapter PCIEX.book Page 105 Tuesday, August 5, 2003 4:22 PM 3 Address Spaces & Transaction Routing The Previous Chapter The previous chapter introduced the PCI Express data transfer protocol. It described the

More information