Power Management Solutions for Xilinx and Altera FPGAs

Transcription

1 M echnology for Innovators M An Analog roduct atalog Inside ow ropout egulators High-erformance F s... ltra-ow ropout inear egulators with oft-tart and racking... tep-own ontrollers ynchronous Buck / ontroller... Wide-Input, ow in-ount Buck ontroller... Integrated F onverters -V to -V Input, -A / onverter....-v to 0-V Input, -A / onverters... ow-ower Integrated F ontrollers.-a tep-own onverter in M-0... ual-hannel tep-own onverter with -in asycale Interface... H ower Modules nd Generation H oint-of-oad Modules... ower upply equencers -hannel ower-upply equencer and Monitor... eference esigns V IN ow ower, mall ize imple esign... V IN ow ower, ost ptimized... V IN Mid ower, imple esign...0 V IN High ower, High fficiency...0 V IN Multiple FGA esign for omplex ystems... ower Management olutions for Xilinx and Altera FGAs ingle-hip olution for partan and yclone 00 AA H A VAAIN M wo % efficient -A buck controllers and one 00-mA Adjustable output voltages to. V for buck and.0 V for Input voltage range:. V to. V Independent enable for each supply ackaging: ow profile. mm x. mm QFN mall single-chip solution Flexible sequencing V_Input 00 pf V AX IN IN IN N N N. nf. nf 0 nf 00 A Buck A Buck 00 ma I W I W A FGA Altera yclone II family Xilinx partan- family Q Q µh µh. k. k. k. k V IN. A 00 pf V. A 00 pf V AX 0 µf. 00 ma Q 00

2 ower Management olutions for FGAs ower Management olutions for Your FGA and esigns Altera Max yclone tratix, GX Max II yclone II tratix II, GX tratix III Xilinx oolunner, XA partan Family Virtex,, M oolunner-ii II, /X Virtex-II, ro, A, Virtex- Virtex- Broad portfolio including s, ontrollers, Integrated F onverters and Modules FGA reference designs, power design services, design software eminars, webcasts and application notes apid delivery samples, evaluation modules ocal application support istributor partners exas Instruments broad portfolio of high-performance power management products, local technical support and easy-touse design tools can help you differentiate your FGA-based design and speed your time to market. his issue highlights several innovative devices optimized to work with FGA and devices, such as those from leading manufacturers Xilinx and Altera. I s new power management Is and reference designs increase power efficiency and simplify design. ower Management Home age: power.ti.com ower Management olutions for Altera FGAs: ower olutions for Xilinx FGAs: e-tore for ower Management valuation Modules ower Management FGA upport mail fpgasupport@list.ti.com ower Management for FGAs ine n exas Instruments Q 00

3 ow ropout egulators High-erformance F s //////xx AA H A VAAIN M Get samples, datasheets, app reports and evaluation modules at: (eplace Anumber with 0, 0, 0, 0, 0, 0, or 0 Input voltage range:. V to. V Fixed output voltages:. V to. V and adjustable. V to.0 V ated output current: 00 ma to. A table with ceramic output capacitor _V M output noise, 00 Hz to 00 khz Fast startup time (0 µs) Accuracy: % over load/line/temp Very high : 0 khz and 0 0 khz roduces low-noise power for sensitive analog functions ses smaller, less expensive ceramic capacitors Altera tratix II GX, MAX II Xilinx Virtex-, oolunner II ow-noise F applications and V power supplies ypical evice pecifications evice I V (mv) N ackages 0 00 ma /N 0 00 ma 0 00 ma, W 0 0 ma M, 0 00 ma A 0, AK, N (. V) 0. A 0, AK V IN IN 0 µf N µf V ltra-ow ropout inear egulators with oft-tart and racking xx AA H A VAAIN M Get samples, datasheets, app reports and evaluation modules at: rogrammable soft-start/tracking capabilities Input voltage range: 0. V to. V Bias voltage range:. V to. V ltra-low V IN V : mv A ltra-low V BIA V :. V A utput voltages: 0. V to. V % accuracy over load/line/temp table with any/no output capacitor Guaranteed min/max current limit ow-noise high-current linear solution ess board space than switching solution Fewer components than switching solution Altera yclone II, tratix II, tratix II GX, tratix III Xilinx partan- family, Virtex- ore and I power supplies and V power supplies ypical evice pecifications evice I (A) V (mv) tartup 0. oft-tart 0. rack oft-tart V V BIA IN µf BIA µf IN N BIA 0 G ptional V G V exas Instruments Q 00 ower Management for FGAs ine n

4 tep-own ontrollers.-v to -V Input, ynchronous Buck / ontroller 00 AA H A VAAIN M Input operating voltage range:. V to V utput voltage down to 0. V with % reference accuracy ynchronous rectification for high efficiency hree selectable short-circuit thresholds Hiccup recovery from short-circuit condition Integrated bootstrap drivers for N-hannel MF Internal soft-start Fewer external components, simplifies design Minimized switching losses improves efficiency p to -A power supply possible with the 00 Minimizes power dissipation in fault condition, automatically restarts when fault is removed Altera yclone II, tratix II, tratix II GX, tratix III Xilinx partan- family, Virtex- ore and I power supplies V hutdown 00 NAB M V HV 0 W B V V High-performance, low-cost solution Allows for a single-input power solution, no separate power supply needed to power the controller rovides power supply flexibility without adding circuit complexity B.-V to -V Input, ow-in ount Buck ontroller 000 AA H A VAAIN M Get samples, datasheets, app reports and evaluation modules at: oft-start provides smooth, well controlled power up imple configuration minimal external components Altera yclone II, tratix II, tratix II GX, tratix III Xilinx partan- family, Virtex- ore and I power supplies.-v to -V operation Voltage mode control with feed-forward compensation 00-mV voltage reference: % accuracy Internal under-voltage lockout rogrammable frequency: khz to 00 khz rogrammable overcurrent protection Frequency synchronization losed loop soft-start Integrated driver 000 / IN M GV V IN N V Wide-input range for use in many applications Voltage feed forward great line regulation, fast transient response rogrammable features allows flexible design; frequency, overcurrent protection, under-voltage lockout ower Management for FGAs ine n exas Instruments Q 00

5 Integrated F onverters.-mhz, -V to -V Input, -A / ynchronous Buck onverter AA H A VAAIN M Input voltage range:.0 V to.0 V wo -A (.-A peak) integrated MFs provide synchronous rectification Adjustable/synchronizable switching frequency to. MHz utput voltage adjustable down to 0. V ower good, enable, adjustable slow-start, current limit, thermal shutdown and % accuracy upported by free witcherro design software High frequency allows use of a smaller inductor and capacitor to save board space High efficiency greater than 0% arge current source from a small board space.-v to 0-V Input, -A and -A onverters 0, 0 AA H A VAAIN M or 0 Input voltage range:. V to 0 V ynchronous-buck for high efficiency Adjustable output voltage down to 0. V ower good, enable, adjustable slow-start, current limit, thermal shutdown 0 out-of-phase switching 0 and 0 are footprint compatible Fixed 0 khz, 00 khz, or adjustable switching frequency ther ow-voltage WIF evices* V IN ange I art Number (V) (A) Frequency ackage 0 to p to 00 khz 0H 0 to p to 00 khz H 0 to p to 00 khz H 00 to p to 00 khz H * ame feature set as Input Altera yclone II, tratix II, tratix II GX, tratix III Xilinx partan- family, Virtex- ore and I power supplies Many integrated protection and performance features to protect the system 0 and 0* YN WG /NA VBIA M WG /NA YNH VBIA Mid-Voltage WIF evices V IN ange I art Number (V) (A) ompensation ackage 0. to 0 xternal H x. to 0 Internal* H 0. to 0 xternal H * Fixed output versions available (.,.,.,. and. V) VN WA A M B H G H B VN Input Voltage utput utput Voltage Accommodates high inrush currents Greater than 0% efficiency % regulation accuracy over temperature educes input bulk capacitance size perates at up to 00 khz for smaller passive components *Note: 0 and 0 are footprint compatible. Altera yclone II, tratix II, tratix II GX, tratix III Xilinx partan- family, Virtex- ore and I power supplies exas Instruments Q 00 ower Management for FGAs ine n

6 ow-ower Integrated F onverters.-a tep-own onverter in M-0 0x AA H A VAAIN M Input voltage range:. V to.0 V utput current: up to. A with up to % efficiency -µa (typ) quiescent current, 0.-µA shutdown FM power-save mode for light loads.-mhz fixed frequency WM operation possible Adjustable output voltage range: 0. V to V IN 00% duty cycle mode oft-start limits in-rush current ackaging: 0-pin M uitable for -to -cell alkaline or -cell i-ion onserve battery capacity High efficiency over entire load range mall inductors Ideal for low-noise applications Altera Max II, yclone II Xilinx oolunner-ii, partan- family V I 0x. V to V W W µf N M 0 mall Inductor. µh V 0. V to V I /. A µf ual-hannel tep-own onverter with -in asycale Interface 00 AA H A VAAIN M Input voltage:. V to V utput voltage: 0. V to.0 V (adj.) utput currents: 00 ma and 00 ma (00) fficiency: % (max) asycale: simple one wire interface to adjust output voltage (dynamic voltage scaling) Fixed frequency operation:. MHz 0 out-of-phase operation ower-save mode (FM/WM) or forced WM, 00% duty cycle oft-start ackaging: mm x mm 0-pin QFN mall solution size asycale digital programming allows simple V educed input capacitance No external compensation required Altera Max II, yclone II Xilinx oolunner-ii, partan- family V IN. V to V 0 µf ynamic Voltage caling in, 0 or 00 mv teps N_ N_ M/AA 0 W F_ W AJ. µh. µh 0 µf V :. V 00 ma V :. V 00 ma 0 µf wo Independent utputs ower Management for FGAs ine n exas Instruments Q 00

7 ower Modules nd Generation H oint-of-oad Modules H0xx, H0xx AA H A VAAIN M urborans technology.% output regulation p to 0% smaller footprint martync synchronization Wide input voltage (. V to V) Auto-rack sequencing b-free/oh compliant ypical evice pecifications Input Voltage utput Voltage utput urrent Model (V) (V) (A) H00W. to. 0. to. H00/W. to 0. to. H00W. to. 0. to. H00/W. to 0. to. H00/W. to. 0. to. 0 H00F. to 0. to.0 0 H00/W. to 0. to. 0 H00W. to. 0. to. H00/W. to 0. to. H00W. to. 0. to. 0 H00W. to 0. to. 0 H00W. to 0. to. 0 V00W to 0. to. 0 s reduce development costs and save B space: equencing easily solved with Auto-rack technology martync synchronization for input cap reduction/easier filtering urborans technology for high transient load applications p to x reduction in output capacitors Faster transient response table with ultra-low caps.% tolerance meets specs of FGA core Altera tratix II, tratix II GX, tratix III Xilinx Virtex- Wireless infrastructure elecom Networking ervers Mass storage martync rack urborans V I Inhibit V % 0.0 W (ptional) 00 µf (equired) 0 rack YN V I ense H0W V INH/V ense V AJ [A] % 0.0 W (equired) % 0.0 W (ptional) ense V 0 00 µf (equired) ense A exas Instruments Q 00 ower Management for FGAs ine n

8 ower upply equencers -hannel ower upply equencer and Monitor 00 AA H A VAAIN M elecommunications switches servers Networking equipment est equipment Any system requiring sequencing of multiple voltage rails equencing and monitoring of up to voltage rails All rails monitored and updated every 0-µs.-mV resolution equencing of up to three digital outputs for power-on-reset and other functions nder- and over-voltage threshold per rail I interface for configuration and monitoring Microsoft Windows GI for configuration and monitoring Flexible rail shutdown upply voltage:. V ow power consumption: 00 µa,.0 V Intuitive Windows-based GI for easy sequencing Allows setting of dependent and independent rails aves fault information if power is suddenly disrupted AI0 ow ropout egulator AI / onverter AI ow ropout egulator AI / onverter / onverter. V Hard rive - AI AI0 AI AI AI AI AI AI AI 0 k o ystem V_IM 0 k 0 A A/ Inputs???? Interface 00 V nable utputs Interrupt utput 0 IN N0 N N N N N N N IN o ystem ow ropout egulator ow ropout egulator AI. V. V /µ Memory - - V_IM AI / onverter.0 V Interface - AI ower Management for FGAs ine n exas Instruments Q 00

9 eference esigns eference esign for yclone II and partan- Family V IN ow ower, mall ize, imple esign ual 0x Integrated high and lowside Fs to achieve up to % conversion efficiency ypical quiescent current: µa oad current:. A perating input voltage range:. V to.0 V fficient generation of lower power I/ voltages witching frequency:. MHz reduces inductor size and output voltage ripple Adjustable and fixed output voltages ower save mode operation at light load currents 00% duty cycle for lowest dropout Internal soft-start ower rail sequencing High efficiency over wide-load range mall solution size V IN V IN 00.0 µf W. A pf W k N µf M 0 µf 00 pf k 0.0 µf W. A W N µf M 0 µf. V V IN N V eference esign for yclone II and partan- Family V IN ow ower, ost ptimized 000 ownload reference design schematic and BM at: www-s.ti.com/sc/techlit/bv00 pf J V 000 pf 0. k k 0 pf k 0. µf V 000 V IN M V F = 00 khz Q N00I 0. µf 00 pf 0.0 K k Q i0by B0 0 µf µh V 0 k MMBZ0B 0 µf. V J 0.0 µf. A imple -pin wide V IN controller for voltage rails needing less than A Voltage feed-forward for improved response to line transients NAB/ 0 k 0 0 pf. K 00 K. K. V V N 0-0K. V_/. K V pf 000 pf 0. k 0 pf k 000 V IN M V F = 00 khz. V_/ 0. µf 0. µf 00 pf.0 K k Q IM0 B0 0 µf µh 0 µf 0 J. A. K 0 pf. k 0 00 K exas Instruments Q 00 ower Management for FGAs ine n

10 eference esigns eference esign for tratix II, tratix II GX, yclone II, Virtex-, partan- Family V IN, Mid ower, imple esign 0 ownload reference design schematic and BM at: www-s.ti.com/sc/techlit/bv00 V IN = V µf ull p. or V 0 µf 0.0 k WG_. 0W B H V H WG G VBIA YN 0 NA A M VN wr 0. µf.0 µf Q FA 0. 0 µh 00 pf 00 µf V =. V V 0 0. µf 0 out-of-phase operation minimizes input capacitance.-v WIF power good pin sequences.-v rail 00-mΩ MF switch integrated for high efficiency at A ses external lowside MF for synchronous operation utput voltage: adjustable down to 0. V with % accuracy witcherro design software an be upgraded to A with the 0 pin-compatible device Integrated F minimizes board space µf 0.0 k 0 µf k 0.0 k 00 pf WG_. 0 pf. k 0W B H V H WG G VBIA YN 0 NA A M VN wr nf 00 pf 0. µf. k. k. k.0 µf 0.0 k.00 k 00 pf Q FA nf 0 µh pf V =. A V -. A 00 µf V =. V V 0. µf eference esign for tratix II, tratix II GX, yclone II, Virtex-, partan- Family V IN, High ower, High fficiency 00 ownload reference design schematic and BM at: www-s.ti.com/sc/techlit/bv00 Input operating voltage range:. V to V eference 0. V ±% Voltage mode control electable short-circuit protection thresholds re-bias output safe Fixed switching frequency of 00 khz Internal soft-start Bootstrapped drivers for N-hannel MF Adaptive anti-cross conduction Internal bootstrap diode. V. K. V V. K 0 0 k 00 K. K. V J 0 pf 00 K MMBZ0B 00 K. K 0 pf 00 K. V 00 K µf 00 K 00 pf 00 pf pen. V_/ 00 pf 00 pf pen V V 00 0 N HV. W 0. µf M B V V B wr 0. µf. µf 0.0 K 0.0 K 00 N HV 0. W 0. µf M B V V B wr 0. µf. µf Q i0y Q i0y Q i Q i 0 µf. µh 00 µf. µh 0 µf 0. K 00 µf 0 µf. V. V_/ V N 0-0K. K. V 00 µf. V J J. A. A calable up to 0 A per rail asy power sequencing with N pin Highly efficient conversion to voltage rails 0 ower Management for FGAs ine n exas Instruments Q 00

11 eference esigns eference esign for Virtex- -V Multiple FGA esign for omplex ystems H00W ownload reference design schematic and BM at: www-s.ti.com/sc/techlit/v0 0 µf 0 µf V Adj. martync (in) 0 µf Auto- rack Board Area 0. in / V ense. kω V ense V IN H00W V.0 0 A ff. % Inhibit/V V AJ 000 µf mω to 0 mω set = 0. kω - % oad.0 0 A Maximum 000 µf mω to 0 mω 0 µf power modules for: Higher current (up to 0 A) implified sequencing with Auto-rack sequencing Fast transient response with urborans technology Frequency synchronization with martynch 00 for termination power ower supply for external flash memory ower supply for fan control esign used in Xilinx evaluation platform M0 s reduce development costs and save B space: equencing easily implemented with Auto-rack technology martync synchronization for input cap reduction/easier filtering urborans technology for high transient load applications p to x reduction in output capacitors Faster transient response table with ultra-low caps.% tolerance meets specs of FGA core N V 00 pf V 0G. V V ms elay martync ontrol 0 khz with hase hift M. µf. µf µf 0 µf 0 µf V V Adj. V Adj. martync (in) µf Auto- rack V IN Board Area 0. in / V ense. kω V ense H00W V. A ff. % Inhibit/V martync (in) µf Auto- rack V IN Board Area 0. in V AJ. kω V ense H00W V. A ff. % Inhibit/V / V ense V AJ 00GQ 00 µf eramic set =. kω - % VQN V oad 00 µf eramic set =. kω - % oad VQ. V 0 µf mω to 0 mω. A Maximum 00 pf mω to 0 mω V 0, A. A Maximum 0. µf VF wr VN 0 µf 0 µf 0 µf IN G owergood µf µf N 0 BIA. V 0 kω. V Flash eset 0.00 µf ms ower p =. kω - % =. kω - % IN G owergood µf µf N 0 BIA. V 0 kω. V Fan ontrol ption 0.00 µf ms ower p =. kω - % =. kω - % exas Instruments Q 00 ower Management for FGAs ine n

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