How to Detect Open Leads in CMOS ICs

Transcription

1 Test Circuit for Vectorless Open Lead Detection of CMOS ICs Masaki Hashizume, Masahiro Ichimiya, Akira Ono, Hiroyuki Yotsuyanagi :Department of Computer Systems Engineering, Institute of Technology and Science, The Univ. of Tokushima Tokushima , Japan :Department of Telecommunications Takuma National College of Technology Takuma-cho Mitoyo, ,Japan Abstract In this paper, a test circuit for a test method is proposed, with which open leads of CMOS logic ICs are detected without generating test input vectors. Open leads are detected by means of supply current of the test circuit that flows when an AC voltage signal is provided to targeted leads with test probes as a stimulus. It is examined by some experiments whether open leads will be detected with the test circuit. The empirical results show that open leads of CMOS ICs will be detected within 5µsec after attachment of test probes to targeted leads. 1. Introduction When ICs are soldered on a print circuit board(pcb) with the state-of-the-art technology, opens have occurred more frequently. In this paper, it is discussed how to detect opens between pads and leads of CMOS ICs that occur when the ICs are soldered on a PCB. Most of the opens are caused by missing solder. The opens are called "open leads" in this paper. An open lead may not be always detected by functional tests, since it may not be estimated correctly which logic value is provided from the open lead, that is, the faulty effects generated by the excitation may not be estimated precisely. An open lead may generate faulty behavior, which is modeled as a delay fault. However, delay faults are difficult to be detected by functional tests and opens may not be detected. In order to detect open leads, various kinds of test methods have been proposed(1-8). They are classified into two types: the one is based on image processing techniques and the other is to detect open leads electrically. Recently, fine-pitched ICs have been often used for fabricating logic circuits. The usage makes it more difficult to detect open leads by test methods based on image processing techniques. Because it is very difficult to examine the connectivity between leads and pads precisely by means of image processing techniques. Until now, two kinds of test methods have been proposed for detecting open leads in CMOS logic circuits electrically by supplying either magnetic or electric field from the outside of a CUT(circuit under test)(5,7). In the method proposed in (5), a signal induced by magnetic field is measured. It is determined by means of the measured signal whether an open lead occurs. However, the induced signal is very small. It leads to difficulty of the robust test. The other one is a test method based on supply current of a CMOS logic circuit, which flows when AC electric field is supplied to the circuit(7). We proposed the supply current test method. If an open lead occurs, voltage of the open lead will change in time by means of the electric field and larger quiescent supply current will appear than one of defect-free circuits. This phenomenon is used for detecting open leads in the test method. Since the change in the supply current is larger than the induced signal used in (5), robust tests for open leads will be realized by the supply current test method. We have shown the feasibility of tests based on the test method by some experiments. In the experiments, SMT SSIs are used and inserted open leads are detected by the test method(7). Also, we have proposed electric field generation methods that would be effective for detecting open leads of CMOS LSIs(9,1). However, the test method proposed in (7) needs preparing test input vectors before testing. Also, in order to detect open leads by the test method, the test vectors should be provided to a CUT. The test input generation and the application may result in high test cost. Thus, we have developed a new test method and proposed a test circuit for the test method(11). Also, we have shown that an open lead can be detected with the test circuit by some experiments in (11). Only one lead can be tested at a time with the test circuit proposed in (11). Since many targeted ICs have

2 many leads, if the test circuit is used in tests of the ICs, it will take a long test time. Thus, we attempted to revise the test circuit so that more than one lead can be tested simultaneously. We propose a revised test circuit in this paper. Also, we examined test speed of the test circuit by some experiments. We show the experimental evaluation results in this paper. When it is examined whether an open occurs at a targeted lead, as shown in Fig.2, AC voltage v S (t) is provided to a targeted lead with a test probe, which is specified by Eq.(2). v S (t)=v S sin(2πft) (2) where the amplitude of v S (t), V S, is a value in the range from V i1 to V i2 defined in Fig Open lead detection method Input/output voltage characteristic of a CMOS inverter gate is shown in Fig.1. As shown in Fig.1(b), when V i is either V DD or GND, no supply current will flow into the gate. However, if V i is in the range specified by Eq.(1), large supply current will flow, since both pmos and nmos transistors in the gate turn on. V i1 <V i <V i2 (1) We use this electrical characteristic to detect open leads. Fig.2 Our primitive test circuit. (a)measurement circuit (b)dc characteristic curve Fig.1 DC characteristics of CMOS inverter gate. Our primitive test circuit is shown in Fig.2. In this section, we will describe the principle of our open lead detection with the test circuit. The test circuit consists of a CMOS inverter gate INV, a resistor R S, a diode D 1 and an AC voltage source v S (t). INV is used as a sensor to detect abnormal voltage of a targeted lead. Logic gates other than an inverter gate will be able to be used instead of INV. The test circuit is almost the same as the one proposed in (11). In our new test circuit, D 1 is added to the test circuit proposed in (11) so that large negative voltage can not be supplied by v S (t) to the targeted lead and INV, since IC#i-1, IC#i and INV may be damaged by the negative voltage. When an open does not occur at the targeted lead, input voltage of INV, v INV (t), will depend on the output voltage of a lead of IC#i-1 independently of v S (t). As a result, i DDT (t) will be almost equal to owing to the property of inverter gates shown in Fig.1. On the other hand, when an open occurs at the targeted lead, v INV (t) will depend on v S (t). If v INV (t) is within V i1 and V i2 in Fig.1(b), large supply current, i DDT (t), will flow into the inverter gate owing to the characteristics shown in Fig.1. If Eq.(3) is satisfied, it is determined that an open occurs at the targeted lead. i DDT (t) I tht (3) where I tht is a threshold value for determining whether the targeted circuit is faulty or not. I tht is estimated from variation of quiescent supply current of the inverter gate used in the test circuit. An example of open lead detection is shown in Fig.3. A targeted lead in Fig.3 is lead a of IC#i. If the open lead occurs in the circuit, v INV (t) will change with v S (t) independently of output logic value of IC#i-1. Since V S is within V i1 and V i2 that are defined in Fig.1, elevated supply current will flow into INV. Examples

3 of the waveforms of v S (t), v INV (t) and i DDT (t) are shown in Fig.4. As shown in Fig.4, large i DDT (t) flows owing to the property shown in Fig.1 and the open lead will be detected by Eq.(3). when v S (t) is greater than the L output voltage of IC#i-1. However, INV will recognize v INV (t) as L regardless of the AC current. Thus, supply current of INV is almost zero and large i DDT (t) will not flow. As a result, the circuit is judged as defect-free from Eq.(3). The other phenomenon is shown in Fig.5(b). In this case, H is provided to the targeted lead. As shown in Fig.5(b), when v S (t) is smaller than the H output voltage of IC#i-1, current will flow into v S (t) through the test probe. However, v INV (t) is recognized as H even if the current flows, since v INV (t) is not below V i2 with R S. Thus, i DDT (t) will not satisfy Eq.(3) and the circuit is judged as defect-free. Fig.3 Open lead detection with test circuit in Fig.2. (a)when L is provided to a targeted lead Fig.4 i DDT (t) waveform in our test. When an open does not occur at the targeted lead, elevated i DDT (t) will not flow, since the input voltage of INV is almost equal to either V DD or GND. The phenomena are summarized in Fig.5. The phenomenon is shown in Fig.5(a) which occurs when L is provided to the targeted lead in the defect-free circuit. In this case, small AC current will flow between v S (t) and the GND terminal of IC#i-1 through R S and the test probe as shown in Fig.5(a) (b)when H is provided to a targeted lead Fig. 5 Test of defect-free circuit. This test method does not need test input generation process. It is apparent from Fig.5. As shown in Fig.5, when an open does not occur, large i DDT (t) will not

4 flow independently of logic values outputted to a targeted lead. On the other hand, if an open occurs at the targeted lead, large i DDT (t) that satisfied Eq.(3) will flow as shown in Fig.4 independently of logic values outputted to the targeted lead. Thus, this test method is a vectorless test one. It means that test input generation and test input application are not needed. If a test probe is attached at high pressure to a targeted lead, the open may disappear only in the test and an open lead may not be detected. Thus, a test probe is attached to a targeted lead at low pressure in our test method. This test probe attachment will result in high contact resistance. Thus, the test circuit is modeled as an equivalent circuit including the contact resistance R c in Fig.6. It is apparent that even if R c is large, only currents that flow through R S will become small and the open lead will be detected without any errors. It means that an open lead will be detected even if a test probe is attached to a targeted lead at low pressure. It stems that an open lead is detected by means of supply current of INV. gate is added to each of the targeted leads. Open leads are attempted to be detected by measuring i DDT (t) in the test circuit. R T in Fig.7 is indispensable. The reason is apparent from Fig.8. When H and L are outputted from terminals b and d of IC#i-1 in Fig.8 respectively, elevated supply current will flow along a path Path3 in Fig.8. If R T s are not inserted, IC#i-1 may be broken by the current, since the current is very large. Thus, R T is inserted to an input terminal of each inverter gate as shown in Fig.7. Fig.7 Test circuit for parallel tests. Fig.6 Tests by low pressure probing. 3. Test circuit for open lead detection Open leads will be detected with the test circuit shown in Fig.2. However, only one lead can be tested at a time with the test circuit. There are a large number of leads to be targeted. Thus, if the circuit is used for testing an IC having a large number of leads, it takes a long test time. It means that the circuit in Fig.2 will be used for diagnosis and not be used for detection. In order to detect an open lead in a short time, we attempted to revise the test circuit so that more than one lead could be tested simultaneously. Our developed test circuit is shown in Fig.7. As shown in Fig.7, a sub-circuit consisting of R T and an inverter Fig.8 Necessity of R T.

5 4. Evaluation by experiments We have examined experimentally whether an open lead could be detected with our test circuit. The circuit shown in Fig.9 is used as a CUT. In our experiments, an open is inserted to the circuit. R S and R T used in our experiments are 1kΩ and 1kΩ, respectively. The frequency of v S (t) is 1kHz. i DDT (t) is measured with a current probe. V DD is 5V. A test probe set used in our experiments is shown in Fig.1(a) that is built by using an IC socket. The test probes are attached to the targeted leads by placing the test probe set upon the targeted IC as shown in Fig.1(b). (a)test probe set (b)installation of test probe set Fig.1 Test probe set used in our experiments. 4 CK 2 iddt(t) 2 1 [ma] vs(t) 1.75 [V] -.64 Fig.9 Circuit under test. Waveforms of i DDT (t) in a defect-free CUT and a CUT having an open lead are shown in Fig.11(a) and Fig.11(b), respectively. As shown in Fig.11(a), even if v S (t) is provided to the targeted leads, large i DDT (t) will not flow. On the other hand, when the open occurs, large i DDT (t) flows as shown in Fig.11(b). Also, the elevated supply current flows when CK is H level and when CK is L level. It means that test vector application is not needed in our tests. As shown in Fig.11(b), by providing v S (t) whose amplitude is 1.75V, the open lead is detected. The amplitude is smaller than V DD. Thus, by using this test method, open leads will be detected with no damage caused by the application of v S (t). 4 CK 2 iddt(t) 2 1 [ma] vs(t) 1.75 [V] t [ms] (a)defect-free circuit t [ms] (b)faulty circuit having open lead at lead b Fig.11 Measured waveforms of CUT in Fig.9. We examined the test speed of our test circuit experimentally. In our experiments, we changed the frequency of v S (t) and examined I DD that is the

6 maximum current of i DDT (t). The results are shown in Fig.12. As shown in Fig.12, the test speed depends on R T. R T of high resistance will reduce test speed of our test circuit, because voltage of the open lead can not become large quickly. The open lead is detected with v S (t) of 2kHz and R T of 1kΩ. It means that the open lead is detected within 5 µsec with our test circuit. IDD[mA] RT=3MΩ RT=1MΩ RT=1MΩ RT=3kΩ RT=3kΩ RT=1kΩ fs[khz] Fig.12 I DD for v S (t) of each frequency. We have not examined test speed of our test circuit for fine-pitched LSIs. We think that almost the same experimental results will be obtained in tests of such LSIs as in ones of this CUT. In order to examine the test speed, we must develop a test probe set that is suitable for the tests. It remains as future works to build a test probe set for such LSIs and to examine the test speed. 5. Conclusion In this paper, we propose a test circuit to detect open leads of CMOS ICs. The test circuit realizes open lead detection without test input vector generation. Only AC voltage is provided to targeted leads through test probes with the test circuit as a stimulus during a test. Open leads are detected by means of supply current of the test circuit. We show by some experiments that open leads of CMOS SSIs will be detected with the test circuit within 5 µsec. The experimental results promise us that a portable test equipment for open lead detection will be developed. It remains as future works to develop test probes for fine-pitched LSIs and to examine test speed for such LSIs. thank Mr. Yusuke Fujioka for his experimental evaluation. This work is supported in part by Japan Society for the Promotion of Science under Grant-in Aid for Scientific Research (C) (No ). References (1)C.Vaucher, "Electrical Test: Where are we and Where are We Going?", Proc. of ECWC8, pp.h (1999). (2)Ted. T. Turner, "Capacitive Leadframe Testing", Proc. of ITC-96, p.925(1996). (3)Jack Ferguson, "High Fault Coverage of In-Circuit IC Pin faults with a Vectorless Test technique Using Parasitic Transistors", Proc. of ITC-96, p.926(1996). (4)Joe Wrinn, "Two new Techniques for Identifying Opens on Printed Circuit Boards: Analog Junction Test and Radio Frequency Induction Test", Proc. of ITC-96, p.927(1996). (5)Anthony J. Suto, "Analog AC Harmonic Method for Detecting Solder Opens", Proc. of ITC-96, p.928(1996). (6)Stig Oresjo, "Unpowered Opens Test with X-Ray Laminography", Proc. of ITC-96,p.926(1996). (7)M.Hashizume et al., "Supply Current Test for Pin Opens in CMOS Logic Circuits", Proc. of ICEP1, pp (21). (8)M.Hashizume et al., "Power-off Vectorless test Method for Pin Opens in CMOS Logic Circuits", Proc. of ICEP2,pp (22). (9)M.Hashizume, et al., "Electric Field Application method effective for Pin Open Detection Based on Supply Current in CMOS Logic Circuits", Proc. of ICEP3,pp.75-8(23). (1)M.Takagi, et al., "AC Electric Field for Detecting Pin Opens by Supply Current of CMOS ICs", Proc. of ICEP24,pp (24). (11)A.Ono, M.Hashizume, M.Ichimiya, H. Yotsuyanagi : Open Lead Detection of CMOS ICs by Low Pressure Probing, Proc. of ICEP27, pp (27). Acknowledgement We would like to thank Mr. Kouji Imagawa for his discussion on this test method. Also, we would like to