HARDWARE SPECIALIZATION OF MACHINE-LEARNING KERNELS: POSSIBILITIES FOR APPLICATIONS AND POSSIBILITIES FOR THE PLATFORM DESIGN SPACE

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1 HARDWARE SPECIALIZATIO OF MACHIE-LEARIG KERELS: POSSIBILITIES FOR APPLICATIOS AD POSSIBILITIES FOR THE PLATFORM DESIG SPACE (Invted) Kyong Ho Lee, Zhuo Wang, and aveen Verma Prnceton Unversty ABSTRACT Ths paper consders two challengng trends affectng lowpower sensng systems: () the applcatons of nterest ncreasngly nvolve embedded sgnals that are very complex to analyze; and (2) the platforms themselves face elevatng constrants n terms of energy and possbly cost. Motvated by the complextes of analyzng the applcaton sgnals, we emphasze the benefts of data-drven approaches. Most notably, these approaches are based on machne learnng, as opposed to tradtonal DSP. We consder how the algorthms lend themselves to specalzed sgnal-analyss platforms. Hardware specalzaton s wellregarded as an approach to address ssues of computatonal effcency, performance, and capacty, thus playng a key role n leveragng Moore s Law. However, we descrbe how hardware specalzaton of machne-learnng kernels, ths tme wth an explct focus on error reslence, can also play a powerful role n enablng system-wde fault tolerance, thereby adng Moore s Law on another dmenson. Index Terms accelerators, embedded systems hardware reslence, machne learnng.. ITRODUCTIO Generally speakng, the physcal systems that we are nterested n sensng can be extremely complex; these mght nclude physologcal systems n the context of medcal devces [], hgh-value nfrastructure n the context of ndustral montorng [2], or large-scale cvl structures n the context of smart ctes [3]. Constructng analytcal models of the embedded sgnals to enable nferences from sensor data s very often unvable. In such scenaros, datadrven sgnal-analyss technques can play a valuable role [4]. Data-drven technques use sensor data, not only to probe a physcal system of nterest, but also as means of constructng models for sgnal analyss. Such technques have ganed hgh relevance n embedded sensng applcatons for two reasons: () powerful frameworks for data-drven modelng and analyss have recently emerged from the doman of machne learnng, and (2) sensor networks, composed of low-power nodes, have made data, that s potentally hghly nformatve, avalable on a large scale. As a result of these factors, sensng nodes have begun to ncorporate data-drven approaches to solve complex embedded-sgnal-analyss problems [5, 6, etc.]. Asde from analyss of applcaton sgnals, data-drven technques have also shown great promse for addressng modelng and predcton challenges on the platform-desgn and -valdaton levels. Ths tme, the strength of these technques has been n representng a platform s own states, when such states are too complex to model analytcally. Successful applcatons of machne-learnng methods for managng workloads n hgh-performance computng platforms [7], thermal fluctuatons n voltage-performance scalable systems [8], bug exposure n post-slcon valdaton methodologes [9], etc., are all drvng exploratons of how such methods can be more extensvely leveraged. Whle machne-learnng methods appear to have strong relevance to the desgn of low-power embedded systems, n fact they have been nvestgated from the perspectve of ultra-low-power systems on only a very lmted level. The purpose of ths paper s to motvate such a perspectve. Ths nvolves three aspects. The frst aspect s that machnelearnng frameworks have not been formulated wth lowpower system constrants n mnd. As a result, even very smple frameworks can pose lmtng challenges n terms of computatonal energy, memory requrements, etc. The Second aspect s that by precsely consderng how machnelearnng frameworks mght be used wthn sensng applcatons, archtectures for low-power devces can explot hardware specalzaton, yeldng a strong lever for overcomng oppostons to the system constrants. Once sutably ncorporated wthn the hardware archtecture, the thrd aspect s that machne-learnng methods can ad the operaton and desgn-space tradeoffs for the platform tself. In partcular, we look at the urgent challenge of hardware faults, whch can arse due to aggressve manufacturng and/or low-energy crcut-operaton regmes. In both cases, the challenges assocated wth modelng the faults and/or ther manfestatons wthn the embedded data makes machne learnng a potentally powerful approach. 2. MACHIE-LEARIG KERELS FROM THE PERSPECTIVE OF PLATFORM EERGY Machne learnng s a rch doman, offerng a wde range of frameworks. Broadly, the varous frameworks take dfferent approaches to statstcal modelng n an effort to address ether the behavor of the system beng modeled or the manner n whch an algorthm mght use the resultng model. For the purposes of ths paper, we focus on a class of frameworks called dscrmnatve methods. These take a

2 smplstc approach, n that they attempt to model a system as a partcular varable of nterest. Despte ths smplcty, dscrmnatve methods form the bass for powerful classfcaton/regresson algorthms, whch can address a wde range of emergng sensor applcatons [0]. Below, we provde an analyss of the energy lmtatons posed by such frameworks and how these can be addressed ether through mathematcal approxmaton or reformulaton. For analyss and llustraton at the kernel-functon level, we focus on support-vector-machne (SVM) classfers, whch have ganed popularty due to ther computatonal effcency and tranng robustness. The SVM s a dscrmnatve supervsed-learnng framework that performs classfcaton on data, whch has been represented as a feature vector. Durng a tranng phase t uses tranng feature vectors to construct a decson boundary n the feature space that optmally separates regons assocated wth dfferent classes of nterest; though bnary classfcaton s most common, mult-class algorthms can be acheved va varous extensons []. The decson boundary s represented by selectng nstances of tranng feature vectors that le near the edges of the dfferent class-data dstrbutons. These nstances are called the support vectors, and are used to compute the classfcaton decson functon. The challenge that typcally arses s that for the strongest classfcaton kernels, the energy of computng the decson functon scales wth the complexty of the support-vector model. Fg. llustrates ths energy scalng for a radalbass-functon (RBF) kernel, profled on an MSP430 mcroprocessor, wth respect to two dmensons that represent model complexty: () feature-vector dmensonalty, and (2) sze of the support-vector set. As a result, n many applcatons, where hgh-order models are requred, the energy of the kernel domnates. The ponts correspondng to two representatve medcal-sensor applcatons are shown emphaszng the mportance of both dmensons. Fg. : Energy of SVM classfcaton on MSP430 showng scalng wth sze of the support-vector set and the dmensonalty of feature vectors [2]. To address the kernel energy, a varety of approaches have been consdered. In [3] a very low-energy formulaton for smple lnear kernels s used. Eq. gves the SVM decson functon, showng how a lnear kernel permts a factorzaton wheren the computaton over all support vectors s reduced va summaton to a sngle vector (sv s a support vector, x s the nput data s feature vector, and all other parameters are from tranng). Ths overcomes the energy scalng shown n Fg. wth respect to the sze of the support-vector set. Let sv = [ sv sv sv ] and x [ x x x ] = 2 M = 2 K( sv, x)α y b = ( sv x)α y b = = sv α y x b = = w x b The challenge s that n many applcatons, lnear kernels show poor performance compared to non-lnear kernels; non-lnear kernels beneft from the ablty to represent much more flexble decson boundares n the feature space. To enhance the performance of weak, low-energy kernels, a powerful technque s adaptve boostng (adaboost) [4]. It constructs a strong kernel by teratvely combnng weak kernels n a lnear combnaton; the weghts for the lnear combnaton are determned through data-drven tranng. The resultng classfer s substantally more flexble, yeldng low-energy and greatly enhanced performance n many applcatons [5]. Rather than approxmatng a desred decson boundary through boostng, another approach s to approxmate the decson functon assocated wth a strong kernel. In [6], non-lnear SVM kernels, ncludng RBF and sgmod, are mplemented n a logarthmc number system. Ths has the beneft of reducng multplcatons to addtons and subtractons, and, thanks to the reduced precson requrements enabled by logarthmc compresson, the logarthmc transformatons can be realzed va look-up tables and/or pece-wse lnear approxmatons. Although approxmatons can substantally mtgate energy consumpton, they do not overcome the problematc energy scalng wth respect to model complexty shown n Fg.. To address ths an alternate formulaton, that uses ncreased dmensonalty to create a lnear kernel from a non-lnear kernel, has been proposed [2]; as wth the lnear-kernel formulaton n Eq., ths enables factorzaton to overcome energy scalng wth the sze of the support-vector set. Eq. 2 shows the formulaton appled to polynomal kernels. Though these kernels offer only an ntermedate level of flexblty compared to RBF kernels, they have shown to yeld comparable performance for many applcatons, and they substantally outperform lnear kernels [2]. The lnear formulaton s acheved by convertng the support vectors nto matrces. The matrx formulaton has the drawback that energy-scalng wth feature-vector dmensonalty s exacerbated (e.g., scalng s quadratc for a second-order polynomal kernel); however, as descrbed n [7] several generc and applcaton-specfc technques M

3 Let sv = = [ sv sv sv ] and x [ x x x ] 2 M = 2 K( sv, x)α y b 2 = ( β sv x + γ ) α y b = γ sv β = 2 M 2 = sv β M [ x x x ] β sv [ γ β sv β sv β sv ] x α y b γ sv β = 2 M 2 = β sv M [ x x x ] β sv [ γ β sv β sv β sv ] α y x b 2 M 2 M [2nd order polynomal kernel] x 2 M 2 x M x x M Precomputed (M+ x M+ matrx) (2) Fg. 2 shows an accelerator-based mcroprocessor that was proposed for SVM-based sgnal-classfcaton applcatons [8]. The SVM accelerator (SVMA) and actve-learnng data-selecton (ALDS) modules compute classfcaton kernels and tranng-data selecton metrcs for actve learnng [9], respectvely; supportng modules, such as a data-path unt for arthmetc and a CORDIC for non-lnear transformatons, are also ncluded. Arbter exst for dmensonalty reducton. As a result, the formulaton enables substantal energy savngs, between n medcal-sensor applcatons [2]. 3. EXPLOITIG ALGORITHMIC STRUCTURE FOR SPECIALIZATIO The prevous secton noted that a key lmtaton of machnelearnng kernels s how ther energy scales wth model complexty. Ths secton looks at algorthmc structure at the applcaton level to explore archtectures for hardware specalzaton that can address kernel energy. An mportant observaton s that sgnal-analyss algorthms can typcally be dvded nto two parts: () sgnal feature extracton, to sutably represent the data n preparaton for classfcaton; and (2) classfcaton, through the applcaton of a hghorder model. Table shows energy proflng results from two representatve applcatons pertanng to medcal-sgnal analyss. What we see s that datasets requrng hgh-order models for analyss lead to a scenaro wheren classfcaton energy substantally domnates. We note, however, that classfcaton can be acheved through varous kernel functons. Feature extracton, on the other hand, requres a hgh degree of programmablty, as t s closely ted to the applcaton and applcaton sgnals of nterest. Its energy, on the other hand, s far lower. These factors suggest that feature-extracton computatons should preferably be delegated to hghly-programmable hardware (.e., CPUs) whle classfcaton should be delegated to specalzed, energy-effcent co-processors. In an ntegrated mcroprocessor, ths motvates an accelerator-based archtecture. Table. Feature extracton and classfcaton energy; Classfcaton energy domnates over feature extracton. Fg. 2: Archtecture block dagram of an accelerator-based mcroprocessor [8]. An mportant concern wth a hardware-specalzed archtecture, however, s the need for selectve confgurablty. As dscussed n the prevous secton, there exst a wde range of kernels and kernel formatons, leadng to a varety of mplementaton tradeoffs. A noteworthy characterstc of data-drven modelng frameworks s that the optmal desgn-pont parameters can depend strongly on the applcaton data. To enable optmzaton of the desgnpont parameters, the classfcaton accelerator n [8] enables confgurablty of the kernel functon and ts formulaton. Table 2 shows the performance as well as computatonal complexty (represented by cycle count) and memory requrements for two medcal-sensor applcatons over the confguraton space. Fg. 3 shows the de photo and the chp summary along wth the measured energy from two medcal-sensor applcatons. As shown, the use of hardware accelerators dramatcally reduces the overall energy (by 44 and 62, respectvely) thanks to the algorthmc structure of the applcatons. 4. DATA-DRIVE HARDWARE RESILIECE THROUGH MACHIE-LEARIG KERELS An archtecture based on hardware accelerators, as above, s motvated by asymmetry n how specfc computatons mpact the overall energy; namely, hardware specalzaton s benefcal for certan computatons f reducng the energy of those computatons has substantal leverage for reducng the overall energy of the applcaton. In ths secton, we show that wth machne-learnng kernels, a new drver for hardware specalzaton may also be reslence;.e., reslence of machne-learnng kernels can be leveraged to substantally mprove the overall platform reslence.

4 Table 2: Illustraton of performance, computatonalcomplexty, and memory usage of kernels over confgurablty space [8]. Fg. 3: De photo, chp summary, and measured applcaton energy of accelerator-based mcroprocessor [8]. Asymmetry based on reslence characterstcs s n fact a prncple that has been exploted prevously. Prmarly, ths has been n the context of control-flow errors n a processor, whch have a more severe mpact on system reslence compared to data-computaton errors. Recognzng ths has motvated specalzed archtectures and desgn methodologes. In the case of archtectures, ether portons of a mcroprocessor [20] or entre cores [2] have been explctly desgned to be error reslent for handlng control flow, whle the remander of the mcroprocessor or cores have been desgned to have relaxed relablty for data computaton. In the case of desgn methodologes, approaches have been developed wheren the control-crtcal logc paths of a mcroprocessor are syntheszed to have ncreased tmng margn [22]. Asde from control-flow errors, hardware asymmetry has also been used n sgnalprocessng archtectures to effcently explot redundancy through the use of statstcal error correcton. Algorthmc nose tolerance (AT) [23] employs a prmary, fullprecson processor that s allowed to make errors alongsde a reduced-precson estmator. Whle the full-precson processor thus benefts from relaxed desgn constrants, the estmator permts error detecton and correcton, through the the use of the estmator output. Other approaches for explotng redundancy have also been proposed [23]. The avalablty of an error-protected machne-learnng accelerator enables an alternate approach. Below we present an overvew and smulaton results for data-drven hardware reslence (DDHR) [24]. In ths approach, learnng enables adaptatons n a classfcaton decson functon. Ths overcomes the mpact of bt-level errors orgnatng from hardware faults n the feature-extracton processor, but also n all prevous stages (ncludng data-acquston and dataconverson blocks). Thanks to the kernel-functon formulatons and hardware-specalzed archtectures presented prevously, the energy and area costs of a reslent classfer mplementaton can be substantally reduced; DDHR thus targets the hardware assocated wth acqurng and dervng sgnal features, whch are becomng ncreasngly complex and dverse wth the expandng scope of applcatons. 4. Overvew of the Approach Fg. 4 llustrates the concept of DDHR. A key premse of machne-learnng systems s that the data used durng the learnng (tranng) phase must exhbt the same statstcs as the data expected durng the analyss phase. In the approach shown, the tranng features are thus obtaned from the error-prone feature-extracton subsystem. Usng ths data, an error-aware model can be constructed for classfcaton. The error-aware model s meant to model the feature-data varances caused due to the applcaton sgnals, but also those caused due to hardware faults. However, model constructon for a supervsed-learnng classfer requres tranng labels n addton to tranng data. It has been shown [24], that f a temporary error-free detector can be mplemented wthn the archtecture, ths can be used to estmate the tranng labels; though the resultng estmates devate from ground truth, smulaton experments show that they can enable performance very close to that of the errorfree system. It should be noted that the requrement of preservng the sgnal statstcs mples that, generally, only statc faults can be addressed through ths approach; transent fault sources can cause the statstcs to be altered, compromsng the performance of the traned model. Fg. 4: Illustraton of DDHR concept. Temporary systems for modelng and labelng enable constructon of an error-aware model from error-affected tranng data. The error-aware model s then used by a real-tme classfer. Fg. 5 llustrates the mpact of hardware faults on feature data and shows how an error-aware model addresses ths. The data shown s obtaned from gate-level smulatons

5 performed on an EEG-based sezure-detecton processor that has been syntheszed to an ASIC standard-cell lbrary. To smulate faults, the syntheszed netlst has been edted to nsert logc-gate swtchng faults and SRAM bt-cell faults at random. As shown, the orgnal decson boundary, traned usng error-free feature vectors, exhbts poor dscrmnaton of the error-affected sezure and non-sezure feature data. An error-aware model, traned usng the erroraffected feature vectors s also shown, llustratng that good dscrmnaton of the resultng data s now acheved. Fg. 5: EEG-sgnal feature data for a sezure detector (plotted n 2D usng prncple component analyss) showng (a) the error-free dstrbuton and (b) the dstrbuton after ntroducng errors (n 20% of the memory cells). Fg. 6 llustrates the mpact of the error-aware model n restorng the performance of the classfcaton decson functon. The frst hstogram shows the classfer output wth an orgnal model when usng error-free feature data as the nput. As shown, good separaton between sezure and non-sezure classes s observed. The second hstogram shows the mpact of njected faults, llustratng the loss of classfer separablty. Fnally, the thrd hstogram shows the output wth an error-aware model when usng error-affected feature data as the nput. As shown separablty performance close to that of the orgnal system s restored. Fg. 6: Hstograms of the classfer output for a sezure detector (a) wthout errors (baselne), (b) wth memory errors, and (c) wth errors, but usng an error-aware model. 4.2 Analyss and Demonstratons To demonstrate the DDHR concept, two bomedcal sensng applcatons are consdered: electroencephalogram (EEG) based epleptc sezure detecton [25] and electrocardogram (ECG) based arrhythma detecton [26]. The EEG and ECG sgnals used are obtaned from the CHB-MIT Scalp EEG Database and the MIT-BIH Arrhythma Database, respectvely [27]. For both applcatons, the performance metrcs consdered are true postve rate (TP), true negatve rate (T), false postve rate (FP), and false negatve rate (F); these are wdely used metrcs for evaluatng bnary classfcaton. For both applcatons, an RTL descrpton of the featureextracton processor s developed and syntheszed to an ASIC standard-cell lbrary to obtan a gate-level netlst. Two types of hardware faults are then njected at a controlled rate nto the netlst. The frst fault type s SRAM bt-cell faults, wheren the data stored n the SRAM s statcally assgned a value of logc or 0 wth 50% probablty. The second fault type s logc-gate swtchng faults, wheren the output nodes of logc gates are statcally ted to logc or 0 wth 50% probablty. Snce the precse locaton of faults can strongly nfluence the manfestatons of errors, ten nstances of error-njected netlsts are smulated n all cases, wth errors njected at random locatons. Fg. 7 shows the error statstcs of the feature-data derved from gate-level smulatons, llustratng sever mpact of the njected faults. The frst plot shows the magntude of the resultng errors by plottng the RMS value of the errors normalzed to the RMS value of the true features; n many cases, the errors exceed the actual feature values. The second set of plots show the error hstogram dstrbutons for four representatve features; the hstograms exhbt hghly-rregular dstrbutons. Error RMS / Sgnal RMS Dmenson # Fg. 7: (a) RMS error by feature (normalzed to the RMS of the true feature value) and (b) representatve error dstrbutons from four features (cases shown correspond to 20% memory bt-cell errors n the sezure detector). Despte the large error magntudes and rregular error dstrbutons n the resultng feature data, the overall performance of the systems s substantally restored thanks to the use of an error-aware model. Fg. 8 shows the performance (averaged over all ten cases at each fault rate) followng SRAM bt-cell error njecton. As shown, the performance of the orgnal model rapdly degrades, whle that of the error-aware model s essentally restored to errorfree levels. Fg. 8 shows the performance followng logcgate error njecton. The performance exhbts hgher varance for ths fault type; thus results for all ten cases are shown at the respectve fault rates where the performance of the error-aware model begns to degrade. As shown, at these fault rates the orgnal model exhbts degraded performance, whle the error-aware model exhbts restored performance (note, T and F results are not shown as they exhbt no notable degradaton).

6 True Postve (%) SRAM bt-cell Error Rate (%) True Postve (%) SRAM bt-cell Error Rate (%) Fg. 8: Performance followng SRAM error njecton of (a) sezure detector and (b) arrhythma detector. Fg. 9: Performance followng logc-gate error njecton of (a) sezure detector wth fault rate of 0-4 errors/node (0 runs), and (b) arrhythma detector wth fault rate of 7x0-2 per node (0 runs). 5. COCLUSIOS Electroncs for embedded applcatons face a challengng two-sded constrant. On one hand, applcatons are rasng the need to perform analyss over ncreasngly complex sensor data. On the other hand, the hardware platforms themselves are plagued by system-resource lmtatons such as energy consumpton, memory sze, and hardware reslence. Gven the opposng tradeoffs typcally faced by platforms, methods that smultaneously address these constrants can have substantal mpact. Machne-learnng approaches can play such a role by enablng new algorthmc capabltes for handlng applcaton sgnals, whle at the same tme rasng opportuntes for hardware specalzaton due to algorthmc structure. Such specalzaton can be leveraged to not only enable substantal energy savngs, but also to enable system-wde fault tolerance. 6. ACKOWLEDGEMETS Ths work was supported n part by Systems on anoscale Informaton fabrcs (SOIC), one of the sx SRC STARnet Centers, sponsored by MARCO and DARPA. 7. REFERECES. Csavoy, G. Molnar, and T. Denson, Creatng support crcuts for the nervous system: Consderatons for bran-machne nterfacng, VLSI Symp. Crcuts, Jun. 2009, pp G. Sartan and C. Purdy, Transformng a 00-year-old ndustry through analytcs, Teradata. 3. A. Maeda, Technology nnovatons for smart ctes," VLSI Symp. Crcuts, June 202, pp Verma, K. H. Lee, and A. Shoeb, Data-drven approaches for computaton n ntellgent bomedcal devces: A case study of EEG montorng for chronc sezure detecton, J. Low Power Electron. Appl., vol., no., pp , Apr J. Park, et al., A 92mW real-tme traffc sgn recognton system wth robust llumnaton adaptaton and support vector machne, IEEE J. Sold State Crcuts, vol. 47, no., pp , ov Verma, A. Shoeb, J. Bohorquez, J. Dawson, J. Guttag, and A. P. Chandrakasan, A mcropower EEG acquston SoC wth ntegrated feature extracton processor for a chronc sezure detecton system, IEEE J. Sold-State Crcuts, vol. 45, no. 4, pp , Apr A. S. Ganapath, Predctng and optmzng system utlzaton and performance va statstcal machne learnng, Ph.D. dssertaton, Unv. Cal., Berkeley, CA, Y. Ge and Q. Qu, Dynamc thermal management for multmeda applcatons usng machne learnng DAC, Jun. 20, pp A. DeOro, et al., Machne learnng-based anomaly detecton for postslcon bug dagnoss, DATE, March P. Dubey, Recognton, mnng and synthess moves computers to the era of tera, Technology at Intel Magazne, Feb C. W. Hsu and C. J. Ln, A comparson of methods for multclass support vector machnes, IEEE Trans. eural etworks vol.3, no.2, pp , Mar K. H. Lee, S.-Y. Kung, and. Verma, Improvng kernel-energy tradeoffs for machne learnng n mplantable and wearable bomedcal applcatons, ICASSP, May 20, pp D. Anguta, A. Bon, and S. Rdella, A dgtal archtecture for support vector machne: theory, algorthm, and FPGA mplementaton, IEEE Tran. eural etworks, vol 4, no. 5, pp , Sep R. E. Schapre and Y. Freund Boostng: Foundatons and Algorthms, Cambrdge, MA, USA: MIT Press, E. I. Shh, Reducng the computatonal demands of medcal montorng classfers by examnng less data, Ph.D. dssertaton, MIT, Cambrdge, MA, F. M. Khan, M. G. Arnold, and W. M. Pottenger. Fnte precson analyss of support vector machne classfcaton n logarthmc number systems, IEEE EUROMICRO Symp.Dgtal System Desgn (DSD), pp , Sept K. H. Lee, S.-Y. Kung, and. Verma, Low-energy Formulatons of Support Vector Machne Kernel Functons for Bomedcal Sensor Applcatons J. Sgn. Process. Syst., Apr DOI 0.007/s K. H. Lee and. Verma, A V general-purpose bomedcal processor wth confgurable machne-learnng accelerators for hghorder, patent-adaptve montorng, ESSCIRC, 202, pp K. Brnker, Incorporatng dversty n actve learnng wth support vector machnes, n MACHIE LEARIG-ITERATIOAL WORKSHOP THE COFERECE, vol. 20, no., 2003, p Y. Yetm, M. Martonos, and S. Malk, "Extractng useful computaton from error-prone processors for streamng applcatons", DATE, March L. Leem, et al., Error-reslent system archtecture for probablstc applcatons, IEEE/ACM DATE, Mar J. Sartor and R. Kumar, Archtectng Processors to Allow Voltage/Relablty Tradeoffs, CASES, Oct Shanbhag, et al., Stochastc computaton, DAC, June Verma, et al., Enablng system-level platform reslence through embedded data-drven nference capabltes n electronc devces, ICASSP, March A. Shoeb, et al., Applcaton of machne learnng to epleptc sezure detecton, ICML, June E. Ubeyl, ECG beats classfcaton usng multclass support vector machnes wth error correctng output codes, Dgtal Sgnal Processng, May Physoet.