[Bar92] G. Barret. Occam3 Reference Manual. InMos Limited, marzo [BaTe97] V.Barbati e L.Tesauro. Master s Thesis, CEFRIEL, luglio 97.

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1 Bibliografia [BaChJu97] F. Balarin, M. Chiodo, A. Jurecska et all., Hardware software co-design of Embedded System: A Polis Approach, Kluwer Accademic Press, giugno [Bar92] G. Barret. Occam3 Reference Manual. InMos Limited, marzo [BaTe97] V.Barbati e L.Tesauro. Master s Thesis, CEFRIEL, luglio 97. [BeBo97] S. Bernardi e A. Bottiroli, Relazione Progetto EDA, CEFRIEL, marzo 97. [BEKSS95] [BeHeEr] [BHLM92] T. Benner, R. Ernst, I. Konenkamp, P. Schuler, H:-C. Schaub, A Prototyping System for Verification and Evaluation in Hardware-Software Cosynthesis, Technical Report, Politecnico di Braunschweig, T. Benner, J. Henkel, R. Ernst, Hardware Generation and Partitioning Effects in the COSYMA system, Technical Report, Politecnico di Braunschweig. J. Buck, S. Ha, E: A: Lee, D. G. Messerschmitt, Ptolemy: A Framework for Simulating and Prototyping Heterogeneous Systems, International Journal of Computer Simulation, University of California, Berkeley, agosto [BoDeMa97] I. Bolsens, H. De Man, Hardware/Sofware Co-design of Digital Telecommunication Systems, Proceedings of the IEEE, Vol. 85, No. 3, marzo [COBo94] P. Chou, R. Ortega, G. Borriello The Chinook Hardware/Software Co-Synthesis System, Technical Report, University of Washington, Seattle, maggio [Co91] R. S. Cok, Parallel Programs for the transputer,

2 [CWBo94] P. Chou, E. Walkup, G. Borriello, Scheduling Issues in the Co-Synthesis of Reactive Real-Time Systems, Technical Report, University of Washington, Seattle, aprile [DeMi93] G. De Micheli, Synthesis of Digital Circuits, Stanford University, [De89] A. L. Decegama; The Technology of parallel processing, [FaGa96] [Fi96] [GaKu83] [GDWL93] [GFV94] N. Fan e D.D.Gajski, Estimation of Schedules for Control/Datapath Pipelining, Technical Report, University of California, Irvine, agosto S. Filipponi, Metodi per la specifica ed analisi temporale di sistemi dominati dal controllo, PhD thesis, luglio 1996 D. D. Gajski e R. Kuhn, Guest Editors Introduction: New VLSI Tools IEEE Computer, vol. 16, no. 12, pp , dicembre D. D. Gajski, N. D. Dutt, A. C-H Wu, S. Y-L Lin, HIGH-LEVEL SYNTHESIS: Introduction to Chip and System Design, Kluwer Academic Publishers, D.D.Gajski. e S. Narayan F. Vahid, Specification and design of embedded sytems, Prentice-Hall, [Gra94] Mentor Graphics, Mentor graphics reference manual, [HaSt71] A. Hashimoto e J.Stevens, Wire Routing by Optimiwing Channel Assignment within Large Apertures, The 8 th Design Automation Conference Workshop, pp , [HaVrZa96] V. C. Hamaker, Z. G. Vranesic, S. G. Zaky, Computer Organization, [HCLH90] [HEHB95] [Hi85] C-Y. Huang, Y-S Chen, Y-L Lin e Y-C Hsu, Data Path Allocation Based on Bipartite Weighted Matching, Proceedings of the 27 th Design Automation Conference pp , J. Henkel, R. Ernst, U. Holtmann, T. Benner, Adaptation of Partitioning and High-Level Syntheisis in Hardware/Software Co-Synthesis, Technical Report, Politecnico di Braunschweig, P. Hilfinger, A High-level Language and Silicon Compiler for Digital Signal Processing, Proc. of IEEE 1985 Custom Integrated Circuits Conference, Portland, OR, USA, maggio 1985, pp

3 [HoJe81] R. W. Hockney, C. R. Jesshope, Parallel Computers, [Ho93] [KaKa90] [Ka95] [KeLi70] [KiGV83] [KuDeMi89] [KuPa87] [JeOBr92] [JMSW91] [LeHL89] [Lim95] [LM93] U. Holtmann, Hierarchical Behavioural Representation in the Braunschwieg Synthesis System BSS, IFIP Workshop on Application of Synthesis and Simulation, Lenggries, S. P. Kartashev, S. I. Kartashev, Supercomputing Systems: architectures, design and performance, A. P. Kalavade, System-Level Codesign of Mixed Hardware-Software Systems, Ph.D Thesis, University of California, Berkeley, pp , K. H. Kernighan e S. Lin, An Efficient Heuristic Procedure for Partitiong Graph, Bell System Technical Journal, vol. 49, no.2, pp , febbraio S. Kirkpatrick, C.D. Gelatt, M. P. Vecchi, Optimization by Simulated Annealing, Science, vol No. 4598, pp , D. Ku, G. De Micheli, Optimal synthesis of control logic from behavioural specification, F. J. Kurdahi, A. C. Parker, REAL: A Program for Register Allocation, Procedeeings of 24 th Design Automation Conference, pp , A. A. Jerraya, K. O Brien, I. Park, B. Courtois, Towards system level modeling and synthesis, Proc. VLSI 92, India, febbraio R. Jain, A. Mujumdar, A. Sharma e H. Wang, Empirical Evaluation of Some Hig- Level Synthesis Scheduling Heuristics, Proceedings of the 28 th Design Automation Conference pp , J. Lee, Y. Hsu e Y. Lin, A New Integer Linear Programming Formulation for the Scheduling Problem in Data-Path Synthesis, Proceedings of the International Conference on Computer-Aided Design, pp 20-23, SGS-Thompson Microelectronics Limited, Occam 2.1 Reference Manual, maggio E.A.Lee e D.G.Messerschmitt, An overview of the Ptolemy project Technical Report, University of California, Berkeley, gennaio [MoKi97] M. Morris, C. R. Kime, Logic and computer design fundamentals,

4 [PaKn89] [PaKy91] P. G. Paulin e J. P. Knight, Force Directed Scheduling for the Behavioural Synthesis of ASIC s, IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems, vol. 8, no. 6, pp , giugno I-C. Park e C-M. Kyung, Fast and Near Optimal Scheduling in Automatic Data Path Synthesis, Proceedings of the 28 th Design Automation Conference pp , [Pe88] D. L. Perry. VHDL. McGraw-Hill, Inc [PM87] [Polis] [Ptolemy] [Rabaey91] [SLSG] D. Pountain e D. May, A tutorial introduction to occam programming, Technical Report ISBN X, InMos, Gran Bretagna, S. Bhattacharyya et all, An Overview of the Ptolemy Project, University of California, Berkeley, marzo M. Rabaey, C: Chu, P. Hoang, M. Potkonak, Fast Prototyping of datapathintensive Architectures, IEEE Design And Test of Computers, pp , giugno [SSL+92] E.M.Sentovich, K. J. Singh, L. Lavagno, C: Moon, R. Murgai, A. Saldanha, H. Savoj, P.R.Stephan, R.K. Brayton, and A. Sangiovanni-Vincentelli, SIS: A system for sequential circuit synthesis, Technical Report UCB/ERL M92/41, U:C: Berkeley, maggio [Stu94] G.S.Sturniolo, Un approccio al problema del partizionamento hardware/software delle specifiche di progetto, PhD thesis, Politecnico di Milano, [TLWN90] D. E. Thomas, E. D. Lagnese, R. A. Walker, J. A. Nestor, J. V. Rajan e R. L. BlackBurn, Algorithmic and Register-Transfer Level Synthesis: The System Architect s Workbench, Kluwer Academic Publishers, Boston, [TsSi86] [Vin95] C. J. Tseng e D. P. Siewiorek, Automated Synthesis of Data Paths on Digital Systems, IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems, vol. CAD-5, no. 3, pp , luglio M. Vincenzi, Specifica di sistema e sintesi del software per architetture miste hardware/software, PhD thesis, Politecnico di Milano,

5 [WaBo94] E. Walkup, G. Borriello, Automatic Synthesis of Device Drivers for Hardware/Sofware Codesign, Technical Report, University of Washington, Seattle, agosto

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