D Partitioig for Iterferece ad Area Miimizatio Hsi-Hsiug Huag ad Tsai-Mig Hsieh Abstract This work defies a ove probem i which a set of modues is assiged to a set of siico ayers i order to miimize the tota chip area whie satisfyig the characteristic costraits. A iteger iear programmig (ILP)-based partitioig approach is aso deveoped to assig a set of modues to the ayers of a three-dimesioa architecture durig a foor-paig phase. The proposed approach attempts to miimize the chip area, which is the maximum siico ayer area amog the set of ayers i a three-dimesioa system-i-package (SIP) architecture. Moreover, the circuit properties i which the digita ad aaog modues ot to assig to the same ayer are icorporated to icrease siga itegrity durig the partitioig stage. The optima modue assigmet for the three-dimesioa SIP architecture coud be obtaied because a the costraits i this work are iear fuctios. Experimeta resuts idicate that the proposed ILP-based method ca miimize the chip area whie meetig the SIP costraits of circuit properties to reduce the potetia of the wires i the digita ad aaog modues. The chip area is arger tha that of the method that does ot cosider properties of modues. Importaty, the proposed ILP-based approach sigificaty reduces the umber of the potetia to be zero by assigig aaog ad digita modues to the differet ayers of the SIP architecture. Keywords Iterferece, SIP-ware partitioig, iteger iear programmig, area miimizatio. T I. INTRODUCTION hree-dimesioa architecture i moder chip desig has may beefits [][][]. The ove three-dimesioa SIP architecture ca sigificaty improve the chip area, tota wire-egth, the umber of via cout ad performace. Hece, a icreasig umber of studies have ivestigated how to miimize the chip area for a three-dimesioa foor-paer. Moreover, compared to a sige-objective, a effective agorithm has bee used to sove a muti-objective probem [4]. Mauscript received Juy 6, 0: Revised versio received August, 0. This work was supported i part by the NSC99-5-E-6-07 from Natioa Sciece Couci. Hsi-Hsiug Huag is with the Lughwa Uiversity of Sciece ad Techoogy, Dept. of Eectroic Egieerig, No.00, Sec.,Washou Rd., Guisha Shiag, Taoyua Couty 06, Taiwa (R.O.C) (phoe:+886--809ext:56, fax: +886--809565, e-mai: pp0@mai.hu.edu.tw) Tsai-Mig Hsieh is with the Departmet of Iformatio ad Computer Egieerig, Chug Yua Christia Uiversity, Chug-Li, 0, Taiwa (R.O.C.). (correspodig author to provide phoe:+886--654708, fax: +886--654799, e-mai: hsieh@cycu.edu.tw) Iterferece degrades the siga itegrity betwee modues ad itercoectios with the differet properties or circuit characteristics of mixed-mode systems [5]. Tummaa derived a soutio for a mixed-siga system to meet the emergecy requiremets [6]. Laas et a. aayzed stochastic parametric resoace ad discussed the importace of oise [7]. Driovsky et a. expored the isertio oss of fiter for the EMI effects uder a testig eviromet [8]. Ho et a. discussed the crosstak () betwee wires for a mutipe-eve router [9]. Wag et a. deveoped a crosstak aware goba router to avoidig assig og segmets to differet tracks [0]. Most of studies reduce the crosstak or betwee wire sigas by the heuristic agorithms. The feasibiity of appyig iteger iear programmigbased approaches to optimize the chip area, tota wire egth, power cosumptio ad cock period has bee studied. Li et a. deveoped a ILP-based approach to reduce the tota wirig area for aaog circuit desig []. Nguye et a. preseted a ILP-based method, which optimizes simutaeousy power ad deay for the VLSI circuit desigs []. Chie et a. expored the feasibiity of usig a ILP-based approach to reduce the power cosumptio of a gate eve etist uder timig, power ad area costraits []. Chai et a. studied ILP formuatios ad soved differet miimizatio probems of the peak curret ad eakage [4]. Huag et a. miimized the cock period for sequetia circuit durig the high eve sythesis usig a ILP-based approach [5]. However, most of the above works did ot focus o the area miimizatio for the SIP architecture. Recet efforts have examied the use of ove three-dimesioa (D) foorpaig as the gate couts are growig rapidy [6]. Yamazaki et a. deveoped the three-dimesioa represetatio of the foorpaers with the mutipe objectives such as therma issues ad the area miimizatio [7]. Hug et a. preseted a foorpaer, which cosidered the therma issue by icorporatig a haf-perimeter egth estimator [8]. Tsai et a. addressed the therma issues for the three-dimesioa foorpaig with through-siicovia ad the physica positio for subcircuits [9]. Xiao et a. provided the fixed-outie costraits for the three-dimesioa foorpaig ad isertig through-siico-via to reduce the icidece of therma probems [0]. Some of works faied to achieve their objectives whe usig the heuristic method. Issue 6, Voume 5, 0 65
The mai cotributios of this paper are as foows. This work formuates a modue assigmet probem which determies the set of modues to the proper ayer i a three-dimesioa architecture. Circuit properties are formuated to reduce the betwee the aaog ad digita modues by the ILP formuatios. Additioay, a costraits are defied by ieary fuctios to obtai the optima soutio uder the give costraits of the properties. Furthermore, the ILP formuatios are efficiet to obtai the optima soutio with a acceptabe rutime. For each siico ayer, the partitioed resuts cotaiig some modues ca be further fed ito a simuated aeaig-based foorpaer that appies a sequece-pair to perturb reatioships betwee modues, for a situatio i which a feasibe foorpa is eeded for a three-dimesioa architecture. The rest of this paper is orgaized as foows. Sectio II describes the SIP architecture, the umber of potetia, the motivatio of cosideratio of modue characteristics ad probem defiitio. Sectio III the itroduces the -aware partitioig scheme to miimize the chip area for a three-dimesioa architecture. Sectio IV summarizes the experimeta resuts. Cocusios are fiay draw i Sectio V. II. PRELIMINARY This sectio describes i detai the system-i-package architecture. The umber of potetia is defied. The motivatio of cosiderig the circuit properties is the discussed to expore how the ILP-based approach hades the -aware partitioig scheme. Moreover, a -aware probem is formuated i the paper. A. Reviewer ad Trasformatio of System-i-Package Some approaches have bee deveoped to icrease productio capacity ad reduce time-to-market deivery [][][]. System-i-packet is a effective approach for a three-dimesioa architecture []. The system-i-packet architecture cotais ayers, such as the (RAM) ayers, digita ogic ayers ad aaog ayers. Figure (a) shows a set of pre-defied iteectua properties (IPs for short) which are paced i the correspodig ayers of the SIP architecture. Figure (b) deotes SIP compoets, icudig three ayers (i.e., digita ad aaog ayers) ad the wire bidig, which are used to coect the wires of modues that are ocated i the differet ayers. For simpicity, the SIP architecture is trasformed ito a set of siico ayers without the wire boudig compoet. I this work does ot cosider the itercoectios betwee the differet modues i differet ayers. Figure shows the trasformatio by omittig the wire bidig compoet ad system-i-package itegrated circuit (). The three ayers are the, aaog ad digita ayers. Each modue i is trasformed ito a rectaguar modue with the correspodig modue area (a i ), height (h i ) ad width (w i ). Figure iustrates the trasformatio from a IP ito a rectaguar modue. Based o the above discussio, Figure 4 pots the probem of assigig IPs to the stacked SIP architecture. Figure 4(a) shows the origia circuit which cotais six hard modues with the correspodig modue areas ad the SIP architecture with, aaog ad digita ayers. Figure 4(b) shows the represetatio with six rectaguar obstaces ad three ayers. Moreover, their modue properties (i.e., digita or aaog) are deotig usig three coors. Ram Aaog Ram Aaog (a) a set of modues with properties wire boudig Aaog (b) stacked three-dimesioa SIP Figure. Rea modue assigmet probem wire boudig Aaog Aaog Figure. Trasformatio of a system-i-package. Iteectua property w i h i Figure. Trasformatio of pre-defied iteectua property. a i w i Issue 6, Voume 5, 0 66
wire boudig Aaog Aaog Aaog digita aago (a) 6 modues ` a = a = a = a 4 = 4 a 5 = 5 a 6 = 6 B. Computatio of the Number of Potetia Iterferece Siga itegrity pays a sigificat roe i the moder chip desigs because of the icreasig umber of the digita ad aaog modes co-desiged i a sige system. As is we kow digita wires are ormay too strog to be high eve or ow eve sigas. I cotrast, the aaog sigas are easiy degraded ad destroyed by other adjacet digita wires. The startig or edig times of aaog wires may be deayed whe adjacet digita wires affect the aaog sigas. Furthermore, a uexpected gitch siga may appear i the aaog modues whe adjacet digita wires are aways at a high or ow votage (Figure 5). For the situatio i Figure 5, properties of the aaog modues may ead to mafuctio of the aaog sigas i the mixed-mode system. wires i aaog modue Iterfeuce by digita modue wires i digita modue (b) D architecture Figure 4. Iustratio of the SIP-aware D partitioig high votage ow votage high votage ow votage Figure 5. Iustratio of the potetia Potetia i the SIP architecture is measured by defiig the umber of potetia as foows., the aaog (digita) modue i is assiged to Nik (, ) = the digita (aaog) ayer k; () 0, otherwise; where Nik (, ) deotes the umber of potetia for modue i to the ayer k. This fidig suggests that if the aaog modue is assiged to the digita ayers of the SIP architecture, the umber of potetia icreases by oe. Simiary, the digita modue, which is assiged to the aaog ayer i the SIP architecture, is regarded as the potetia. C. Motivatio Area miimizatio ad potetia betwee modues i the same ayer are of priority cocer i the moder D stacked architecture. Whie faiig to cosider the issue betwee the digita modues ad the aaog modues ormay miimizes the chip area for the D foorpaig However, adjacet digita wires may uexpectedy destroy some aaog wires. Figure 6(a) demostrates the side effect due to the. Without focusig o the modue property, the digita modues may be assiged to the aaog ayer i order to miimize the chip area. Wires i the digita modue which is assiged to the aaog ayer potetiay degrade the wires i the aaog modue 4. Simiary, the wires i the aaog modue 5 may suffer uder the same circumstaces. Issue 6, Voume 5, 0 67
a 6 = 6 a = a 6 = 6 a = a = a 4 = 4 potetia a 5 = 5 a 4 = 4 free a = a 5 = 5 potetia a = a = free (a) chip area is 7 ad potetia is (b) chip area is 9 ad potetia is 0 Figure 6. Effect of the -ware partitioig Whie cosiderig the SIP costraits to assig a modue to the correspodig ayers i the SIP architecture, our ove formuatios obtai the -free modue assigmet soutio with a itte additioa chip area. I Figure 6(b), the aaog modues 4 ad 5 are assiged to the aaog ayer ad the umber of potetia s is zero. Simiary, o potetia occurs for digita ayers ad. Accordig to our resuts, the chip area coud be icreased to 9 with sma additioa chip area. This observatio motivates us to expore the ILP-based SIP-aware formuatios i order to miimize the chip area whie meetig the SIP costraits. This work examies how to achieve this mutipe-objective i this paper. Aaog Aaog Aaog Aaog (a) SIP-aware Partitioig Aaog aago digita D. Probem Defiitio Figure 7 shows the overa D foorpaig, i which the SIP-aware partitioig stage is of particuar focus. For the partitioed resuts i each ayer, the we-deveoped foorpaer which is based o the D represetatio (e.q. sequetia-pair) ca used to obtai a feasibe foorpa. Therefore, the probem discussed here is formuated as foows. Give a set of modue area { a, a, a,... a }, ad a set of k siico ayers {,,,... k } for three-dimesioa SIP architecture. For a set of modues { m, m, m,... m }, each modue has it correspodig properties { p, p, p,..., p }. Each modue is assiged to oe siico ayers. The work attempts to meet the SIP characteristic costraits whie miimizig the chip area for the SIP architecture. a 0 = 0 a 4=4 a 5=5 a a 6=6 7=7 (b)foorpaig a 0 = 0 a = a 9 = 9 a = a = a 4=4 a 9 = 9 a5=5 a = a = a = a 7=7 a 6=6 a = 7 a = 7 ayer Aaog ayer ayer ayer Figure 7. Iustratio of desig fow. Issue 6, Voume 5, 0 68
wire boudig Aaog digita aago Aaog Aaog (a) D SIP partitioig Aaog Aaog ` a = a = a 0 = 0 a = a = 7 a 9 = 9 a 4 = 4 a 5 = 5 a 6 =6 a 7 = 7 Figure 8. Iustratio of -free three-dimesioa partitioig (b) Modeig 4 III. ILP FORMULATION FOR SIP-AWARE PARTITIONING This sectio discusses ILP formuatios with -aware for the SIP architecture, i which the modue shaped is fixed (i.e. hard modues). May foorpaers have bee deveoped i the recet iterature. Therefore, this work discusses i detai the SIP-aware partitioig. A. Area Miimizatio Formuatio with SIP costraits A attempt is made to determie automaticay the modue assigmet automaticay by settig a biary variabe x(, i j ) to oe, if the modue i is assiged to the ayer j, otherwise x(, i j ) is set to be zero. The objective of this work is derived as foows, mi tota _ area () Subject to x(, i j ) = ; () i= j deotes aowed ayers tota_area ai x( i, j); (4) i= where x(, i j) deotes the biary variabe for the modue i, which is assiged to the ayer j. ai represets the modue area of the moduei. For each modue, to meet the SIP costraits, ot a ayers i a three-dimesioa SIP architecture coud be assiged. The tota _ area refers to the maximum chip area amog the three-dimesioa SIP architecture with k ayers. Formua () gives the objective to miimize the chip area for the three-dimesioa SIP architecture with k ayers. Formua () idicates that each modue i is assiged to oy oe ayer j. Formua (4) reveas that the maximum chip area is arger tha the area of each ayer j. By doig so, the umber represetig the ayer area ca be reduced. Origiay, the area of each ayer is deoted by usig four variabes. Notaby, reducig four variabes ito oe variabe speeds up the computatioa time. Reducig the potetia for the aaog modues ad digita modues ivoves the modue assigmet accordig to the modue property ad the SIP-aware costraits. This fidig suggests that the biary vaues deotig the modue assigmet shoud be modified. For istace, if modue is the aaog modue ad this modue shoud be assiged to ayer i order to reduce the potetia for the SIP architecture with four ayers, the biary variabe shoud be x (, ) = ad x(,) = x(,) = x(,4) = 0. B. Iustrative Exampe By usig a iustrative exampe, this subsectio expais how to formuate the proposed ILP formuatios with a SIP costrait. Origiay formuated as Figure 8(a), Figure 8(b) shows four ayers ad modues with the correspodig properties. For the SIP-aware partitioig scheme, = ad k = 4. Simiary, the objective is described as foows. mi = tota _ area; (5) Figure 8(b) reveas the foowig costraits to represet the chip area. a = ; a = ; a = ; a4 = 4; a5 = 5; a6 = 6; a7 = 7; a8 = 8; a9 = 9; a = 0; a = 7; 0 Notaby, i this paper, o modue is partitioed ad we the modue assigmet is defied by usig the biary variabe. For modue, four optios are avaiabe to pace i a three-dimesioa SIP architecture, thus eadig to (6) x(,) + x(, ) + x(,) + x(, 4) = ; (7) To meet paper space imitatio, oy modues ad are used to represet the reatio as foows. ad x(,) + x(,) + x(,) + x(,4) = ; (8) x(,) + x(, ) + x(, ) + x(, 4) = ; (9) Issue 6, Voume 5, 0 69
a 0 = 0 potetia a 0 = 0 a = a 4 = 4 a 5 = 5 a 7 = 7 a = a 4 = 4 a 5 = 5 a 9 = 9 a = a = 7 potetia a = a = a 6 = 6 a 7 = 7 4 a = a 6 = 6 a 9 = 9 potetia 4 a = 7 Iterferece free (a) partitioig with potetia (b) -free partitioig Figure 9. Iustratio of -free SIP partitioig The area boud for a ayers cotaiig a set of modues is give. I ayer, the tota ayer area is the sum of modue areas from modues to. Based o the above discussio, we defie biary variabes x (,), x (,),..., ad x (,) to deote the reatio of a modues ad a ayers, respectivey. The ayer area i ayer is obtaied with the foowig formua. tota_area a x(,) + a x(,) + a x(,) + a4 x(4,) + a5 x(5,) + a6 x(6,) + a7 x(7,) + a8 x(8,) + a9 x(9,) + a x(0,) + a x(,); 0 (0) Simiary, the ayer area ca be formuated based o the above discussio for ayers, ad 4. Without cosiderig SIP costraits (circuit properties) of modues ad ayers i the SIP architecture, the assiged modue ca be derived as foows. ad x(8,) = x(0,) = () x(, ) = x(4, ) = x(5, ) = x(7, ) = () x(, ) = x(, ) = () x(, 4) = x(6, 4) = x(9, 4) = (4) The above equatios revea that the optima chip area is tota _ area = 8 with potetia. Figure 9(a) summarizes the partitioed resuts for this circuit. I ayer (a aaog ayer), digita modues ad 7 are assiged. Accordig to the computatio of the potetia, the umber of potetia is. Simiary, aaog modues ad 9 are assiged to the ayers ad 4 (two digita ayers) ad the umber of the potetia is ad, respectivey. Therefore, the approach without cosiderig the potetia betwee the modues, the umber of potetia is 4. The of modue assigmet must be addressed ad reduced. Cosiderig the SIP costraits which are based o the properties of the modues ad the ayers aows us to reduce the potetia issue. For modue, it is proper to assig this modue to the digita ayers ad 4 ad we have the formua of x(,)+ x(,4)=. Simiary, for modue, we have x(,)+ x(,4)=. For the digita modues 6, 7 ad, we have x(6,)+ x(6,4)=, x(7,)+ x(7,4)= ad x(,)+ x(,4)=. Ivovig the above costraits i the LIP formuatio aows us to miimize the chip area whie reducig the umber of potetia. The modue assigmet is as foows. ad x(8,) = x(0,) = (5) x(,) = x(4,) = x(5,) = x(9,) = (6) x(,) = x(,) = x(6,) = x(7,) = (7) x (, 4) = (8) Accordig to our resuts, the chip area is icreased to 9 ( tota _ area = 9 ). Formuas (5)-(8) idicate that modues 8 ad 0 are assiged to ayer ; modues, 4, 5 ad 9 are assiged to ayer ; modues,, 6 ad 7 are assiged to ayer ; ad modue is assiged to ayer 4. Figure 9(b) reveas that the aaog modues, 4, 5 ad 9 are assiged to the aaog ayers i order to avoid potetia. Simiary, the umber of potetia s of ayers ad 4 are reduced to zero by ivovig SIP costraits. Summary, the chip area is icreased oy sighty (from 8 to 9) whie reducig the umber of potetia (from 4 to 0). This fidig suggests that the proposed SIP-aware partitioig approach ca simutaeousy miimize the chip area ad the potetia for the sigas betwee the digita ad aaog modues. IV. EXPERIMENTAL RESULTS I this work, ILP formuatios are geerated automaticay by C++ aguage, aog with experimets performed o a Ite.40GB machie with GB i order to optimize the chip area for a D stacked SIP architecture with four meta ayers. Effectiveess of the proposed ILP formuatios is demostrated by usig GRSC bechmarks that are utiized to perform experimets. Tabe ists the statistics of GRSC bechmarks, icudig the circuit ame, the umber of modues, the modue area, the chip area ad percetage of area reductio. Issue 6, Voume 5, 0 640
First, effectiveess of the ILP-based approach is examied. Compared with the theoreticay resuts, i.e. tota modue area based o the umber of ayer, the ILP-based approach without SIP miimizes the chip area. Tabes ad show that both the ILP-based without ad with SIP costrait reduce the chip area. With a acceptabe rutime, the partitioed resuts are obtaied efficiety. Additioay, the improvemet i the umber of the potetia is aso examied. I the formuatios with SIP cosideratio, the digita ad aaog modues are paced i the differet ayers. Hece, the sigas i aaog modues did ot be affected by itercoects i the digita modues. Accordig to Tabe, the umber of potetia is reduced to zero. V. CONCLUSIONS This work defies a ove probem of a D SIP-aware partitioig scheme ad soves it by usig the ILP-based approach. The objective is to miimize the chip area whie satisfyig the SIP costraits i order to reduce the potetia. A costraits are iear to formuate this SIP-aware partitioig probem. Experimeta resuts idicate that the proposed ILP-based SIP-aware method reduce the area compared to the tota modue area. Furthermore, the SIP-aware approach more sigificaty reduces the umber of potetia s tha with partitioig approach without the SIP costraits. ACKNOWLEDGEMENTS The authors woud ike to thak the fiacia support of the grat NSC99-5-E-6-07 from Natioa Sciece Couci. REFERENCES [] J. Miz, ad S.K. Lim, "Bock-eve D Goba Routig With a Appicatio to D Packagig," IEEE Trasactios o Computer-Aided Desig of Itegrated Circuits ad Systems, Vo. 5, No. 0, pp. 48-57, 006. [] Jiwoo Pak; Myughyu Ha; Jaemi Kim; Doghee Kag; Ho Choi; Seyoug Kwo; Keusoo La; Jougho Kim, Desig of a -D SiP for T-DMB with Improvemet of Sesitivity ad Noise Isoatio, i Proc. of Eectroics Packagig Techoogy Coferece, pp.87-9, 008. [] S. K. Lim, Physica desig for D System-o-Package, IEEE Des. Test. Comput., vo., o. 6, pp. 5 59, 005. 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Hsieh, Optima Suppy Votage Assigmet uder Timig, Power ad Area Costraits, IEICE Trasactios o Fudametas of Eectroics, Commuicatios, ad Computer Scieces, Vo.E9, NO4, pp. 76-768, 00. [4] D. Chai ad A. Kuehma, Circuit-based Preprocessig of ILP ad Its Appicatios i Leakage Miimizatio ad Power Estimatio, i Proc. of IEEE/ACM Iteratioa Coferece o Computer Desig, pp.-6, 004. [5] S.H. Huag, C.H. Cheg, Y.T. Nieh, ad W.C. Yu, Register Bidig for Cock Period Miimizatio, Proc. of ACM/IEEE Desig Automatio Coferece, pp.49-444, 006. [6] L. Cheg, L. Deg ad D. F. Wog, Foorpaig for D VLSI desig, Proc. of ACM/IEEE Asia-South Pacific Desig Automatio Coferece, pp.405-4, 005. [7] H. Yamazaki, K. Sakaushi, S. Nakatake ad Y. Kajitai, The D Packig by Meta Data Structure ad Packig Heuristics, IEICE Tras. o Fudametas, pp.69-645, 000. [8] W.L. Hug, G.M. Lik, X. Yua, N. Vijaykrisha, ad M.J. Irwi, Itercoect ad Therma-aware Foorpaig for d Microprocessors, Proc. of Iteratioa Symposium o Quaity Eectroic Desig, pp. 6, 006. [9] M.C. Tsai, T.C. Wag, ad T. T. Hwag, Through-Siico Via Paig i D Foorpaig, IEEE Trasactios o Very Large Scae Itegratio Systems, pp.-0, 00. [0] L. Xiao, S. Siha, J. Xu, F.Y Youg, Fixed-Outie Therma-aware D Foorpaig, Proc. of ACM/IEEE Asia ad South Pacific Desig Automatio Coferece, pp.56-567, 00. Hsi-Hsiug Huag received the M.S. ad Ph.D. degrees i the Dept. Iformatio Computer Egieerig ad Eectroic Egieerig from Chug Yua Christia Uiversity, Taoyua, Taiwa, i 000 ad 008, respectivey. From 000 to 00, He is a hardware egieerig to desig the Etheret product at Accto Corporatio, Hsi-Chu, Taiwa. From 00 to 00, He focus o the chip desig for the 0/00/000 Mbps Etheret MAC at TM-Techoogy Corporatio, Hsi-Chu, Taiwa. His is iterested i the desig ad aaysis of the agorithms. He is workig toward the agorithm reated fieds, such the appicatio of ie-foowig maze robot ad CAD agorithms for the VLSI, the foorpaer ad performace-drive routig with the obstaces. Tsai-Mig Hsieh received his B.S. degree i Eectrica Egieerig form Chug Yua Uiversity, Chug-Li, Taiwa, i 970 ad his M.S. ad Ph.D degrees i Eectrica Egieerig from the Istitute of Eectroics, Natioa Chiao Tug Uiversity, Hsichu, Taiwa, i 974 ad 98, respectivey. He is currety a professor of the Departmet of Iformatio ad Computer Egieerig at Chug Yua Uiversity. His curret research iterests are i computer-aided desig o itegrated circuits, desig ad aaysis of agorithms, ad combiatioa mathematics. Issue 6, Voume 5, 0 64
stabe. Bechmark statistics ad resuts without SIP costraits. Name A B C Imp (%) 0 0 679 5668 74.6646 0 0 0859 550 74.9989 50 50 98579 49645 74.99987 00 00 7950 44876 74.99958 A= umber of modues for each bechmark ; B= tota modue area ; ad C= chip area without SIP ; Imp(%)= the reductio of chip area without SIP (=00 (B-C)/B) ; Tabe. Bechmark statistics ad resuts with SIP costraits. Name A B D Imp (%) 0 0 679 947 58.79 0 0 0859 5489 7.6849 50 50 98579 5488 7.664 00 00 7950 506 7.06 B= tota modue area ; D= chip area with SIP ; Imp(%)= the reductio of chip area with SIP (=00 (B-D)/B) ; Tabe. Compariso of the umber of potetia without ad with SIP costraits. Name A E F Imp 0 0 0 0 0 0 0 0 50 50 0 00 00 6 0 6 E= The umber of potetia without SIP ; F= The umber of potetia with SIP ; Imp= E-F; Issue 6, Voume 5, 0 64