: An Overview Applicaion Noe 1. Inroducion 2. Volaile Memory All compuer-based sysems conain memory. Memory is where informaion is sored while waiing o be operaed on by he Cenral Processing Uni (CPU) of he compuer. There are wo ypes of memory: volaile memory and non-volaile memory. Volaile memory reains is informaion only while power is applied o he memory device. The conens of his memory ype may be easily and quickly changed. Non-volaile memory reains is informaion even when no power is applied o he memory device. Alhough he informaion in mos non-volaile memories may be changed, he process involved is much slower han for volaile memory. Volaile memory loses is conens when he device loses power. Random Access Memory (RAM) is he radiional name used for volaile memory. The name refers o he abiliy o access any locaion of he memory quickly wih no paricular order of accesses needed. Saic RAM (SRAM) and Dynamic RAM (DRAM) are wo examples of volaile memories ha have his characerisic. SRAM ypically uses six ransisors for each memory bi (cell) o reain daa as long as power is being supplied. This makes each memory cell relaively large and limis SRAM o use in lower densiy memories. SRAM can provide faser access o daa, use less sandby power, and ends o be more expensive han DRAM. DRAM uses a single ransisor and a small capacior for each bi of memory. Since capaciors do no hold a charge indefiniely, DRAM cells mus be frequenly recharged (refreshed) o avoid losing he conens. These smaller memory cells allow DRAM o be used for high densiy, low cos memories, bu are ypically slower han SRAM. 3. Non-Volaile Memory Non-volaile memory is memory ha reains is conens even if he power is los. Non-volaile memory was originally called Read Only Memory (ROM) because is conens were loaded during he manufacuring process and could be read, bu never erased or reprogrammed. Over ime, he abiliy o erase and reprogram ROM was added in differen ways and referred o as Elecrically Programmable ROM (EPROM), Elecrically Erasable and Programmable ROM (EEPROM), and flash EEPROM - commonly referred o simply as flash memory. ROM memory is programmed by he way i is manufacured and sores permanen code and daa ha is generally used o iniialize and operae a compuer sysem. EPROM can be elecrically programmed one bye a a ime bu is no elecrically erasable. I has o be exposed o ulra-viole (UV) ligh for abou weny minues in order o erase all bis in he memory array. EPROM uses a single ransisor for each daa bi and can be used in relaively high densiy memories. EEPROM is elecrically erasable and programmable in-sysem, one bye a a ime, bu he memory cells use more ransisors and are larger han hose in EPROMs, hus EEPROM has higher coss and lower densiy (generally less han 1 Mb). Flash EEPROM memory can be elecrically programmed a single bye or word a a ime, bu a large group of byes or words called a block, secor, or page are elecrically erased a he same ime. Due o he erase operaion being much faser han he prior EPROM or EEPROM devices, hese devices came o be called flash erase EEPROM, or simply flash memories. The flash memory cell uses a single ransisor o sore one or more bis of informaion. Flash echnology combines he high densiy of EPROM wih he elecrical Publicaion Number FlashOverview_AN Revision A1 Issue Dae November 15, 2010
Applicaion Noe in-sysem erase and programmabiliy of EEPROMs. Flash memory has become he dominan ype of non-volaile memory in use. Table 3.1 compares he fundamenal feaures of flash memory wih hose of he oher memory echnologies discussed earlier. The remainder of he applicaion noe will cover only flash memory. Non volaile Table 3.1 Compares wih Oher Memory Technologies High Densiy Low Power One Transisor Per Cell In-Sysem Rewrieable Fully Bi-Alerable High-Performance Read Flash Memory x x x x x x SRAM x x x DRAM x x x x x EPROM x x x x x EEPROM x x x x x 4. Archiecures Two main archiecures dominae flash memory: NOR and NAND. NOR is ypically used for code sorage and execuion. NOR allows quick random access o any locaion in he memory array, 100% known good bis for he life of he par, and code execuion direcly from NOR flash memory. NOR is available in boh parallel and serial inerface configuraions. Parallel configuraions suppor eiher separae or muliplexed address and daa busses. Serial configuraions suppor daa ransfers of 1, 2, or 4 bis in a hos conrolled synchronous ransfers. This documen refers o parallel NOR feaures and conrols. NAND is used for daa sorage. NAND flash requires a relaively long iniial read access o he memory array, 98% good bis when shipped wih addiional bi failure over he life of he par (ECC highly recommended), program/erase imes are much faser han NOR and NAND coss less per bi han NOR. NAND is primarily available in a parallel configuraion wih muliplexed address and daa busses. Table 4.1 Difference Beween NOR and NAND Parameer NOR NAND Densiy 1 Mbi 2 Gbi 256 Mbi - 64 Gbi Read iniial access 55 ns 10,000 ns Read sequenial access 7 ns 50 ns Program 0.3-1.5 Mbyes / s 2-166 Mbyes / s Erase 0.2-0.7 Mbyes / s 10-60 Mbyes / s Access Mehod Random Sequenial 5. Spansion Spansion is one of he world's leading suppliers of NOR flash memory. Spansion flash memory producs include a broad specrum of densiies and feaures o suppor a wide range of cusomer specific markes such as hand-held/mobile elecronics, compuer, se-op boxes, and auomoive applicaions. Spansion primarily uses wo flash memory echnologies: Floaing Gae and MirrorBi. Floaing Gae echnology was firs inroduced in he early 1990's. I offered fas access imes, and high program/erase endurance cycles. This echnology allowed he sorage of only one daa bi per cell. However, wih he inroducion of MirrorBi echnology in 2001, Spansion is able o offer a more cos-effecive soluion o cusomers, while sill mainaining fas access imes and high endurance cycles. The cos effecive soluion is he design of he MirrorBi sorage cell, which can sore wo daa bis per cell, insead of jus one daa bi. This design enables manufacuring coss o be significanly lower han ha of Floaing Gae echnology. MirrorBi echnology definiely has a clear economical, as well as a echnological advanage over Floaing Gae echnology. 2 FlashOverview_AN_A1 November 15, 2010
Applicaion Noe 5.1 Disincive Feaures Spansion parallel NOR flash memory offers many disincive feaures ha help designers build feaure-rich, cos-effecive sysems. Key disincive characerisics include: Secured Silicon Secor ACC WP# VI/O CFI Wrie Buffer Advanced Secor Proecion Page Mode Burs Mode Simulaneous Read/Wrie Secured Silicon Secor feaure enables permanen par idenificaion hrough an Elecronic Serial Number (ESN). The Secure Silicon Secor provides a 128 Byes o 1 Kbyes area for code or daa ha can be permanenly proeced. Once his secor is proeced, no furher changes wihin he secor can occur. The Secure Silicon Secor Indicaor Bi (DQ7) is used o deermine wheher or no he Secure Silicon Secor is proeced. Spansion offers he device wih he Secure Silicon Secor eiher cusomer lockable or facory locked. The cusomer-lockable version is shipped wih he Secure Silicon Secor unproeced and has he Secure Silicon Secor Indicaor Bi permanenly se o a 0. The facory-locked version is always proeced and has he Secure Silicon Secor Indicaor Bi permanenly se o a 1. ACC (Acceleraed Program Operaion) is an inpu pin ha allows for faser programming or erases operaion when raised o a specified volage (12V or 9V). WP# (Wrie Proec) is a hardware mehod for proecing boo secors using sandard conrol logic signals. V I/O is a feaure ha allows he signal inerface volage levels o be deermined by he V I/O power supply. CFI is a feaure ha provides device-specific informaion o he sysem, allowing hos sofware o easily reconfigure for differen flash devices. The device eners he CFI Query mode when he sysem wries he CFI Query command, 98h, o address 55h, any ime he device is ready o read array daa. The sysem can also wrie he CFI Query command when he device is in he Auoselec mode. Wrie Buffer allows he sysem o wrie up o 32 words in one programming operaion. I is implemened o speed up programming operaions. A Wrie Buffer is a se of regisers used o hold several words ha are o be programmed as a group. Advanced Secor Proecion provides command-conrolled raher han volage-conrolled proecion o any secor agains inadveren or malicious program or erase operaions. Refer o he daa shee for deailed informaion. Page Mode allows high speed random read access o memory addresses near he iniial access address. Use of page mode can increase asynchronous read hroughpu by up o 300%. Burs Mode allows high speed sequenial reading of he flash wihou he need o updae he address lines. Synchronous ransfers can occur a raes of up o 216 MByes per second. Simulaneous Read/Wrie allows he flash o be read from a he same ime a program or erase operaion is being performed. Flash wih his feaure are subdivided ino muliple banks of secor groups. While program or erasing is occurring in one bank, he sysem can read from any oher bank. November 15, 2010 FlashOverview_AN_A1 3
Applicaion Noe 5.2 Basic Operaion 5.2.1 Read There are hree basic operaions in a flash memory: read (a bye or a word), program (a bye or a word), and erase (one or more secors). Spansion provides hree ypes of read operaions: asynchronous read, asynchronous page read, and synchronous burs read. Asynchronous read is a read no occurring a predeermined or regular inervals (no dependen on a clock). Typical read access ime is 55 o 120 ns. Figure 5.1 shows he iming diagram. Figure 5.1 Asynchronous Read Operaion Timing RC Addresses Addresses Sable ACC CE# OE# RH RH OE DF OEH WE# Oupus High-Z CE OH Oupu Valid High-Z RESET# RY/BY# 0 V Asynchronous page read is an asynchronous read operaion of several words, in which he firs word of he group akes a longer iniial access ime, and subsequen words in he group ake less page access ime o be read. The page size of he page mode devices varies beween 8 and 32 byes, wih he page being seleced by he leas significan wo o four bis of he address bus. Page mode inerface provides faser read access speed for random locaions wihin a page. Iniial access ime is ypically 70 o 120 ns. Access ime wihin a page is ypically 20 o 30 ns. Figure 5.2 shows he page read iming diagram. Figure 5.2 Page Read Timing A19-A3 Same Page A2-A1 Daa Bus Aa Ab Ac Ad ACC PACC PACC PACC Qa Qb Qc Qd CE# Synchronous burs read is a read occurring a regular inervals dependen on a clock edge. Burs mode devices require hree exra conrol pins o perform burs read: Clock, Load Burs Address (LBA#) or Address Valid (ADV#), and Burs Address Advance (BAA#) or RDY. 4 FlashOverview_AN_A1 November 15, 2010
Applicaion Noe When he burs device firs powers up, i is enabled for asynchronous read operaion. To enable synchronous burs read, he sysem mus issue he burs mode enable command sequence. The iniial address of an access is loaded by he clock edge when LBA# or AVD# is low. The firs daa word is available afer he iniial access ime delay. Sequenial words are available on each subsequen rising clock edge afer an iniial burs access delay of ypically 50 o 104 ns. Burs accesses can coninue a a clock rae of up o 108 MHz. Depending on he specific device, Spansion burs mode flash offers a number of read modes o inerface wih a wide range of microprocessors. They are linear burs, inerleaved burs, and coninuous sequenial burs. In he linear and inerleaved burs modes, he device delivers a sream of words from a 4, 8, 16, or 32 word aligned block. (For he S29CD family, he burs is 32-bi double words.) If he iniial address is no a he beginning of he block, he sequence of words following he iniial access will wrap from he end o he beginning of he block. In coninuous sequenial burs mode he device reads sequenially hrough he enire address range. Refer o a specific burs device daa shee for deailed informaion. Figure 5.3 shows burs read mode. Figure 5.3 Burs Read Timing CE# CES CEZ CLK LBAS LBA# BAA# A0:A18 DQ0:DQ15 ACS Aa ACH LBAH BAAH BDH BAAS BACC IACC Da Da + 1 Da + 2 Da + 3 Da OE#* OE OEZ IND# 5.2.2 Program 5.2.3 Erase The unprogrammed sae of a flash memory cell is a high signal level or logical one. Changing a flash memory cell (or bi) o a low volage level or zero is called programming. Programming on Spansion Floaing Gae flash is generally done one bye or word a a ime. MirrorBi echnology uses a wrie buffer o program one bye o as many as 32 byes. One key poin o noe is ha programming only changes ones o zeros. Programming is iniiaed by a series of wrie accesses ha form a program command. The required sequence of wrie accesses prevens uninended changes o sored daa. Erasure of a flash device is done hrough muliple wrie accesses ha form an erase command. The erase compleion ime is dependen upon he secor size and echnology. The erase command sequence iniiaes he embedded erase algorihm an inernal algorihm ha auomaically preprograms he memory array (if i is no already programmed) before execuing he erase operaion simulaneously on all bis of he secor. One key poin o noe is ha chip or secor erasing only changes zeros o ones. During erase, he device auomaically imes he erase pulse widhs and verifies he proper cell margin. November 15, 2010 FlashOverview_AN_A1 5
Applicaion Noe 5.3 Temperaure Ranges Spansion flash memory devices are available in various emperaure ranges, as shown in Table 5.1. Table 5.1 Various Temperaure Opions Code Name Descripion C Commercial 0 o +70 C or + 85 C W Wireless -25 o +85 C I Indusrial -40 o +85 C V Auomoive-In cabin -40 o +105 C N Exended -40 o +125 C H Ho -40 o +145 C 5.4 Spansion Produc Families Table 5.2 Spansion Produc Families Produc Family Archiecure Densiy Core Volage AL AS CD CL F FL GL JL NS PL VS WS XS Floaing Gae Technology, Low Volage, Asynchronous, Parallel NOR Floaing Gae Technology, Super Low Volage, Asynchronous, Parallel NOR Floaing Gae Technology, Very Low Volage, Simulaneous Read/Wrie, Synchronous, Parallel NOR Floaing Gae Technology, Low Volage, Simulaneous Read/Wrie, Synchronous, Parallel NOR Floaing Gae Technology, Asynchronous, Parallel NOR Floaing Gae or MirrorBi Technology, Low Volage, High Performance, Serial NOR MirrorBi Technology, Low Volage, Page Mode, Asynchronous, Parallel NOR Floaing Gae Technology, Low Volage, Simulaneous Read/Wrie, Asynchronous, Parallel NOR Floaing Gae or MirrorBi Technology, Super Low Volage, Simulaneous Read/Wrie, Synchronous, Muliplexed Parallel NOR Floaing Gae Technology, Low Volage, Simulaneous Read/Wrie, Page Mode, Asynchronous Parallel NOR MirrorBi Technology, Super Low Volage, Simulaneous Read/Wrie, Synchronous, Muliplexed Parallel NOR MirrorBi Technology, Super Low Volage, Simulaneous Read/Wrie, Synchronous, Parallel NOR MirrorBi Technology, Super Low Volage, Simulaneous Read/Wrie, Synchronous, Muliplexed Parallel NOR 8 Mb 16 Mb 3V 8 Mb 16 Mb 1.8V 16 Mb 32 Mb 2.5V 16 Mb 32 Mb 3V 1 Mb 8 Mb 5V 8 Mb 512 Mb 3V 32 Mb 2 Gb 3V 32 Mb 64 Mb 3V 32 Mb 256 Mb 1.8V 32 Mb 128 Mb 3V 128 Mb 256 Mb 1.8V 64 Mb 512 Mb 1.8V 128 Mb 256 Mb 1.8V Noe: Devices have prefixes such as AM29, S25, and S29. 6. Conclusion Spansion flash memory provides a compac, easy o use, non-volaile code and daa sorage soluion for elecronic producs. Spansion provides a broad porfolio of flash memories o sui a wide range of applicaions. The memory size, volage, speed, and package, can be seleced o sui he applicaion. 6 FlashOverview_AN_A1 November 15, 2010
Applicaion Noe 7. Revision Hisory Secion Revision A0 (November 10, 2005) Revision A1 (November 15, 2010) Global Iniial release Updaed o reflec curren flash porfolio Descripion November 15, 2010 FlashOverview_AN_A1 7
Applicaion Noe Colophon The producs described in his documen are designed, developed and manufacured as conemplaed for general use, including wihou limiaion, ordinary indusrial use, general office use, personal use, and household use, bu are no designed, developed and manufacured as conemplaed (1) for any use ha includes faal risks or dangers ha, unless exremely high safey is secured, could have a serious effec o he public, and could lead direcly o deah, personal injury, severe physical damage or oher loss (i.e., nuclear reacion conrol in nuclear faciliy, aircraf fligh conrol, air raffic conrol, mass ranspor conrol, medical life suppor sysem, missile launch conrol in weapon sysem), or (2) for any use where chance of failure is inolerable (i.e., submersible repeaer and arificial saellie). Please noe ha Spansion will no be liable o you and/or any hird pary for any claims or damages arising in connecion wih above-menioned uses of he producs. Any semiconducor devices have an inheren chance of failure. You mus proec agains injury, damage or loss from such failures by incorporaing safey design measures ino your faciliy and equipmen such as redundancy, fire proecion, and prevenion of over-curren levels and oher abnormal operaing condiions. If any producs described in his documen represen goods or echnologies subjec o cerain resricions on expor under he Foreign Exchange and Foreign Trade Law of Japan, he US Expor Adminisraion Regulaions or he applicable laws of any oher counry, he prior auhorizaion by he respecive governmen eniy will be required for expor of hose producs. Trademarks and Noice The conens of his documen are subjec o change wihou noice. This documen may conain informaion on a Spansion produc under developmen by Spansion. Spansion reserves he righ o change or disconinue work on any produc wihou noice. The informaion in his documen is provided as is wihou warrany or guaranee of any kind as o is accuracy, compleeness, operabiliy, finess for paricular purpose, merchanabiliy, non-infringemen of hird-pary righs, or any oher warrany, express, implied, or sauory. Spansion assumes no liabiliy for any damages of any kind arising ou of he use of he informaion in his documen. Copyrigh 2005-2010 Spansion Inc. All righs reserved. Spansion, he Spansion logo, MirrorBi, MirrorBi Eclipse, ORNAND, EcoRAM and combinaions hereof, are rademarks and regisered rademarks of Spansion LLC in he Unied Saes and oher counries. Oher names used are for informaional purposes only and may be rademarks of heir respecive owners. 8 FlashOverview_AN_A1 November 15, 2010