List of Figures Preface Acknowledgments First Author s Personal Thanks xi xv xxi xxiii 1. PRELIMINARIES 1 1 High-speed CMOS-circuits 1 2 Asynchronous protocols and delay-insensitive codes 3 3 Production rules 4 4 The MiniMIPS processor 4 5 Commonly used abbreviations 6 2. ASYNCHRONOUS PULSE-LOGIC BASICS 7 1 Road map of this chapter 9 2 The pulse repeater 10 2.1 Timing constraints in the pulse repeater 11 2.2 Simulating the pulse repeater 11 2.3 The synchronous digital model 18 2.4 Asymmetric pulse-repeaters 20 3 Formal model of pulse repeater 21 3.1 Basic definitions 21 3.2 Handling the practical simulations 22 3.3 Expanding the model 24 3.4 Using the extended model 26 3.5 Noise margins 28 4 Differential-equations treatment of pulse repeater 29 4.1 Input behavior of pulse repeater 30
vi ASYNCHRONOUS PULSE LOGIC 4.2 Generalizations and restrictions 34 3. COMPUTING WITH PULSES 37 1 A simple logic example 38 2 Pulse-handshake duty-cycle 42 3 Single-track handshake interfaces 45 4 Timing constraints and timing assumptions 46 5 Minimum cycle transition-counts 47 6 Solutions to transition-count problem 48 7 The APL design-style in short 48 4. A SINGLE-TRACK ASYNCHRONOUS PULSE- LOGIC FAMILY: I. BASIC CIRCUITS 51 1 Preliminaries 51 1.1 Transition counting in pipelined asynchronous circuits 52 1.2 Transition-count choices in pulsed circuits 53 1.3 Execution model 56 1.4 Capabilities of the STAPL family 56 1.5 Design philosophy 58 2 The basic template 58 2.1 Bit generator 59 2.2 Bit bucket 63 2.3 Left-right buffer 66 3 Summary of properties of the simple circuits 71 5. A SINGLE-TRACK ASYNCHRONOUS PULSE- LOGIC FAMILY: II. ADVANCED CIRCUITS 73 1 Multiple input and output channels 73 1.1 Naïve implementation 74 1.2 Double triggering of logic block in the naïve design 75 1.3 Solution 76 1.4 Timing assumptions 77 2 General logic computations 77 2.1 Inputs whose values are not used 78 3 Conditional communications 81 3.1 The same program can be expressed in several ways 83 3.2 Simple techniques for sends 83 3.3 General techniques for conditional communications 84 4 Storing state 89
vii 4.1 The general state-storing problem 89 4.2 Implementing state variables 90 4.3 Compiling the state bit 92 5 Special circuits 95 5.1 Arbitration 96 5.2 Four-phase converters 99 6 Resetting STAPL circuits 100 6.1 Previously used resetting schemes 101 6.2 An example 104 6.3 Generating initial tokens 104 7 How our circuits relate to the design philosophy 105 8 Noise 106 8.1 External noise-sources 106 8.2 Charge sharing 107 8.3 Crosstalk 107 8.4 Design inaccuracies 109 6. AUTOMATIC GENERATION OF ASYNCHRONOUS PULSE-LOGIC CIRCUITS 111 1 Straightforwardly compiling from a higher-level specification 111 2 An alternative compilation method 113 3 What we compile 113 4 The PL1 language 114 4.1 Channels or shared variables? 115 4.2 Simple description of the PL1 language 115 4.3 An example: the replicator 117 5 Compiling PL1 118 6 PL1-compiler front-end 120 6.1 Determinism conditions 120 6.2 Data encoding 122 7 PL1-compiler back-end 124 7.1 Slack 125 7.2 Logic simplification 127 7.3 Code generation 129 7. A DESIGN EXAMPLE: THE SPAM MICROPROCESSOR 133 1 The SPAM architecture 133 2 SPAM implementation 134
viii ASYNCHRONOUS PULSE LOGIC 2.1 Decomposition 2.2 Arbitrated branch-delay 2.3 Byte skewing 3 Design examples 3.1 The PCUNIT 3.2 The REGFILE 4 Performance measurements on the SPAM implementation 4.1 Straightline program 4.2 Computing Fibonacci numbers 4.3 Energy measurements 4.4 Summary of SPAM implementation s performance 4.5 Comparison with QDI 8. RELATED WORK 1 Theory 2 STAPL circuit family 3 PL1 language 4 SPAM microprocessor 9. LESSONS LEARNED 1 Conclusion Appendices PL1 Report 0.1 Scope 0.2 Structure of PL1 1 Syntax elements 1.1 Keywords 1.2 Comments 1.3 Numericals 1.4 Identifiers 1.5 Reserved special operators 1.6 Expression operators 1.7 Expression syntax 1.8 Actions 2 PL1 process description 2.1 Declarations 2.2 Communication statement 2.3 Process communication-block 134 136 137 140 140 151 158 158 160 162 163 163 169 170 171 172 175 175
ix 3 Semantics 178 3.1 Expression semantics 178 3.2 Action semantics 180 3.3 Execution semantics 180 3.4 Invariants 181 3.5 Semantics in terms of CHP 181 3.6 Slack elasticity 183 4 Examples 184 SPAM Processor Architecture Definition 187 1 SPAM overview 187 2 SPAM instruction format 187 3 SPAM instruction semantics 189 3.1 Operand generation 189 3.2 Operation definitions 189 4 Assembly-language conventions 191 4.1 The SPAM assembly format 191 Proof that Definition 2.2 Defines a Partial Order 193 1 Remark on Continuity 194