Coherent sub-thz transmission systems in Silicon technologies: design challenges for frequency synthesis Alexandre Siligaris www.cea.fr
Cliquez pour modifier le style du Outline titre Introduction-context for sub-thz Some ideas for low PhN Architecture and design choices Examples on fabricated circuits CMOS 65nm Application to THz imagers : impact of PhN CEA. All rights reserved DACLE Division 2014 2
THz gap!! Far IR Mid IR Near UV Bands Cliquez pour modifier Introduction-Context le style titre Spectrum : available sources wavelength l (m) frequency (Hz) 1 cm 1 mm 0.1 mm 1 µm 1 nm 1 Å 1 pm 10 3 10 2 10 1 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 1 MHz 1 GHz 1 THz 1 PHz 1 EHz 10 5 10 6 10 7 10 8 10 9 10 10 10 11 10 12 10 13 10 14 10 15 10 16 10 17 10 18 10 19 10 20 Radio spectrum THz Infrared Ultraviolet X-Rays Gamma Broadcast Wireless Microwave Extreme UV Soft X-ray Hard X-ray Electronics frequency (GHz) Optoelectronics (diodes, lamps ) UV lamps diodes X-ray tubes 100 200 300 Microwave Sub-THz THz Pushing up electronics operating frequency CEA. All rights reserved DACLE Division 2014 3
Cliquez pour modifier Introduction-Context le style titre THz gap: increasing electronics frequency Application to Communication systems >10 Gbps QPSK RX at 240 GHz Need of coherent (locked) frequency sources Thyagarajan et al. RFIC 2014 THz imaging : CEA. All rights reserved DACLE Division 2014 4
PhN @ 1MHz (dbc/hz) Cliquez pour modifier Introduction-Context le style titre RF mmw PLL state of the art. PhN vs Osc. frequency -70 CICC 2006 Trend -80-90 -100-110 -120-130 -140 CICC 2009 ISSCC 2014 ISSCC 2009 JSSC 2004 ISSCC 2011 VLSI 2013 CICC 2007 VLSI 2011 ISSCC 2008 VLSI 2012 VLSI 2012 1 10 100 VCO PLL Frequency (GHz) VLSI 2013 ASSCC 2010 ISSCC 2008 VLSI 2013 TCAS-II 2011 ISSCC 2009 ISSCC 2013 CICC 2006 ISSCC 2014 ASSCC 2010 + 20log(freq/fosc) JSSC 2004 + 20log(freq/fosc) Is it possible to realize a sub- THz freq. synthesis on the red line??? CEA. All rights reserved DACLE Division 2014 5
Cliquez pour modifier le style du Outline titre Introduction-context for sub-thz Some ideas for low PhN Architecture and design choices Examples on fabricated circuits CMOS 65nm BiCMOS 55nm Application to THz imagers : impact of PhN CEA. All rights reserved DACLE Division 2014 6
Main idea: Cliquez pour modifier Some ideas le style for low du titre PhN From a lower frequency synthesis use frequency multipliers PFD CP Div. X GHz PhN X GHz Freq. Mult. xn XN GHz PhN X GHz +20log(N) Aim : ~ 300 GHz What is the best choice for X GHz??? Determines multiplication factor N Constrains Constrains on PLL design: - VCO PhN. - Freq. dividers/prescalers design. - Filter and PLL stability. Constrains on multiplier design: - Technique choice. - Circuit architecture choice. - Energy efficiency. CEA. All rights reserved DACLE Division 2014 7
Cliquez pour modifier Some ideas le style for low du titre PhN State of the art high order freq. mult. for THz Berkeley (RFIC 2014): 240 GHz QPSK Rx University of Wuppertal (TMTT 2011): 325 GHz LO generator LO generator @ 240 GHz x3 Distorder x3 Distorder x2 Distorder 13.3 GHz X2 Push-push 26.7 GHz ILO 26.7 GHz 80 GHz 80 GHz x3 SHILO PA 240 GHz x3 Distorder X18 Multiplier in CMOS 65nm P DC ~ 1500 mw X18 Multiplier in CMOS 65nm P DC ~ 180 mw CEA. All rights reserved DACLE Division 2014 8
Cliquez pour modifier Some ideas le style for low du titre PhN Frequency Multiplication steps: example 1 frequency (GHz) Optimal Osc. fundamental operation f t, fmax CMOS f t, fmax BiCMOS PLL synth. 50 100 200 300 Microwave Sub-THz THz Example : PLL freq =50 GHz, F out =300 GHz => N=6 x6 the oscillator fundamental frequency PFD CP 50 GHz x6 300 GHz Div. CEA. All rights reserved DACLE Division 2014 9
Cliquez pour modifier Some ideas le style for low du titre PhN Frequency Multiplication steps: example 2 frequency (GHz) Optimal Osc. fundamental operation f t, fmax CMOS f t, fmax BiCMOS PLL synth. 50 100 200 300 Microwave Sub-THz THz Example : PLL freq =2 GHz, F out =300 GHz => N=150 x150 the oscillator fundamental frequency PFD CP 2 GHz x25 * 50 GHz 100 GHz x150 x2 300 GHz Div. * C. Jany et al. A novel ultra-low phase noise, programmable frequency multiplier-by-30 architecture. Application to 60-GHz frequency generation, ESSCIRC 2014. injection locking CEA. All rights reserved DACLE Division 2014 10
Cliquez pour modifier le style du Outline titre Introduction-context for sub-thz Some ideas for low PhN Architecture and design choices Examples on fabricated circuits CMOS 65nm BiCMOS 55nm Application to THz imagers : impact of PhN CEA. All rights reserved DACLE Division 2014 11
Cliquez Architecture pour modifier and le design style du choices titre Frequency Multiplication steps: design choices 50 GHz 100 GHz x2 300 GHz Self mixing High order oscillator : 2 nd harmonic - Push-Push - Push-Push-Push (Triple Push) 3 rd harmonic - Push-Push-Push-Push (Q-Push) - 4 th harmonic CEA. All rights reserved DACLE Division 2014 12
Cliquez Architecture pour modifier and le design style du choices titre N-Push principle: Example Push-Push: LC Elements On common mode node: - Even Harmonics combined - Odd harmonics out of phase 180 v + v - v + v - i + Example Triple-Push: Recombination Transmission line i v + L i - i L Z L i - i L v L =i L *Z L Z l i tot i 1 i 2 i 3 i 1 i 2 i 3 On common mode node: - Harmonics 3, 6, 9 combined - Other harmonics out of phase i tot CEA. All rights reserved DACLE Division 2014 13
Cliquez Architecture pour modifier and le design style du choices titre N-Push sub-harmonic locking principle: Example Push-Push: LC Elements Inj. 180 v + v - v + v - i + Inj. Example Triple-Push: Z l Recombination Transmission line i v + L i - i L Z L i - i L v L =i L *Z L i tot i 1 i 2 i 3 Inj. CEA. All rights reserved DACLE Division 2014 14
Cliquez pour modifier le style du Outline titre Introduction-context for sub-thz Some ideas for low PhN Architecture and design choices Examples on fabricated circuits CMOS 65nm Application to THz imagers : impact of PhN CEA. All rights reserved DACLE Division 2014 15
Injection (46 GHZ) Injection (47 GHz) Fout (276 GHz) Fout (282 GHz) 426 µm 141 µm Cliquez Examples pour modifier on fabricated le style du circuits titre Fabricated circuits in CMOS 65nm Triple-Push oscillator in CMOS 65nm: 682 µm 46 GHz 92GHz x2 276 GHz VDD Output matching 142 µm finj AC gnd AC gnd Input matching Vosc CEA. All rights reserved DACLE Division 2014 16
Cliquez Examples pour modifier on fabricated le style du circuits titre Fabricated circuits in CMOS 65nm Triple-Push oscillator measurement setup: 46 GHz 92GHz x2 276 GHz Synth. (PSG or VNA) FSU 67 (RS) Coaxial V WR 3.4 45 to 50 GHz J band mixer (RPG 220-325 GHz) mmw/sub-mmw PM4 Powermeter (Erickson) CEA. All rights reserved DACLE Division 2014 17
Cliquez Examples pour modifier on fabricated le style du circuits titre Fabricated circuits in CMOS 65nm Triple-Push oscillator measurement setup: 46 GHz 92GHz x2 276 GHz CEA. All rights reserved DACLE Division 2014 18
Injection Power (dbm) f osc (GHz) Cliquez Examples pour modifier on fabricated le style du circuits titre Fabricated circuits in CMOS 65nm 46 GHz 92GHz x2 276 GHz 15 10 Triple-Push oscillator measurement results: 5 278 277 276 275 274 273 272 271 0.5 0.7 0.9 1.1 1.3 1.5 V DD (V) Pdc: 15 90 mw Nominal at 276 GHz : 30 mw 0-5 -10-15 271.5 GHz 277.5 GHz VDD=1.4 V -20-25 45 45,5 46 46,5 47 VDD=0.8 V Finj (GHz) CEA. All rights reserved DACLE Division 2014 19
PhN @ 1MHz (dbc/hz) Cliquez Examples pour modifier on fabricated le style du circuits titre RF mmw PLL state of the art. PhN vs Osc. frequency -70 CICC 2006-80 -90-100 CICC 2007 VLSI 2013 VLSI 2012 ISSCC 2009 TCAS-II 2011 ISSCC 2013 ISSCC 2008 CICC 2006 ISSCC 2014 20log(6) CMOS 65nm (30 mw) -110 CICC 2009 ISSCC 2011 ASSCC 2010 VLSI 2013 VNA source @ 46 GHz -120 ISSCC 2014 VLSI 2011 VLSI 2013 ISSCC 2008-130 -140 ISSCC 2009 JSSC 2004 VLSI 2012 1 10 100 VCO PLL Frequency (GHz) CEA. All rights reserved DACLE Division 2014 20
Cliquez Examples pour modifier on fabricated le style du circuits titre THz oscillators-sources state of the art TABLE I Comparison of recently published Silicon Oscillators near 300 GHz Ref. [3] [4] [5] [6] [7] This Work * Tech. BiCMOS 90nm CMOS 65nm CMOS 65nm CMOS 65nm CMOS 65nm BiCMOS 55nm Fosc. (GHz) Tunning Range (%) Pout (dbm) Pdc PhN(1MHz) (mw) (dbc/hz) FOM(1MHz)* (dbc/hz) 280-303 8-14 105-80 -169.1 338 2-1 82-93 -184.4 288 - -1.5 275-87 -171,8 285-290 1.7-19 70-80.5-171,2 283-296 4.5-1.5 325-78 -162,1 272-303 10.8-9 52-105 -197 CEA. All rights reserved DACLE Division 2014 21
Cliquez pour modifier le style du Outline titre Introduction-context for sub-thz Some ideas for low PhN Architecture and design choices Examples on fabricated circuits CMOS 65nm Application to THz imagers : impact of PhN CEA. All rights reserved DACLE Division 2014 22
Application Cliquez to pour THz modifier imagers : le impact style du of titre PhN Sub-THz heterodyne pixel in CMOS 65nm Pixel Transmission antenna Bench photograph Pixel IF Output (~100 MHz) Parabolic mirrors First LETI s 280 GHz heterodyne receiver with integrated antenna (CMOS 65nm using the presented sub-harmonic injection locked oscillator) CEA. All rights reserved DACLE Division 2014 23
Application Cliquez to pour THz modifier imagers : le impact style du of titre PhN Sub-THz heterodyne pixel in CMOS 65nm: Raster scan image (step 0.75 mm) Humid zone Dry zone Rx with locked oscillator at 278 GHz Image Dynamic (max SNR) : 20 db CEA. All rights reserved DACLE Division 2014 24
Application Cliquez to pour THz modifier imagers : le impact style du of titre PhN Sub-THz heterodyne pixel in CMOS 65nm: raster scan image (step : 1.5 mm) Rx with locked oscillator at 278 GHz Image Dynamic (max SNR) : 45 db CEA. All rights reserved DACLE Division 2014 25
Application Cliquez to pour THz modifier imagers : le impact style du of titre PhN Sub-THz heterodyne pixel in CMOS 65nm: raster scan image (step : 1.5 mm) Rx with free run oscillator at 278 GHz Image Dynamic (max SNR) : 35 db (10 db loss on SNR!!!) CEA. All rights reserved DACLE Division 2014 26
Application Cliquez to pour THz modifier imagers : le impact style du of titre PhN Sub-THz heterodyne pixel in CMOS 65nm: raster scan image (step : 0.75 mm) Rx with locked oscillator at 278 GHz Image Dynamic (max SNR) : 50 db CEA. All rights reserved DACLE Division 2014 27
Cliquez pour modifier le style du Outline titre Introduction-context for sub-thz Some ideas for low PhN Architecture and design choices Examples on fabricated circuits CMOS 65nm BiCMOS 55nm Application to THz imagers : impact of PhN CONCLUSION CEA. All rights reserved DACLE Division 2014 28
Cliquez pour modifier le style Conclusion du titre Need of coherent (locked) frequency synthesis in the THz band. Low phase noise implies low frequency PLLs and high multiplication factors. Multiply, multiply, mutiply CEA. All rights reserved DACLE Division 2014 29
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