SERIAL I/O COMMON PROTOCOLS
RS-232 Fundamentals
What is RS-232 RS-232 is a popular communications interface for connecting modems and data acquisition devices (i.e. GPS receivers, electronic balances, data loggers,...) to computers. RS-232 can be plugged straight into the computer s serial port (know as COM or Comm port).
RS-232 Signals Architecturally RS-232 is a bi-directional point to point link. Two independent channels are established for two-way (fullduplex) communications. RS-232 can also carry additional signals used for flow control (RTS, CTS) and modem control (DCD, DTR, DSR, RI). (serial port - PC side)
RS-232 Line Driver Unbalanced Line Drivers Each signal appears on the interface connector as a voltage with reference to a signal ground. The idle state (MARK) has the signal level negative with respect to common whereas the active state (SPACE) has the signal level positive respest to the same reference.
RS-232 Speed How fast can RS-232 be? The maximum speed, according to the standard, is 20kbit/s. However, modern equipment can operate much faster than this. (i.e. Lynx can reach 115200 baud.) The length of the cable also plays a part in maximum speed. The longer the cable and the slower the speed at which you can obtain accurate results. A large wire capacitance and inductance limits the maximum length of the cable and/or the maximum speed; Moreover higher is the capacitance of the cable higer is the interference between two adjacent signal wire. 50 feet (15m) @ max baudrate is commonly quoted as the maximum distance. It is not specified in EIA standard but it s recommended respect these values.
RS-232 sw settings One byte of async data has: Start Bit = 1 (always); Stop bits = 1 (or 2) Data Bits = 8 (or 7); Parity = NONE (or EVEN or ODD) + 25-25
What is RS-485? RS-485 is a EIA standard interface which is very common in the data acquisition world RS-485 provides balanced transmission line which also can be shared in Multidrop mode. It allows high data rates communications over long distances in real world environments. How fast can RS-485 be? RS-485 was designed for greater distance and higher baudrates than RS-232. According to the standard, 100kbit/s is the maximum speed and distance up to 4000 feet (1200 meters) can be achieved.
RS-485 Line Driver Balanced Line Drivers Voltage produced by the driver appears across a pair of signal wires that transmit only one signal. Both wires are driven opposite. RS-485 driver has always the Enable direction control signal. Differential system provides noise immunity, because much of the common mode signal can be rejected by the receiver. So ground shifts and induced noise signals can be nullified.
RS-485 Network RS-485 provides Half-Duplex, Multidrop communications over a single twisted pair cable. The standard specifies up to 32 drivers and 32 receivers can share a multidrop network Terminator resistors avoid reflected signal MASTER SLAVE-2 SLAVE-3 SLAVE-1
RS-485 Half-duplex TX ENABLE RX Master RTX485+ RTX485-485GND TX ENABLE RX TX ENABLE RX TX ENABLE RX Slave 1 Slave 2 Slave N
RS-485 Full-duplex Potentially RS-485 interface can also use 4-wires to communicate in multidrop mode ENABLE TX RX Scanner TX485+ RX485+ TX485- RX485-485GND TX RX Other device ENABLE
RS-232 vs RS-485 The architectural difference between RS-232 and RS-485 is that 232 is a bi-directional point to point link, whereas 485 is a single channel bus. Electrically, each 232 signal uses a single wire with symmetric voltages about a common ground wire. 485 uses two wires to carry the single signal differentially. The big difference to the software is that only one device on a 485 bus can transmit at a time, whilst there is not similar limitation on RS232 because is a peer-to-peer link
RS-232 vs RS-485
I 2 C and SPI
I 2 C and SPI Serial communication protocols Meant for short distances inside the box Low complexity Low cost Low speed (a few Mbps at the fastest )
What is I 2 C? Shorthand for an Inter-integrated circuit bus Developed by Philips Semiconductor for TV sets in the 1980 s I 2 C devices include EEPROMs, thermal sensors, and real-time clocks Used as a control interface to signal processing devices that have separate data interfaces, e.g. RF tuners, video decoders and encoders, and audio processors. I 2 C bus has three speeds: Slow (under 100 Kbps) Fast (400 Kbps) High-speed (3.4 Mbps) I 2 C v.2.0 Limited to about 10 feet for moderate speeds
I 2 C Bus Configuration 2-wire serial bus Serial data (SDA) and Serial clock (SCL) Half-duplex, synchronous, multi-master bus No chip select or arbitration logic required Lines pulled high via resistors, pulled down via opendrain drivers (wired-and)
I 2 C Protocol 1. Master sends start condition (S) and controls the clock signal 2. Master sends a unique 7-bit slave device address 3. Master sends read/write bit (R/W) 0 - slave receive, 1 - slave transmit 4. Receiver sends acknowledge bit (ACK) 5. Transmitter (slave or master) transmits 1 byte of data
I 2 C Protocol (cont.) 6. Receiver issues an ACK bit for the byte received 7. Repeat 5 and 6 if more bytes need to be transmitted. 8.a) For write transaction (master transmitting), master issues stop condition (P) after last byte of data. 8.b) For read transaction (master receiving), master does not acknowledge final byte, just issues stop condition (P) to tell the slave the transmission is done
I 2 C Signals Start high-to-low transition of the SDA line while SCL line is high Stop low-to-high transition of the SDA line while SCL line is high Ack receiver pulls SDA low while transmitter allows it to float high Data transition takes place while SCL is low, valid while SCL is high
I 2 C Features Clock stretching when the slave (receiver) needs more time to process a bit, it can pull SCL low. The master waits until the slave has released SCL before sending the next bit. General call broadcast addresses every device on the bus 10-bit extended addressing for new designs. 7-bit addresses all exhausted
I 2 C Tradeoffs Advantages: Good for communication with on-board devices that are accessed occasionally. Easy to link multiple devices because of addressing scheme Cost and complexity do not scale up with the number of devices Disadvantages: The complexity of supporting software components can be higher than that of competing schemes ( for example, SPI ).
What is SPI? Shorthand for Serial Peripheral Interface Defined by Motorola on the MC68HCxx line of microcontrollers Generally faster than I 2 C, capable of several Mbps Applications: Like I 2 C, used in EEPROM, Flash, and real time clocks Better suited for data streams, i.e. ADC converters Full duplex capability, i.e. communication between a codec and digital signal processor
SPI Bus Configuration Synchronous serial data link operating at full duplex Master/slave relationship 2 data signals: MOSI master data output, slave data input MISO master data input, slave data output 2 control signals: SCLK clock /SS slave select (no addressing)
SPI vs. I 2 C For point-to-point, SPI is simple and efficient Less overhead than I 2 C due to lack of addressing, plus SPI is full duplex. For multiple slaves, each slave needs separate slave select signal More effort and more hardware than I 2 C
SPI Protocol 2 Parameters, Clock Polarity (CPOL) and Clock Phase (CPHA), determine the active edge of the clock CPOL CPHA Active edge 0 0 Rising 0 1 Falling 1 0 Falling 1 1 Rising Master and slave must agree on parameter pair values in order to communicate
CAN Protocol
ISO-OSI Reference Model 7. Application Layer CAN Layers 2. Data Link Layer 1. Physical Layer 6. Presentation Layer 5. Session Layer 4. Transport Layer 3. Network Layer HLPs: CANopen, DeviceNet, OSEK/VDX CAN Protocol Partially Implemented by High Layer Protocol (HLP)
CAN Bus Logic 1 Recessive (r) 0 Dominant (D) Two logic states on the CAN bus Node 1 Node 2 Node 3 Bus D D D D D D r D D r D D D r r D r D D D r D r D r r D D r r r r Wired-AND Function Bus in dominant state Bus in recessive state or idle
Typical CAN Node TXD CAN_H µcontroller CAN Controller CAN Transceiver RXD CAN_L CAN Bus is a simple 2-wire differential serial bus CAN Bus is terminated on each side by a 120 Ohm resistor CAN Bus
CAN Bit Coding & Bit Stuffing Bit Coding : NRZ (Non-Return-To-Zero code) does not ensure enough edges for synchronization Stuff Bits are inserted after 5 consecutive bits of the same level Stuff Bits have the inverse level of the previous bit. No deterministic encoding, frame length depends on transmitted data Number of consecutive bits with the same polarity
CAN Bus Access and Arbitration: CSMA/CD and AMP CSMA/CD: Carrier Sense Multiple Access / Collision Detection AMP: Arbitration by Message Priority
CAN Bus Synchronization Hard synchronization at Start Of Frame bit Re-Synchronization on each Recessive to Dominant bit