Johnson Counter Introduction The goal is to design a 4-bit Johnson counter with stop control that can count bidirectional, depending on the setting of the control inputs RIGHT and LEFT using the schematics mode of design entry on Spartan 3E Board. ISE Version: 9.2i or 10.1i Objective The purpose of this lab is: 1. To get familiar with the flip-flops. 2. To design an up/down Johnson counter using D flip-flops. 3. To implement the counter using Xilinx FPGA board. 4. To experimentally check the operation of the counter. The counter has an asynchronous reset (or clear) input which brings the outputs to 0 as soon as the RESET signal is asserted. The counter counts at the negative edge of the clock. When the RIGHT input is high, the counter counts in one direction and when LEFT input is high, it counts in the other direction, as shown in the state transition diagram. Counter should stop at a particular count when STOP input is high. Figure 1: State transition diagram for up/down counter. 1
Process 1. Create project using ISE 9.2i/10.1i 2. Test behavior of the sequence detector using Xilinx ISE. 3. Configure FPGA with the sequence detector 4. Test behavior of sequence detector on the Spartan 3E starter board Implementation 1. Open ISE Project Navigator. If a project is already open, go to the File menu and select Close Project. Now under the File menu select New Project. ISE will launch the New Project Wizard. In the Create New Project window under Project Name: enter your project name. Under Project Location click the button with the three dots and navigate to where you want the project to be located. Under Top-Level Source Type: make sure HDL is selected and then click Next>. 2. In the Device Properties window copy the settings from figure 3 and then click Next>. Figure 2 New Project Wizard - Device Properties settings. 3. Click Next> on the Create New Source window. Click Next>. 4. Click Ok and click Finish on the Project Summary window. You have created the project and in the workspace window of ISE you should see a project summary. You can close the project summary by going under the File menu and selecting Close. 2
5. In the Sources window, right click on the small box with the - symbol and click new source to open a new Schematic design entry in your project. Design your schematic here using symbols and save it. 6. After saving your project click Synthesis in the process window. Once synthesis is done successfully. Next step is to check the functionality of your design. 7. Right click on your project file and click new source, add test bench waveform and associate it with your design file. This will open a waveform associated with your design. Force the valid input values and save it. 8. Go to the pulldown menu in the Sources window and select Behavioral Simulation. Figure 3 Pull down menu in Sources window. 9. Highlight the.tbw file in the Sources window by clicking on it. In the Processes window, click on the small box with the + symbol that is next to the Xilinx ISE Simulator toolbox and then double click Simulate Behavioral Model to start the simulation. When you are done, close Simulation Window. 10. Go to the Source window pulldown menu and select Synthesis/Implementation and then click on source file (VHDL Design File) to highlight it. In the Processes window expand the User Constraints toolbox and double click Edit Constraints (Text). This will open.ucf in the ISE workspace. 3
Figure 4 Opening the UCF file. The user constraints file has been notated to show what board features have been connected to the inputs and outputs of VHDL Design File. Figure 5 The UCF file displayed in the ISE workspace. 11. It is time to program the Spartan 3E board. In the Processes window you have to run the Synthesize - XST, Implement Design, and Generate Programming File processes. Instead of doing each one separately, you can double click on Generate Programming File. This will run all the processes. 4
Figure 6 Running processes As the processes finish running they will be marked with a green checkmark to indicate no problems were encountered. The Implement Design process may generate warnings (yellow triangle with an exclamation point), warnings can be ignored. 12. Connect the Spartan 3E board to the computer and turn the board s power on. Expand the \ Generate Programming File process and double click on Configure Device (impact). This will launch the impact program. Click Finish on the Welcome to impact window. Figure 7 Starting impact impact will perform a boundary scan and will display three devices in the ISE workspace. Pictures of Xilinx IC packages represent the devices. In figure 9 you can see that no files are associated with the packages. 5
Figure 8 Devices shown in boundary scan You have to assign the.bit file to the Spartan 3E s FPGA. The FPGA is represented in the workspace by the picture of the Xilinx package labeled xc3s500e. The package should already be highlighted (as in figure 9). Click on top_sequence.bit in the Assign New Configuration File window and then click the Open button. The file is now associated with the FPGA and the next device is highlighted. Figure 9 Assigning *.bit file to xc3s500e. Click Bypass for the next two devices since we are not programming them and then click on an empty area inside the ISE workspace. Now right click on the xc3s500e and select Program from the drop down menu. 6
Figure 10 Programming the FPGA. Click Ok on the Programming Properties window (nothing needs to be selected for this tutorial). After the FPGA is programmed a Program Succeeded message will be displayed in the ISE workspace and a yellow LED will show the Spartan 3E has been configured. 13. The Spartan 3E is programmed as a sequence detector. The board will hold this program until the power is turned off, the reset button near the yellow LED is pressed, or you reprogram the board. 7