Señal RS232
SCI Señal desde y hacia el µc BREAK: Caracter con todos 0 lógicos IDLE: caracter con todos 1 lógicos
SCI estructura simplificada Se terminó de transferir un caracter al shift register TDRE SCIxD TC 11 bit Shift register 11 bit Shift register TX RX RDRF Llegó un nuevo caracter
SCI estructura del transmisor
SCI estructura del receptor
SCI registros RX EDGe Interrupt Generation (1: habilitado) SCIxBDH Line BreaK Detection Interrupt Enable (1: habilitado) SCIxBDL SBR12.. SBR0 -> 0 a 8191 Divisor para obtener Baud Rate (0: desactiva Baud generator) Baud Rate = BUSCLK / (16 * BR)
SCI registros SCISWAI 1: SCI Stops In WAIt mode M 1: 9 bits (start + 9 data bits + stop) ILT Idle Line Type 0: Idle count after start bit 1: Idle count after stop bit LOOPS 1: Enable RSRC Receiver SouRCe Select (si LOOPS= 1) 0: Loopback 1: Single Wire (TX) WAKE 0: IDLE 1: Address Mark PE Parity Enable (MSb) 1: Enable PT Parity Type 0: Even 1: Odd
SCI registros TCIE (TC) Transmission Complete Interrupt Enable 1: Enable ILIE (IDLE) Idle Line Interrupt Enable 1: Enable RE Receiver Enable 1: Enable SBK Send BreaK 1: Envía Break 0: Operación normal TIE (TE) Transmit Interrupt Enable 1: Enable RIE (RF) Receiver Interrupt Enable 1: Enable TE Transmitter Enable 1: Enable RWU Receiver Wake-Up 1: standby 0: normal
SCI registros R8 Noveno bit recibido (si M = 1, dato 9bit) T8 Noveno bit a transmitir (si M = 1, dato 9bit) TXDIR TX pin DIRection in single-wire mode 0: input 1: output TXINV TX data INVersion 0: normal 1: invertido Framing Error Interrupt Enable Parity Error Interrupt Enable OverRun Error Interrupt Enable Noise Error Interrupt Enable
SCI registros TDRE Transmit Data Register Empty Flag 1: Buffer TX vacío 0: Buffer TX lleno Para limpiar este flag, leer SCIxS1 y escribir SCIxD IDLE Idle Line Flag 1: línea Idle Para limpiar este flag: leer SCIxS1 y leer SCIxD Noise Flag Framing Error flag Receiver OverRun flag TC Transmission Complete flag 1: Transmisor ocioso 0: Transmisor activo Para limpiar este flag: leer SCIxS1 y escribir SCIxD RDRF Receive Data Register Full flag 1: Llegó un nuevo byte a SCIxD Para limpiar este flag: leer SCIxS1 y leer SCIxD Parity error Flag
SCI registros LBKDIF LIN Break Detect Interrupt Flag 0: No se detectó caracter LIN break Para limpiar este flag, escribir 1 en este bit RXEDGIF RX Pin active EDGe Interrupt Flag 0: No se flanco activo en RX Para limpiar este flag, escribir 1 en este bit RXINV RX data INVersion 0: normal 1: invertido BRK13 Break character generation length 1: 13 bits (14 si M = 1) 0: 10 bits (11 si M = 1) LBKDE Lin BreaK Detection Enabled 1: Habilitada RWUID Rx Wake-Up Idle Detection 1: El caracter IDLE que produce Wake-Up setea bit IDLE RAF Receiver Active Flag 1: Receptor activo
SCI registros
SCI ejemplo SCI1C1 = 0x00; /* Loop mode disabled, disable SCI, Tx output not inverted, 8-bit characters, idle line wakeup, disable parity bit */ SCI1C2 = 0x00101100 ; /* Enable SCI receive interrupts, Enable Tx & Rx */ SCI1C3 = 0x00; /* Disable all error interrupts */ ***************************************************************** * BUSCLK 4 MHz * * Baud Rate = -------------------- = ---------- = 9600 bps * * [SBR12:SBR0] x 16 26 x 16 * ***************************************************************** /* For this example, the internal bus clock is used, SCI1BDH = 0x00; // SCI1BDH [SBR12:SBR8] + SCI1BDL [SBR7:SBR0] SCI1BDL = 0x1A; // SCI1BDH and SCI1BHL control the 13 bit // prescale divisor for the SCI module baud rate.... interrupt 17 void SCI_RX_isr (void) { SCI1S1; // Acknowledge SCI Receiver Full Flag dato_recibido = SCID; while (SCI1S1_TDRE == 0); // Wait for the transmitter to be empty SCI1D = dato_mandar; //Manda dato }
SCI ejemplo unsigned char buffer[10]; unsigned char bp = 0; unsigned char proc_mensaje = 0; SCIBD = 52; // divisor = 52 baud = 8MHz / 52 / 16 = 9615,38 9600 SCIC1 = 0b00000010; // paridad habilitada paridad par SCIC2 = 0b00101100; // habilita interrupción de recepción, transmisor y receptor SCIC3 = 0; for(;;) { if (proc_mensaje == 1) { while (SCIS1_TC!= 1); // espera TC = 1 SCID = 'A'; //envía 65 while (SCIS1_TC!= 1); // espera TC = 1 SCID = 0x42; //envía 66 } }.. interrupt 17 void rx_int() { SCIS1; // Limpia flag RDRF Buffer[bp++] = SCID; if (bp == 11) { bp = 0; proc_mensaje = 1; } }
The receiver samples the RxD pin at the RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock is resynchronized at the following times (see Figure 9-6): After every start bit After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and RT10 samples returns a valid logic 0) To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.