nc. MC8HCA8 HCMOS Single-Chip Microcontroller For More Information On This Product,
nc. For More Information On This Product,
nc. TABLE OF CONTENTS Paragraph Page Number Title Number INTRODUCTION. Features...-.. Hardware Features...-.. Software Features...-. General Description...-. Programmer s Model...-. Summary of M8HC Family...- SIGNAL DESCRIPTIONS AND OPERATING MODES. Signal Pin Descriptions...-.. Input Power (V DD ) and Ground (V SS )...-.. Reset (RESET)...-.. Crystal Driver and External Clock Input (XTAL, EXTAL)...-.. E Clock Output (E)...-.. Interrupt Request (IRQ)...-.. Non-Maskable Interrupt (XIRQ)...-..7 Mode A/Load Instruction Register and Mode B/Standby Voltage (MODA/ LIR, MODB/V STBY ) -..8 A/D Converter Reference Voltages (V RL, V RH )...-..9 Strobe B and Read/Write (STRB/R/W)...-.. Strobe A and Address Strobe (STRA/AS)...-.. Port Signals...-... Port A...-... Port B...-... Port C...-... Port D...-... Port E...-. Operating Modes...-.. Single-Chip Operating Mode...-.. Expanded Multiplexed Operating Mode...-.. Special Bootstrap Operating Mode...-8.. Additional Boot Loader Program Options...-.. Special Test Operating Mode...- ON-CHIP MEMORY. Memory Maps...-. RAM and I/O Mapping Register (INIT)...-. ROM...-. RAM...-. EEPROM...-.. EEPROM Programming Control Register (PPROG)...- iii For More Information On This Product,
nc... Programming/Erasing Internal EEPROM...-7... Read...-7... Programming...-7... Bulk Erase...-8... Row Erase...-8... Byte Erase...-9.. System Configuration Register (CONFIG)...-9... Programming and Erasure of the CONFIG Register...-... Operation of the Configuration Mechanism...- PARALLEL I/O. General-Purpose I/O (Ports C and D)...-. Fixed Direction I/O (Ports A, B, and E)...-. Simple Strobed I/O...-.. Strobed Input Port C...-.. Strobed Output Port B...-. Full Handshake I/O...-.. Input Handshake Protocol...-.. Output Handshake Protocol...-. Parallel I/O Control Register (PIOC)...- SERIAL COMMUNICATIONS INTERFACE. Overview and Features...-.. SCI Two-Wire System Features...-.. SCI Receiver Features...-.. SCI Transmitter Features...-. Data Format...-. Wake-Up Feature...-. Receive Data (RxD)...-. Start Bit Detection...-. Transmit Data (TxD)...-.7 Functional Description...-.8 SCI Registers...-.8. Serial Communications Data Register (SCDR)...-.8. Serial Communications Control Register (SCCR)...-8.8. Serial Communications Control Register (SCCR)...-8.8. Serial Communications Status Register (SCSR)...-.8. Baud Rate Register (BAUD)...- SERIAL PERIPHERAL INTERFACE. Overview and Features...-. SPI Signal Descriptions...-.. Master In Slave Out (MISO)...-.. Master Out Slave In (MOSI)...-.. Serial Clock (SCK)...- For More Information On This Product, MC8HCA8 TECHNICAL DATA
nc... Slave Select (SS)...-. Functional Description...-. SPI Registers...-.. Serial Peripheral Control Register (SPCR)...-.. Serial Peripheral Status Register (SPSR)...-.. Serial Peripheral Data l/o Register (SPDR)...- 7 ANALOG-TO-DIGITAL CONVERTER 7. Conversion Process...7-7. Channel Assignments...7-7. Single-Channel Operation...7-7. Multiple-Channel Operation...7-7. Operation in STOP and WAIT Modes...7-7. A/D Control/Status Register (ADCTL)...7-7.7 A/D Result Registers,,, and (ADR, ADR, ADR, and ADR)...7-7.8 A/D Power-Up and Clock Select...7-8 PROGRAMMABLE TIMER, RTI, AND PULSE ACCUMULATOR 8. Programmable Timer...8-8.. Counter...8-8.. Input Capture...8-8.. Output Compare...8-8.. Output Compare I/O Pin Control...8-8.. Timer Compare Force Register (CFORC)...8-8.. Output Compare Mask Register (OCM)...8-8..7 Output Compare Data Register (OCD)...8-8..8 Timer Control Register (TCTL)...8-8..9 Timer Control Register (TCTL)...8-8.. Timer Interrupt Mask Register (TMSK)...8-8.. Timer Interrupt Flag Register (TFLG)...8-8.. Timer Interrupt Mask Register (TMSK)...8-8.. Timer Interrupt Flag Register (TFLG)...8-7 8. Real-Time Interrupt...8-8 8. Pulse Accumulator...8-8 8.. Pulse Accumulator Control Register (PACTL)...8-8 9 RESETS, INTERRUPTS, AND LOW POWER MODES 9. Resets...9-9.. External RESET Pin...9-9.. Power-On Reset...9-9... CPU...9-9... Memory Map...9-9... Parallel l/o...9-9... Timer...9-9... Real-Time Interrupt...9- v For More Information On This Product,
nc. 9... Pulse Accumulator...9-9...7 COP...9-9...8 SCI Serial l/o...9-9...9 SPI Serial l/o...9-9... A/D Converter...9-9... System...9-9.. Computer Operating Properly (COP) Reset...9-9.. Clock Monitor Reset...9-9.. Configuration Options Register (OPTION)...9-9. Interrupts...9-7 9.. Software Interrupt (SWI)...9-9 9.. Illegal Opcode Trap...9-9 9.. Interrupt Mask Bits in Condition Code Register...9-9 9.. Priority Structure...9-9.. Highest Priority I Interrupt Register (HPRIO)...9-9. Low-Power Modes...9-7 9.. WAIT Instruction...9-7 9.. STOP Instruction...9-7 CPU, ADDRESSING MODES, AND INSTRUCTION SET. CPU Registers...-.. Accumulators A and B...-.. Index Register X (IX)...-.. Index Register Y (IY)...-.. Stack Pointer (SP)...-.. Program Counter (PC)...-.. Condition Code Register (CCR)...-... Carry/Borrow (C)...-... Overflow (V)...-... Zero (Z)...-... Negative (N)...-... Interrupt Mask (I)...-... Half Carry (H)...-...7 X Interrupt Mask (X)...-...8 Stop Disable (S)...-. Addressing Modes...-.. Immediate Addressing...-.. Direct Addressing...-.. Extended Addressing...-.. Indexed Addressing...-.. Inherent Addressing...-.. Relative Addressing...-..7 Prebyte...-. Instruction Set...- A ELECTRICAL CHARACTERISTICS MC8HCA8 TECHNICAL DATA For More Information On This Product,
nc. B MECHANICAL DATA AND ORDERING INFORMATION B. Pin Assignments... B- B. Package Dimensions... B- C DEVELOPMENT SUPPORT C. M8HCEVB Evaluation Board... C- C.. EVB Features... C- C. M8HCEVBU Universal Evaluation Board... C- C.. EVBU Features... C- C. M8HCEVM Evaluation Module... C- C.. EVM Features... C- C. MMDS Modular Development System... C- C.. MMDSFeatures... C- SUMMARY OF CHANGES vii For More Information On This Product,
nc. MC8HCA8 TECHNICAL DATA For More Information On This Product,
Figure nc. LIST OF ILLUSTRATIONS Page - Block Diagram... - - Programming Model... - - Common Crystal Connections... - - External Oscillator Connections... - - One Crystal Driving Two MCUs... - - Address/Data Demultiplexing... -8 - Memory Maps... - - Data Format... - - Sampling Technique Used on All Bits... - - Examples of Start Bit Sampling Techniques... - - SCI Artificial Start Following a Framing Error... - - SCI Start Bit Following a Break... - - Serial Communications Interface Block Diagram... -7-7 Rate Generator Division... - - Data Clock Timing Diagram... - - Serial Peripheral Interface Block Diagram... - - Serial Peripheral Interface Master-Slave Interconnection... - 7- A/D Conversion Sequence... 7-7- A/D Pin Model... 7-9- Reset Timing... 9-9- Simple LVI Reset Circuit... 9-9- Interrupt Stacking Order... 9-9 9- Processing Flow Out of Resets (Sheet of )... 9-9- Processing Flow Out of Resets (Sheet of )... 9-9- Interrupt Priority Resolution (Sheet of )... 9-9- Interrupt Priority Resolution (Sheet of )... 9-9- Interrupt Source Resolution Within SCI... 9- - Programming Model... - - Special Operations... - A- Test Methods...A- A- Timer Inputs...A-7 A- POR and External Reset Timing Diagram...A-8 A- STOP Recovery Timing Diagram...A-9 A- WAIT Recovery Timing Diagram...A- A- Interrupt Timing Diagram...A- A-7 Port Write Timing Diagram...A- A-8 Port Read Timing Diagram...A- A-9 Simple Output Strobe Timing Diagram...A- A- Simple Input Strobe Timing Diagram...A- A- Port C Input Handshake Timing Diagram...A- A- Port C Output Handshake Timing Diagram...A- A- Three-State Variation of Output Handshake Timing Diagram (STRA Enables Output Buffer) A- A- Multiplexed Expansion Bus Timing Diagram...A- A-8 a) SPI Master Timing (CPHA = )...A- ix For More Information On This Product,
nc. A-8 b) SPI Master Timing (CPHA = )...A- A- SPI Timing Diagram ( of )...A- A- c) SPI Slave Timing (CPHA = )...A- A- d) SPI Slave Timing (CPHA = )...A- A- SPI Timing Diagrams ( of )...A- B- -Pin PLCC...B- B- 8-Pin DIP...B- B- -Pin QFP...B- B- M8HC P/N Options...B- MC8HCA8 TECHNICAL DATA For More Information On This Product,
nc. LIST OF TABLES Table Page - M8HC Family Devices... - - Operating Modes vs. MODA and MODB... - - Port Signal Summary... -7 - Bootstrap Mode Interrupt Vectors... -9 - Register and Control Bit Assignments... - - Handshake l/o Operations Summary... - - First Prescaler Stage... - - Second Prescaler Stage... - - Prescaler Highest Baud Rate Frequency Output... - - Transmit Baud Rate Output for a Given Prescaler Output... - - Serial Peripheral Rate Selection... - 7- Analog-to-Digital Channel Assignments... 7-8- Real Time Interrupt Rate versus RTR and RTR... 8-9 9- COP Timeout Period versus CR and CR... 9-9- IRQ Vector Interrupts... 9-8 9- Interrupt Vector Assignments... 9-8 9- SCI Serial System Interrupts... 9-9 9- Mode Bits Relationship... 9-9- Highest Priority I Interrupt versus PSEL[:]... 9-7 9-7 Pin State Summary for RESET, STOP, and WAIT... 9-8 - MC8HCA8 Instructions, Addressing Modes, and Execution Times... - - Cycle-by-Cycle Operation Inherent Mode... - - Cycle-by-Cycle Operation Immediate Mode... - - Cycle-by-Cycle Operation Direct Mode... - - Cycle-by-Cycle Operation Extended Mode... -8 - Cycle-by-Cycle Operation Indexed X Mode... -9-7 Cycle-by-Cycle Operation Indexed Y Mode... - -8 Cycle-by-Cycle Operation Relative Mode... - A- Maximum Rating...A- A- Thermal Characteristics...A- A- DC Electrical Characteristics...A- A- DC Electrical Characteristics (MC8LA8)...A- A- Control Timing...A- A- Control Timing (MC8LA8)...A- A- Peripheral Port Timing...A- A- Peripheral Port Timing (MC8LA8)...A- A- Analog-To-Digital Converter Characteristics...A-7 A- Analog-To-Digital Converter Characteristics (MC8LA8)...A-8 A-7 Expansion Bus Timing...A-9 A-7 Expansion Bus Timing (MC8LA8)...A- A-8 Serial Peripheral Interface (SPI) Timing...A- A-8 Serial Peripheral Interface (SPI) Timing (MC8LA8)...A- xi For More Information On This Product,
nc. A-9 EEPROM Characteristics...A- A-9 EEPROM Characteristics (MC8LA8)...A- B- Ordering Information...B- MC8HCA8 TECHNICAL DATA For More Information On This Product,
nc. INTRODUCTION The HCMOS MC8HCA8 is an advanced 8-bit microcontroller (MCU) with highly sophisticated on-chip peripheral capabilities. A fully static design and high-density complementary metal-oxide semiconductor (HCMOS) fabrication process allow E-series devices to operate at frequencies from MHz to dc, with very low power consumption.. Features The following are some of the hardware and software highlights... Hardware Features 8 Kbytes of ROM Bytes of EEPROM Bytes of RAM (All Saved During Standby) Relocatable to Any K Boundary Enhanced -Bit Timer System: Four Stage Programmable Prescaler Three Input Capture Functions Five Output Compare Functions 8-Bit Pulse Accumulator Circuit Enhanced NRZ Serial Communications Interface (SCI) Serial Peripheral Interface (SPI) Eight Channel, 8-Bit Analog-to-Digital Converter Real Time Interrupt Circuit Computer Operating Properly (COP) Watchdog System Available in Dual-In-Line or Leaded Chip Carrier Packages.. Software Features Enhanced M8/M8 Instruction Set x Integer and Fractional Divide Features Bit Manipulation WAIT Mode STOP Mode. General Description The high-density CMOS technology (HCMOS) used on the MC8HCA8 combines smaller size and higher speeds with the low power and high noise immunity of CMOS. On-chip memory systems include 8 Kbytes of ROM, bytes of electrically erasable programmable ROM (EEPROM), and bytes of static RAM. A block diagram of the MC8HCA8 is shown in Figure -. Major peripheral functions are provided on-chip. An eight channel analog-to-digital (A/D) converter is included with eight bits of resolution. An asynchronous serial communications interface INTRODUCTION MOTOROLA TECHNICAL DATA For More Information On This Product, -
nc. (SCI) and a separate synchronous serial peripheral interface (SPI) are included. The main -bit free-running timer system has three input capture lines, five output compare lines, and a real-time interrupt function. An 8-bit pulse accumulator subsystem can count external events or measure external periods. Self monitoring circuitry is included on-chip to protect against system errors. A computer operating properly (COP) watchdog system protects against software failures. A clock monitor system generates a system reset in case the clock is lost or runs too slow. An illegal opcode detection circuit provides a non-maskable interrupt if an illegal opcode is detected. Two software controlled operating modes, WAIT and STOP, are available to conserve additional power. COP PULSE ACCUMULATOR MODA/ LIR MODE CONTROL TIMER SYSTEM PORT A MODB/ V STBY PERIODIC INTERRUPT PA7/PAI/OC PA/OC/OC PA/OC/OC PA/OC/OC PA/OC/OC PA/IC PA/IC PA/IC XTAL EXTAL OSCILLATOR CLOCK LOGIC PORT B E BUS EXPANSION ADDRESS PB7/A PB/A PB/A PB/A PB/A PB/A PB/A9 PB/A8 CPU IRQ XIRQ INTERRUPT LOGIC ADDRESS/DATA STROBE AND HANDSHAKE PARALLEL I/O CONTROL PORT C PC7/A7/D7 PC/A/D PC/A/D PC/A/D PC/A/D PC/A/D PC/A/D PC/A/D RESET R/W AS STRB/R/W STRA/AS SPI SS SCK MOSI MISO PD/SS PD/SCK PD/MOSI PD/MISO 8 KBYTES ROM BYTES EEPROM BYTES RAM CONTROL PORT D SCI TxD RxD PD/TxD PD/RxD A/D CONVERTER PORT E V DD V SS V RH V RL *PE7/AN7 *PE/AN *PE/AN *PE/AN PE/AN PE/AN PE/AN PE/AN * NOT BONDED ON 8-PIN VERSION. A8 BLOCK Figure - Block Diagram. Programmer s Model In addition to being able to execute all M8 and M8 instructions, the MC8HCA8 allows execution of 9 new opcodes. Figure - shows the seven CPU registers which are available to the programmer. INTRODUCTION MC8HCA8 - For More Information On This Product, TECHNICAL DATA
nc. 7 A 7 B D IX IY SP PC 7 S X H I N Z V C 8-BIT ACCUMULATORS A & B OR -BIT DOUBLE ACCUMULATOR D INDEX REGISTER X INDEX REGISTER Y STACK POINTER PROGRAM COUNTER CONDITION CODES. Summary of M8HC Family Figure - Programming Model CARRY/BORROW FROM MSB OVERFLOW Table - and the following paragraphs summarize the current members of the M8HC family of MCUs. This technical data book describes the MC8HCA8 version and can be used as a primary reference for several other versions of the M8HC family. However, with the exception of the CPU, some newer members differ greatly from the MC8HCA8 MCU and their respective technical literature should be referenced. Several of the device series within the M8HC family have x and x versions. These are identical to the main member of the series but have some of their on-chip resources disabled. For instance, an MC8HCA is identical to the MC8HCA8 except that its ROM is disabled. An MC8HCA has disabled EPROM and EE- PROM arrays. Refer to Table -. Nearly all series within the M8HC family have both a ROM version and an EPROM version. Any device in the M8HC family that has a 7 preceding the is a device containing EPROM instead of ROM (e.g., MC8HC7E9). These devices operate exactly as the custom ROM-based version (e.g., MC8HCE9) but can be programmed by the user. EPROM-based devices in a windowed package can be erased and reprogrammed indefinitely. EPROM-based devices in standard packages are one-time-programmable (OTP). Refer to Table -. ZERO NEGATIVE I-INTERRUPT MASK HALF CARRY (FROM BIT ) X-INTERRUPT MASK STOP DISABLE INTRODUCTION MOTOROLA TECHNICAL DATA For More Information On This Product, -
nc. Table - M8HC Family Devices Device RAM ROM EPROM EEPROM COMMENTS MC8HCA8 8K -bit timer; 8 channel 8-bit A/D, SCI, SPI MC8HCA7 8K MC8HCA MC8HCA MC8HCD 9 K -bit timer; SCI, SPI MC8HC7D 9 K MC8HCD 9 MC8HCED -bit timer; SCI, SPI MC8HCE9 K -bit timer; SCI, SPI, 8 channel 8-bit A/D MC8HC7E9 K MC8HCE8 K MC8HCE MC8HCE MC8HC8E 8 -bit timer; SCI, SPI, 8 channel 8-bit A/D, K EEPROM MC8HCE 78 K -bit timer; SCl, SPI, 8 channel 8-bit A/D, MC8HC7E 78 K K ROM/EPROM MC8HCF nonmultiplexed bus, 8 channel 8-bit A/D, chip selects, SCI, SPI MC8HCG7 K nonmultiplexed bus, 8 channel -bit A/D, channel PWM, MC8HCG K SCI, SPI, I/O pins MC8HC7G K MC8HCG MC8HCK 78 K nonmultiplexed bus, memory expansion to MB, MC8HC7K 78 K 8 channel 8-bit A/D, channel PWM, chip selects MC8HCK 78 K MC8HCK 78 MC8HCK 78 MC8HCKA 78 K nonmultiplexed bus, 8 channel 8-bit A/D, SCI, SPI, MC8HC7KA 78 K channel PWM MC8HCKA K MC8HC7KA K MC8HCL K multiplexed bus, -bit timer; 8 channel 8-bit A/D, SCI, SPI MC8HC7L K MC8HCL K MC8HCL MC8HCL MC8HCM 8 K nonmultiplexed bus, 8 channel 8-bit A/D, channel PWM, MC8HC7M 8 K DMA, on-chip math coprocessor, SCI, SPI MC8HCN 78 K nonmultiplexed bus, channel 8-bit A/D, channel 8- bit D/A, MC8HC7N 78 K channel PWM, on-chip math coprocessor, SCI, SPI MC8HCP K nonmultiplexed bus, PLL, 8 channel 8-bit A/D, channel PWM, MC8HC7P K SCI ( with Ml bus), SPI, I/O pins INTRODUCTION MC8HCA8 - For More Information On This Product, TECHNICAL DATA
nc. SIGNAL DESCRIPTIONS AND OPERATING MODES The signal descriptions and operating modes are presented in this section. When the microcontroller is in an expanded multiplexed operating mode, 8 pins change function to support a multiplexed address/data bus.. Signal Pin Descriptions The following paragraphs provide a description of the input/output signals. Reference is made, where applicable, to other sections that contain more detail about the function being performed... Input Power (V DD ) and Ground (V SS ) Power is supplied to the microcontroller using these pins. V DD is the positive power input and V SS is ground. Although the MC8HCA8 is a CMOS device, very fast signal transitions are present on many of its pins. Short rise and fall times are present even when the microcontroller is operating at slow clock rates. Special care must be taken to provide good power supply bypassing at the MCU. Recommended bypassing would include a. µf ceramic capacitor between the V DD and V SS pins and physically adjacent to one of the two pins. A bulk capacitance, whose size depends on the other circuitry in the system, should also be present on the circuit board... Reset (RESET) This active low bidirectional control signal is used as an input to initialize the MC8HCA8 to a known start-up state, and as an open-drain output to indicate that an internal failure has been detected in either the clock monitor or computer operating properly (COP) watchdog circuit. This reset signal is significantly different from the reset signal used on other Motorola MCUs. Please refer to 9 RESETS, INTERRUPTS, AND LOW POWER MODES before designing circuitry to generate or monitor this signal... Crystal Driver and External Clock Input (XTAL, EXTAL) These two pins provide the interface for either a crystal or a CMOS compatible clock to control the internal clock generator circuitry. The frequency applied to these pins shall be four times higher than the desired E clock rate. The XTAL pin is normally left unterminated when using an external CMOS compatible clock input to the EXTAL pin. However, a K to K load resistor to ground may be used to reduce RFI noise emission. The XTAL output is normally intended to drive only a crystal. The XTAL output may be buffered with a high-input-impedance buffer such as the 7HC, or it may be used to drive the EXTAL input of another M8HC. In all cases take extra care in the circuit board layout around the oscillator pins. Load capacitances shown in the oscillator circuits include all stray layout capacitances. Refer to Figure -, Figure -, and Figure - for diagrams of oscillator circuits. SIGNAL DESCRIPTIONS AND OPERATING MODES MOTOROLA TECHNICAL DATA For More Information On This Product, -
nc. EXTAL pf * MCU XTAL MΩ x E CRYSTAL pf * * THIS VALUE INCLUDES ALL STRAY CAPACITANCES. COMMON XTAL CONN Figure - Common Crystal Connections EXTAL FIRST MCU XTAL MCU EXTAL XTAL NC x E CMOS-COMPATIBLE EXTERNAL OSCILLATOR Figure - External Oscillator Connections MΩ x E CRYSTAL pf * pf * Ω NC EXT EXTAL CONN EXTAL SECOND MCU XTAL * THIS VALUE INCLUDES ALL STRAY CAPACITANCES. DUAL-MCU XTAL CONN Figure - One Crystal Driving Two MCUs SIGNAL DESCRIPTIONS AND OPERATING MODES MC8HCA8 - For More Information On This Product, TECHNICAL DATA
nc... E Clock Output (E) This is the output connection for the internally generated E clock which can be used as a timing reference. The frequency of the E clock output is actually one fourth that of the input frequency at the XTAL and EXTAL pins. When the E clock output is low an internal process is taking place and, when high, data is being accessed. The E clock signal is halted when the MCU is in STOP mode... Interrupt Request (IRQ) The IRQ input provides a means for requesting asynchronous interrupts to the MC8HCA8. It is program selectable (OPTION register) with a choice of either negative edge-sensitive or level-sensitive triggering, and is always configured to levelsensitive triggering by reset. The IRQ pin requires an external pull-up resistor to V DD (typically.7k ohm)... Non-Maskable Interrupt (XIRQ) This input provides a means for requesting a non-maskable interrupt, after reset initialization. During reset, the X bit in the condition code register is set and any interrupt is masked until MCU software enables it. The XIRQ input is level sensitive and requires an external pull-up resistor to V DD...7 Mode A/Load Instruction Register and Mode B/Standby Voltage (MODA/LIR, MODB/V STBY ) During reset, MODA and MODB are used to select one of the four operating modes. Refer to Table -. Paragraph. Operating Modes provides additional information. Table - Operating Modes vs. MODA and MODB MODB MODA Mode Selected Single Chip Expanded Multiplexed Special Bootstrap Special Test After the operating mode has been selected, the LIR pin provides an open-drain output to indicate that an instruction is starting. All instructions are made up of a series of E clock cycles. The LIR signal goes low during the first E clock cycle of each instruction (opcode fetch). This output is provided as an aid in program debugging. The V STBY signal is used as the input for RAM standby power. When the voltage on this pin is more than one MOS threshold (about.7 volts) above the V DD voltage, the internal -byte RAM and part of the reset logic are powered from this signal rather than the V DD input. This allows RAM contents to be retained without V DD power applied to the MCU. Reset must be driven low before V DD is removed and must remain low until V DD has been restored to a valid level. SIGNAL DESCRIPTIONS AND OPERATING MODES MOTOROLA TECHNICAL DATA For More Information On This Product, -
nc...8 A/D Converter Reference Voltages (V RL, V RH ) These two inputs provide the reference voltages for the analog-to-digital converter circuitry...9 Strobe B and Read/Write (STRB/R/W) This signal acts as a strobe B output or as a data bus direction indicator depending on the operating mode. In single-chip operating mode, the STRB output acts as a programmable strobe for handshake with other parallel l/o devices. Refer to PARALLEL I/O for additional information. In expanded multiplexed operating mode, R/W is used to control the direction of transfers on the external data bus. A low on the R/W signal indicates data is being written to the external data bus. A high on this signal indicates that a read cycle is in progress. R/W will stay low during consecutive data bus write cycles, such as in a double-byte store. The NAND of inverted R/W with the E clock should be used as the write enable signal for an external static RAM... Strobe A and Address Strobe (STRA/AS) This signal acts as an edge detecting strobe A input or as an address strobe bus control output depending on the operating mode. In single-chip operating mode, the STRA input acts as a programmable strobe for handshake with other parallel l/o devices. Refer to PARALLEL I/O for additional information. In expanded multiplexed operating mode, the AS output is used to demultiplex the address and data signals at port C. Refer to.. Expanded Multiplexed Operating Mode for additional information... Port Signals Ports A, D, and E signals are independent of the operating mode. Port B provides eight general purpose output signals in single-chip operating modes and provides eight high-order address signals when the microcontroller is in expanded multiplexed operating modes. Port C provides eight general purpose input/output signals when the microcontroller is in singlechip operating modes. When the microcontroller is in expanded multiplexed operating modes, port C is used for a multiplexed address/data bus. Table - shows a summary of the port signals as they relate to the operating modes. Unused inputs and l/o pins configured as inputs should be terminated high or low. SIGNAL DESCRIPTIONS AND OPERATING MODES MC8HCA8 - For More Information On This Product, TECHNICAL DATA
nc.... Port A Port A may be configured for: three input capture functions (IC, IC, IC), four output compare functions (OC, OC, OC, OC), and either a pulse accumulator input (PAI) or a fifth output compare function (OC). Refer to 8. Programmable Timer for additional information. Any port A pin that is not used for its alternate timer function may be used as a generalpurpose input or output line.... Port B While in single-chip operating modes, all of the port B pins are general-purpose output pins. During MCU reads of this port, the level sensed at the input side of the port B output drivers is read. Port B may also be used in a simple strobed output mode where an output pulse appears at the STRB signal each time data is written to port B. When in expanded multiplexed operating modes, all of the port B pins act as high order address output signals. During each MCU cycle, bits 8 through of the address are output on the PB-PB7 lines respectively.... Port C While in single-chip operating modes, all port C pins are general-purpose input/output pins. Port C inputs can be latched by providing an input transition to the STRA signal. Port C may also be used in full handshake modes of parallel l/o where the STRA input and STRB output act as handshake control lines. When in expanded multiplexed operating modes, all port C pins are configured as multiplexed address/data signals. During the address portion of each MCU cycle, bits through 7 of the address are output on the PC-PC7 lines. During the data portion of each MCU cycle (E high), pins through 7 are bidirectional data signals (D-D7). The direction of data at the port C pins is indicated by the R/W signal.... Port D Port D pins - may be used for general-purpose l/o signals. Port D pins alternately serve as the serial communications interface (SCI) and serial peripheral interface (SPI) signals when those subsystems are enabled. Pin PD is the receive data input (RxD) signal for the serial communication interface (SCI). Pin PD is the transmit data output (TxD) signal for the SCI. Pins PD through PD are dedicated to the SPI. PD is the master-in-slave-out (MI- SO) signal. PD is the master-out-slave-in (MOSI) signal. PD is the serial clock (SCK) signal and PD is the slave select (SS) input. SIGNAL DESCRIPTIONS AND OPERATING MODES MOTOROLA TECHNICAL DATA For More Information On This Product, -
... Port E Port E is used for general-purpose inputs and/or analog-to-digital (A/D) input channels. Reading port E during the sampling portion of an A/D conversion could cause very small disturbances and affect the accuracy of that result. If very high accuracy is required, avoid reading port E during conversions.. Operating Modes nc. There are four operating modes for the MC8HCA8: single-chip operating mode, expanded multiplexed operating mode, special bootstrap operating mode, and special test operating mode. Table - shows how the operating mode is selected. The following paragraphs describe these operating modes... Single-Chip Operating Mode In single-chip operating mode, the MC8HCA8 functions as a monolithic microcontroller without external address or data buses. Port B, port C, strobe A, and strobe B function as general purpose l/o and handshake signals. Refer to PARALLEL I/O for additional information... Expanded Multiplexed Operating Mode In expanded multiplexed operating mode, the MC8HCA8 has the capability of accessing a Kbyte address space. This total address space includes the same onchip memory addresses used for single-chip operating mode plus external peripheral and memory devices. The expansion bus is made up of port B and port C, and control signals AS and R/W. Figure - shows a recommended way of demultiplexing low order addresses from data at port C. The address, R/W, and AS signals are active and valid for all bus cycles including accesses to internal memory locations. SIGNAL DESCRIPTIONS AND OPERATING MODES MC8HCA8 - For More Information On This Product, TECHNICAL DATA
nc. Table - Port Signal Summary Port-Bit Single Chip and Bootstrap Mode Expanded Multiplexed and Special Test Mode A- A- A- A- A- A- A- A-7 PA/IC PA/IC PA/IC PA/OC/OC PA/OC/OC PA/OC/OC PA/OC/OC PA7/PAI/OC PA/IC PA/IC PA/IC PA/OC/OC PA/OC/OC PA/OC/OC PA/OC/OC PA7/PAI/OC B- B- B- B- B- B- B- B-7 C- C- C- C- C- C- C- C-7 D- D- D- D- D- D- E- E- E- E- E- E- E- E-7 ## Not bonded in 8-pin versions PB PB PB PB PB PB PB PB7 PC PC PC PC PC PC PC PC7 PD/RXD PD/TXD PD/MISO PD/MOSI PD/SCK PD/SS STRA STRB PE/AN PE/AN PE/AN PE/AN PE/AN## PE/AN## PE/AN## PE7/AN7## A8 A9 A A A A A A A/D A/D A/D A/D A/D A/D A/D A7/D7 PD/RXD PD/TXD PD/MISO PD/MOSI PD/SCK PD/SS AS R/W PE/AN PE/AN PE/AN PE/AN PE/AN## PE/AN## PE/AN## PE7/AN7## SIGNAL DESCRIPTIONS AND OPERATING MODES MOTOROLA TECHNICAL DATA For More Information On This Product, -7
nc. PB7/A PB/A PB/A PB/A PB/A PB/A PB/A9 PB/A8 PC7/A7/D7 PC/A/D PC/A/D PC/A/D PC/A/D PC/A/D PC/A/D PC/A/D AS D D D D D D D7 D8 LE HC7 Q Q Q Q Q Q Q7 Q8 OE A A A A A A A9 A8 A7 A A A A A A A MC8HCA8.. Special Bootstrap Operating Mode R/W E Figure - Address/Data Demultiplexing ADDR/DATA DEMUX The bootstrap mode is considered a special operating mode as distinguished from the normal single-chip operating mode. This is a very versatile operating mode since there are essentially no limitations on the special purpose program that can be loaded into the internal RAM. The boot loader program is contained in the 9 byte bootstrap ROM. This ROM is enabled only if the MCU is reset in special bootstrap operating mode, and appears as internal memory space at locations $BF-$BFFF. The boot loader program will use the SCI to read a byte program into on-chip RAM at locations $-$FF. After the character for address $FF is received, control is automatically passed to that program at location $. The MC8HCA8 communicates through the SCI port. After reset in special bootstrap operating mode, the SCI is running at E clock/ (78 baud for E clock equal MHz). If the security feature was specified and the security bit is set, $FF is output by the SCI transmitter. The EEPROM is then erased. If erasure is unsuccessful, $FF is output again and erasure is attempted again. Upon successful erasure of the EE- PROM, all internal RAM is written over with $FF. The CONFIG register is then erased. The boot loader program now proceeds as though the part had not been in security mode. WE D7 D D D D D D D SIGNAL DESCRIPTIONS AND OPERATING MODES MC8HCA8-8 For More Information On This Product, TECHNICAL DATA
nc. If the part is not in security mode (or has completed the above erase sequence), a break character is output by the SCI transmitter. For normal use of the boot loader program, the user sends $FF to the SCI receiver at either E clock/ (78 baud for E clock = MHz) or E clock/ ( baud for E clock = MHz). NOTE This $FF is not echoed through the SCI transmitter. Now the user must download bytes of program data to be put into RAM starting at location $. These characters are echoed through the transmitter. When loading is complete, the program jumps to location $ and begins executing that code. If the SCI transmitter pin is to be used, an external pull-up resistor is required because port D pins are configured for wire-or operation. In special bootstrap operating mode the interrupt vectors are directed to RAM as shown in Table -. This allows the user to use interrupts by way of a jump table. For example: to use the SWI interrupt, a jump instruction would be placed in RAM at locations $F, $F, and $F. When an SWI is encountered, the vector (which is in the boot loader ROM program) will direct program control to location $F in RAM which in turn contains a JUMP instruction to the interrupt service routine. Table - Bootstrap Mode Interrupt Vectors Address Vector C SCI C7 SPI CA Pulse Accumulator Input Edge CD Pulse Accumulator Overflow D Timer Overflow D Timer Output Compare D Timer Output Compare D9 Timer Output Compare DC Timer Output Compare DF Timer Output Compare E Timer Input Capture E Timer Input Capture E8 Timer Input Capture EB Real Time Interrupt EE IRQ F XIRQ F SWI F7 Illegal Opcode FA COP Fail FD Clock Monitor BF Reset (Boot) SIGNAL DESCRIPTIONS AND OPERATING MODES MOTOROLA TECHNICAL DATA For More Information On This Product, -9
nc... Additional Boot Loader Program Options The user may transmit a $ (only at E clock/) as the first character rather than the normal $FF. This will cause the program to jump directly to location $, skipping the download. The user may tie the receiver to the transmitter (with an external pull-up resistor). This will cause the program to jump directly to the beginning of EEPROM ($B). Another way to cause the program to jump directly to EEPROM is to transmit either a break or $ as the first character rather than the normal $FF. Note that none of these options bypass the security check and so do not compromise those customers using security. Keep in mind that upon entry to the downloaded program at location $, some registers have been changed from their reset states. The SCI transmitter and receiver are enabled which cause port D pins and to be dedicated to SCI use. Also port D is configured for wired-or operation. It may be necessary for the user to write to the SCCR and SPCR registers to disable the SCI and/or port D wire-or operation... Special Test Operating Mode The test mode is a special operating mode intended primarily for factory testing. This mode is very similar to the expanded multiplexed operating mode. In special test operating mode, the reset and interrupt vectors are fetched from external memory locations $BFC $BFFF rather than $FFC $FFFF. There are no time limits for protection of the TMSK, OPTION, and INIT registers, so these registers may be written repeatedly. Also a special TEST register is enabled which allows several factory test functions to be invoked. The special test operating mode is not recommended for use by an end user because of the reduced system security; however, an end user may wish to come out of reset in special test operating mode. Then, after some initialization, the SMOD and MDA bits could be rewritten to select a normal operating mode to re-enable the protection features. SIGNAL DESCRIPTIONS AND OPERATING MODES MC8HCA8 - For More Information On This Product, TECHNICAL DATA
nc. ON-CHIP MEMORY This section describes the on-chip ROM, RAM, and EEPROM memories. The memory maps for each mode of operation are shown and the RAM and l/o mapping register (INIT) is described. The INIT register allows the on-chip RAM and the control registers to be moved to suit the needs of a particular application.. Memory Maps $ $ $B $E $FFFF Composite memory maps for each mode of operation are shown in Figure -. Memory locations are shown in the shaded areas and the contents of these shaded areas are shown to the right. These modes include single-chip, expanded multiplexed, special bootstrap, and special test. Single-chip operating modes do not generate external addresses. Refer to Table - for a full list of the registers. SINGLE CHIP EXT EXT EXT EXPANDED BOOTSTRAP EXT EXT EXT SPECIAL TEST FF F B B7FF BF BFFF E FFFF BYTES RAM -BYTE REGISTER BLOCK BYTES EEPROM BOOT ROM 8 KBYTES ROM BFC BFFF FFC FFFF SPECIAL MODES INTERRUPT VECTORS NORMAL MODES INTERRUPT VECTORS A8 MEM MAP Figure - Memory Maps ON-CHIP MEMORY MOTOROLA TECHNICAL DATA For More Information On This Product, -
nc. Table - Register and Control Bit Assignments (Sheet of ) Bit 7 Bit Bit Bit Bit Bit Bit Bit $ Bit 7 Bit PORTA I/O Port A $ Reserved $ STAF STAI CWOM HNDS OIN PLS EGA INVB PIOC Parallel I/O Control Register $ Bit 7 Bit PORTC I/O Port C $ Bit 7 Bit PORTB Output Port B $ Bit 7 Bit PORTCL Alternate Latched Port C $ Reserved $7 Bit 7 Bit DDRC Data Direction for Port C $8 Bit Bit PORTD I/O Port D $9 Bit Bit DDRD Data Direction for Port D $A Bit 7 Bit PORTE Input Port E $B FOC FOC FOC FOC FOC CFORC Compare Force Register $C OCM7 OCM OCM OCM OCM OCM OC Action Mask Register $D OCD7 OCD OCD OCD OCD OCD OC Action Data Register $E Bit Bit 8 TCNT Timer Counter Register $F Bit 7 Bit $ Bit Bit 8 TIC Input Capture Register $ Bit 7 Bit $ Bit Bit 8 TIC Input Capture Register $ Bit 7 Bit $ Bit Bit 8 TIC Input Capture Register $ Bit 7 Bit $ Bit Bit 8 TOC Output Compare Register $7 Bit 7 Bit $8 Bit Bit 8 TOC Output Compare Register $9 Bit 7 Bit $A Bit Bit 8 TOC Output Compare Register $B Bit 7 Bit $C Bit Bit 8 TOC Output Compare Register $D Bit 7 Bit $E Bit Bit 8 TCO Output Compare Register $F Bit 7 Bit ON-CHIP MEMORY MC8HCA8 - For More Information On This Product, TECHNICAL DATA
nc. Table - Register and Control Bit Assignments (Sheet of ) Bit 7 Bit Bit Bit Bit Bit Bit Bit $ OM OL OM OL OM OL OM OL TCTL Timer Control Register $ EDGB EDGA EDGB EDGA EDGB EDGA TCTL Timer Control Register $ OCI OCI OCI OCI OCI ICI ICI ICI TMSK Timer Interrupt Mask Register $ OCF OCF OCF OCF OCF ICF ICF ICF TFLG Timer Interrupt Flag Register $ TOI RTII PAOVI PAII PR PR TMSK Timer Interrupt Mask Register $ TOF RTIF PAOVF PAIF TFLG Timer Interrupt Flag Register $ DDRA7 PAEN PAMOD PEDGE RTR RTR PACTL Pulse Accumulator Control Register $7 Bit 7 Bit PACNT Pulse Accumulator Count Register $8 SPIE SPE DWOM MSTR CPOL CPHA SPR SPR SPCR SPI Control Register $9 SPIF WCOL MODF SPSR SPI Status Register $A Bit 7 Bit SPDR SPI Data Register $B TCLR SCP SCP RCKB SCR SCR SCR BAUD SCI Baud Rate Control $C R8 T8 M WAKE SCCR SCI Control Register $D TIE TCIE RIE ILIE TE RE RWU SBK SCCR SCI Control Register $E TRDE TC RDRF IDLE OR NF FE SCSR SCI Status Register $F Bit 7 Bit SCDR SCI Data (Read RDR, Write TDR) $ CCF SCAN MULT CD CC CB CA ADCTL A/D Control Register $ Bit 7 Bit ADR A/D Result Register $ Bit 7 Bit ADR A/D Result Register $ Bit 7 Bit ADR A/D Result Register $ Bit 7 Bit ADR A/D Result Register $ thru Reserved $8 $9 ADPU CSEL IRQE DLY CME CR CR OPTION System Configuration Options $A Bit 7 Bit COPRST Arm/Reset COP Timer Circuitry $B ODD EVEN BYTE ROW ERASE EELAT EEPGM PPROG EEPROM Program Control Register $C RBOOT SMOD MDA IRV PSEL PSEL PSEL PSEL HPRIO Highest Priority I-Bit Int and Misc $D RAM RAM RAM RAM REG REG REG REG INIT RAM and I/O Mapping Register $E TILOP OCCR CBYP DISR FCM FCOP TCON TEST Factory TEST Control Register $F NOSEC NOCOP ROMON EEON CONFIG COP, ROM, and EEPROM Enables ON-CHIP MEMORY MOTOROLA TECHNICAL DATA For More Information On This Product, -
nc. In expanded multiplexed operating modes, memory locations are basically the same as the single- chip operating modes; however, the locations between the shaded areas (designated EXT) are for externally addressed memory and l/o. If an external memory or l/o device is located to overlap an enabled internal resource, the internal resource will take priority. For reads of such an address the data (if any) driving the port C data inputs is ignored and will not result in any harmful conflict with the internal read. For writes to such an address data is driven out of the port C data pins as well as to the internal location. No external devices should drive port C during write accesses to internal locations; however, there is normally no conflict since the external address decode and/ or data direction control should incorporate the R/W signal in their development. The R/W, AS, address, and write data signals are valid for all accesses including accesses to internal memory and registers. The special bootstrap operating mode memory locations are similar to the single-chip operating mode memory locations except that a bootstrap program at memory locations $BF through $BFFF is enabled. The reset and interrupt vectors are addressed at $BFC $BFFF while in the special bootstrap operating mode. These vector addresses are within the 9 byte memory used for the bootstrap program. The special test operating mode memory map is the same as the expanded multiplexed operating mode memory map except that the reset and interrupt vectors are located at external memory locations $BFC $BFFF.. RAM and I/O Mapping Register (INIT) There are internal registers which are used to control the operation of the MCU. These registers can be relocated on K boundaries within the memory space, using the INIT register. Refer to Table - for a complete list of the registers. The registers and control bits are explained throughout this document. The INIT register is a special-purpose 8-bit register which may be used during initialization to change the default locations of RAM and control registers within the MCU memory map. It may be written to only once within the initial E clock cycles after a reset and thereafter becomes a read-only register. 7 $D RAM RAM RAM RAM REG REG REG REG INIT RESET The default starting address for internal RAM is $ and the default starting address for the control registers is $ (the INIT register is set to $ at reset). The upper four bits of the INIT register specify the starting address for the byte RAM and the lower four bits of INIT specify the starting address for the control registers. These four bits are matched to the upper four bits of the -bit address. Throughout this document, the control register addresses will be displayed with the high-order digit shown as a bold to indicate that the register block may be relocated to some K memory page other than its default position of $-$F. ON-CHIP MEMORY MC8HCA8 - For More Information On This Product, TECHNICAL DATA
nc. Note that if the RAM is relocated to either $E or $F, which is in conflict with the internal ROM, (no conflict if the ROMON bit in the configuration register is zero), RAM will take priority and the conflicting ROM will become inaccessible. Also, if the control registers are relocated so that they conflict with the RAM and/or ROM, then the control registers take priority and the RAM and/or ROM at those locations become inaccessible. No harmful conflicts result, the lower priority resources simply become inaccessible. Similarly, if an internal resource conflicts with an external device no harmful conflict results. Data from the external device will not be applied to the internal data bus and cannot interfere with the internal read. Note that there are unused register locations in the byte control register block. Reads of these unused registers will return data from the undriven internal data bus and not from another resource that happens to be located at the same address.. ROM The internal 8K ROM occupies the highest 8K of the memory map ($E $FFFF). This ROM is disabled when the ROMON bit in the CONFIG register is clear. The ROMON bit is implemented with an EEPROM cell and is programmed using the same procedures for programming the on-chip EEPROM. For further information refer to.. System Configuration Register (CONFIG). In the single-chip operating mode, internal ROM is enabled regardless of the state of the ROMON bit. There is also a 9 byte mask programmed boot ROM in the MC8HCA8. This bootstrap program ROM controls the operation of the special bootstrap operating mode and is only enabled following reset in the special bootstrap operating mode. For more information refer to.. Special Bootstrap Operating Mode.. RAM The byte internal RAM may be relocated during initialization by writing to the INIT register. The reset default position is $ through $FF. This RAM is implemented with static cells and retains its contents during the WAIT and STOP modes. The contents of the -byte RAM can also be retained by supplying a low current backup power source to the MODB/V STBY pin. When using a standby power source, V DD may be removed; however, RESET must go low before V DD is removed and remain low until V DD has been restored.. EEPROM The bytes of EEPROM are located at $B through $B7FF and have the same read cycle time as the internal ROM. The write (or programming) mechanism for the EEPROM is controlled by the PPROG register. The EEPROM is disabled when the EEON bit in the CONFIG register is zero. The EEON bit is implemented with an EE- PROM cell. ON-CHIP MEMORY MOTOROLA TECHNICAL DATA For More Information On This Product, -
nc. The erased state of an EEPROM byte is $FF. Programming changes ones to zeros. If any bit in a location needs to be changed from a zero to a one, the byte must be erased in a separate operation before it is reprogrammed. If a new data byte has no ones in bit positions which were already programmed to zero, it is acceptable to program the new data without erasing the EEPROM byte first. For example, programming $ to a location which was already $ would change the location to $. Programming and erasure of the EEPROM relies on an internal high-voltage charge pump. At E clock frequencies below MHz the efficiency of this charge pump decreases which increases the time required to program or erase a location. The recommended program and erase time is milliseconds when the E clock is MHz and should be increased to as much as milliseconds when E is between MHz and MHz. When the E clock is below MHz, the clock source for the charge pump should be switched from the system clock to an on-chip R-C oscillator clock. This is done by setting the CSEL bit in the OPTION register. A millisecond period should be allowed after setting the CSEL bit to allow the charge pump to stabilize. Note that the CSEL bit also controls a clock to the analog-to-digital converter subsystem... EEPROM Programming Control Register (PPROG) This 8-bit register is used to control programming and erasure of the -byte EE- PROM. Reset clears this register so the EEPROM is configured for normal reads. 7 $B ODD EVEN BYTE ROW ERASE EELAT EEPGM PPROG RESET ODD Program Odd Rows (TEST) EVEN Program Even Rows (TEST) Bit Not implemented. This bit always reads zero. BYTE Byte Erase Select This bit overrides the ROW bit. = Row or Bulk Erase = Erase Only One Byte ROW Row Erase Select If the BYTE bit is, ROW has no meaning. = Bulk Erase = Row Erase ERASE Erase Mode Select = Normal Read or Program = Erase Mode ON-CHIP MEMORY MC8HCA8 - For More Information On This Product, TECHNICAL DATA
nc. EELAT EEPROM Latch Control = EEPROM Address and Data Configured for Read Mode = EEPROM Address and Data Configured for Programming/Erasing EEPGM EEPROM Programming Voltage Enable = Programming Voltage Switched Off = Programming Voltage Turned On If an attempt is made to set both the EELAT and EEPGM bits in the same write cycle, neither will be set. If a write to an EEPROM address is performed while the EEPGM bit is set, the write is ignored and the programming operation currently in progress is not disturbed. These two safeguards were included to prevent accidental EEPROM changes in cases of program runaway. Mask sets A8P, A9N, and date codes before 8xx did not have these safeguards... Programming/Erasing Internal EEPROM The EEPROM programming and erasure process is controlled by the PPROG register. The following paragraphs describe the various operations performed on the EE- PROM and include example program segments to demonstrate programming and erase operations. These program segments are intended to be simple straightforward examples of the sequences needed for basic program and erase operations. There are no special restrictions on the address modes used and bit manipulation instructions may be used. Other MCU operations can continue to be performed during EEPROM programming and erasure provided these operations do not include reads of data from EEPROM (the EEPROM is disconnected from the read data bus during EEPROM program and erase operations). The subroutine DLY used in these program segments is not shown but can be any set of instructions which takes ten milliseconds.... Read For the read operation the EELAT bit in the PPROG register must be clear. When this bit is cleared, the remaining bits in the PPROG register have no meaning or effect, and the EEPROM may be read as if it were a normal ROM.... Programming During EEPROM programming, the ROW and BYTE bits are not used. If the E clock frequency is MHz or less, the CSEL bit in the OPTION register must be set. Recall that in this EEPROM, zeros must be erased by a separate erase operation before programming. The following program segment demonstrates how to program an EE- PROM byte. ON-CHIP MEMORY MOTOROLA TECHNICAL DATA For More Information On This Product, -7
nc.... * On entry, A = data to be programmed and X = EEPROM address PROG LDAB #$ STAB $B Set EELAT Bit (EEPGM = ) STAA,X Store Data to EEPROM Address LDAB #$ STAB $B Set EEPGM Bit (EELAT = ) JSR DLY Delay ms CLR $B Turn Off High Voltage and Set to READ Mode Bulk Erase The following program segment demonstrates how to bulk erase the -byte EE- PROM. The CONFIG register is not affected in this example. BULKE LDAB #$ STAB $B Set to Bulk Erase Mode STAB $B Write any Data to any EEPROM Address LDAB #$7 STAB $B Turn On Programming Voltage JSR DLY Delay ms CLR $B Turn Off High Voltage and Set to READ Mode... Row Erase The following program segment demonstrates the row erase function. A row is sixteen bytes ($B-$BF, $B-$BF... $B7F-$B7FF). This type of erase operation saves time compared to byte erase when large sections of EEPROM are to be erased. ON-CHIP MEMORY MC8HCA8-8 For More Information On This Product, TECHNICAL DATA
nc. *On entry X = any address in the row to be erased ROWE LDAB #$E STAB $B Set to Row Erase Mode STAB,X Write any Data to any Address in Row LDAB #$F STAB $B Turn on High Voltage JSR DLY Delay ms CLR $B Turn Off High Voltage and Set to Read Mode... Byte Erase The following program segment shows the byte erase function. *On entry, X = address of byte to be erased BYTEE LDAB #$ STAB $B Set to Byte Erase Mode STAB,X Write any Data to the Address to Erase LDAB #$7 STAB $B Turn on High Voltage JSR DLY Delay ms CLR $B Turn off High Voltage and Set to Read Mode.. System Configuration Register (CONFIG) The MC8HCA8 can be configured to specific system requirements through the use of hardwired options such as the mode select pins, semi-permanent EEPROM control bit specifications (CONFIG register), or by use of control registers. The configuration control register (CONFIG) is implemented in EEPROM cells and controls the presence ON-CHIP MEMORY MOTOROLA TECHNICAL DATA For More Information On This Product, -9