High voltage resonant controller Features High voltage rail up to 600 V dv/dt immunity ±50 V/ns in full temperature range Driver current capability: 250 ma source 450 ma sink Switching times 80/40 ns rise/fall with 1 nf load CMOS shutdown input Undervoltage lockout Soft-start frequency shifting timing Datasheet - production data Sense op amp for closed loop control or protection features High accuracy current controlled oscillator Integrated bootstrap diode Clamping on Vs Available in DIP16 and SO16 packages Description Figure 1. Block diagram The L6598 device is manufactured with the BCD offline technology, able to ensure voltage ratings up to 600 V, making it perfectly suited for AC/DC adapters and wherever a resonant topology can be beneficial. The device is intended to drive two power MOSFETs, in the classical half bridge topology. A dedicated timing section allows the designer to set soft-start time, soft-start and minimum frequency. An error amplifier, together with the two enable inputs, are made available. In addition, the integrated bootstrap diode and the Zener clamping on low voltage supply, reduces to a minimum the external parts needed in the applications. November 2013 DocID6554 Rev 8 1/23 This is information on a product in full production. www.st.com
Contents L6598 Contents 1 Maximum ratings............................................ 3 2 Electrical characteristics..................................... 4 3 Pin connections............................................. 6 4 Timing diagrams............................................ 7 5 Block diagram description.................................... 9 5.1 High/low side driving section................................... 9 5.2 Timing and oscillator section................................... 9 5.3 Bootstrap section........................................... 13 5.4 Op amp section............................................ 14 5.5 Comparators............................................... 15 6 Package information........................................ 19 7 Ordering codes............................................ 22 8 Revision history........................................... 23 2/23 DocID6554 Rev 8
Maximum ratings 1 Maximum ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit IS Supply current at V (1) cl 25 ma VLVG Low side output 14.6 V VOUT High side reference -1 to VBOOT -18 V VHVG High side output -1 to VBOOT V VBOOT Floating supply voltage 618 V dvboot/dt VBOOT pin slew rate (repetitive) ±50 V/ns dvout/dt OUT pin slew rate (repetitive) ±50 V/ns Vir Forced input voltage (pins Rfmin, Rfstart) -0.3 to 5 V Vic Forced input voltage (pins Css, Cf) -0.3 to 5 V VEN1, VEN2 Enable input voltage -0.3 to 5 V IEN1, IEN2 Enable input current ±3 ma Vopc Sense op amp common mode range -0.3 to 5 V Vopd Sense op amp differential mode range -5 to 5 V Vopo Sense op amp output voltage (forced) 4.6 V Tstg Storage temperature -40 to +150 C Tj Junction temperature -40 to +150 C Tamb Ambient temperature -40 to +125 C 1. The device is provided of an internal clamping Zener between GND and the Vs pin, It must not be supplied by a low impedance voltage source. Note: ESD immunity for pins 14, 15 and 16 is guaranteed up to 900 (human body model). Table 2. Thermal data Symbol Parameter SO16N DIP16 Unit R thja Thermal resistance junction to ambient 120 80 C/W Table 3. Recommended operating conditions Symbol Parameter Value Unit V S Supply voltage 10 to Vcl V V (1) out High side reference -1 to Vboot - Vcl V V (1) boot Floating supply rail 500 V fmax Maximum switching frequency 400 khz 1. If the condition V boot - V out < 18 is guaranteed, V out can range from -3 to 580 V. DocID6554 Rev 8 3/23 23
Electrical characteristics L6598 2 Electrical characteristics V S = 12 V; V BOOT - V OUT = 12 V; T A = 25 C Table 4. Electrical characteristics Symbol Pin Parameter Test condition Min. Typ. Max. Unit Supply voltage V suvp V S turn on threshold 10 10.7 11.4 V V suvn V S turn off threshold 7.3 8 8.7 V Supply voltage under V suvh 2.7 V voltage hysteresis 12 V cl Supply voltage clamping 14.6 15.6 16.6 V I su Start up current V S < V suvn 250 µa Quiescent current, fout = I q V 60 khz, no load S > V suvp 2 3 ma High voltage section I bootleak 16 BOOT pin leakage current V BOOT = 580 V 5 µa I outleak 14 OUT pin leakage current V OUT = 562 V 5 µa R DSon 16 High/low side drivers I hvgso 15 I hvgsi I lvgso 11 I lvgsi Bootstrap driver onresistance High side driver source current High side driver sink current Low side driver source current Low side driver sink current 100 150 300 V HVG - V OUT = 0 170 250 ma V HVG - V BOOT = 0 300 450 ma V LVG - GND = 0 170 250 ma V LVG - V S = 0 300 450 ma t rise Low/high side output rise 15,11 time C load = 1 nf 80 120 ns t fall C load = 1 nf 40 80 ns Oscillator DC f min f start 14 Output duty cycle 48 50 52 % Minimum output oscillation frequency Soft-start output oscillation frequency C f = 470 pf; R fmin = 50 k C f = 470 pf; R fmin = 50 k; R fstart = 47k 58.2 60 61.8 khz 114 120 126 khz 4/23 DocID6554 Rev 8
Electrical characteristics V ref 2, 4 Voltage to current converters threshold 1.9 2 2.1 V t d 14 Deadtime between low and high side conduction 0.2 0.27 0.35 µs IVref 2, 4 Reference current 120 A Timing section k ss 1 Soft-start timing constant C ss = 330 nf 0.115 0.15 0.185 s/µf Sense op amp l IB Input bias current 0.1 µa 6, 7 V io Input offset voltage -10 10 mv R out Output resistance 200 300? I out- 5 Source output current V out = 4.5 V 1 ma I out+ Sink output current V out = 0.2 V 1 ma V ic 6,7 GBW Op amp input common mode range -0.2 3 V Sense op amp gain band width product (1) 0.5 1 MHz Gdc DC open loop gain 60 80 db Comparators Table 4. Electrical characteristics (continued) Symbol Pin Parameter Test condition Min. Typ. Max. Unit Vthe1 8 Vthe2 9 Enabling comparator threshold Enabling comparator threshold 0.56 0.6 0.64 V 1.05 1.2 1.35 V tpulse 8,9 Minimum pulse length 200 ns 1. Guaranteed by design. DocID6554 Rev 8 5/23 23
Pin connections L6598 3 Pin connections Figure 2. Pin connections Table 5. Pin description Pin no. Name Function 1 CSS Soft-start timing capacitor 2 R fstart Soft-start frequency setting - low impedance voltage source -see also C f 3 C f Oscillator frequency setting - see also R fmin, R fstart 4 R fmin Minimum oscillation frequency setting - low impedance voltage source - see also C f 5 O Pout Sense op amp output - low impedance 6 O Pon- Sense op amp inverting input -high impedance 7 O Pon+ Sense op amp non inverting input - high impedance 8 EN1 Half bridge latched enable 9 EN2 Half bridge unlatched enable 10 GND Ground 11 LVG Low side driver output 12 V s Supply voltage with internal Zener clamp 13 N.C. Not connected 14 OUT High side driver reference 15 HVG High side driver output 16 V boot Bootstrapped supply voltage 6/23 DocID6554 Rev 8
Timing diagrams 4 Timing diagrams Figure 3. EN2 timing diagram Figure 4. EN1 timing diagram DocID6554 Rev 8 7/23 23
Timing diagrams L6598 Figure 5. Oscillator/output timing diagram 8/23 DocID6554 Rev 8
Block diagram description 5 Block diagram description 5.1 High/low side driving section A high and low side driving section provide the proper driving to the external power MOS or IGBT. A high sink/source driving current (450/250 ma typ.) ensure fast switching times also when size for power MOS are used. The internal logic ensures a minimum deadtime to avoid cross conduction of the power devices. 5.2 Timing and oscillator section The device is provided of a soft-start function. It consists in a period of time, T SS, in which the switching frequency shifts from fstart to fmin. This feature is explained in the following description (refer to Figure 6 and Figure 7). Figure 6. Soft-start and frequency shifting block During the soft-start time the current I SS charges the capacitor C SS, generating a voltage ramp which is delivered to a transconductance amplifier, as shown in Figure 6. Thus this voltage signal is converted in a growing current which is subtracted to Ifstart. Therefore the current which drives the oscillator to set the frequency during the soft-start is equal to: Equation 1 g m I ss I osc = I fmin + I fstart g m V Css t = I + fmin I fstart ------------- C ss Equation 2 V REF V REF where I fmin = ------------- I fstart = ---------------, V REF = 2V R fmin R fstart DocID6554 Rev 8 9/23 23
Block diagram description L6598 At the startup (t = 0) the oscillator frequency is set by: Equation 3 1 1 I OSC 0= I fmin + I fstart = V REF ------------- + --------------- R fmin R fstart At the end of the soft-start (t = T SS ) the second term of eq.1 decreases to zero and the switching frequency is set only by Imin (i.e. R fmin ): Equation 4 V REF I OSC T SS = I fmin = ------------- R fmin Since the second term of Equation 1 is equal to zero, we have: Equation 5 I fstart g m I ss C ss I fstart ------------- T C SS = 0 T SS = ----------------------- ss g m I ss Note that there is not a fixed threshold of the voltage across C SS in which the soft-start finishes (i.e. the end of the frequency shifting), and TSS depends on C SS, Ifstart, g m, and I SS (Equation 5). Making T SS independent of Ifstart, the ISS current has been designed to be a fraction of I fstart, so: Equation 6 I SS I fstart C ss I fstart = ------------- T K SS = ------------------------- T g m I fstart K SS = C ss ----------- T g m K SS k SS C SS In this way the soft-start time depends only on the capacitor C SS. The typical value of the k SS constant (Soft-start timing constant) is 0.15 s/f. The current I osc is fed to the oscillator as shown in Figure 7. It is twice mirrored (x4 and x8) generating the triangular wave on the oscillator capacitor C f. Referring to the internal structure of the oscillator (Figure 7), a good relationship to compute an approximate value of the oscillator frequency in normal operation is: Equation 7 1.41 f min = ------------------- R fmin C f 10/23 DocID6554 Rev 8
Block diagram description The degree of approximation depends on the frequency value, but it remains very good in the range from 30 khz to 100 khz (Figure 8 to Figure 12). Figure 7. Oscillator block DocID6554 Rev 8 11/23 23
Block diagram description L6598 Figure 8. Typ. f min vs. R fmin at Cf = 470 pf Figure 9. Typ. (f start -f min ) vs. R fstar at C f = 470 pf Figure 10. Typ. (f start -f min ) vs. R fstar at C f = 470 pf Figure 11. f min at different R f vs C f 12/23 DocID6554 Rev 8
Block diagram description Figure 12. Typ. (f start -f min ) vs. R fstar at C f = 470 pf 5.3 Bootstrap section The supply of the high voltage section is obtained by means of a bootstrap circuitry. This solution normally requires a high voltage fast recovery diode for charging the bootstrap capacitor (Figure 13 - part a). In the device a patented integrated structure replaces this external diode. It is released by means of a high voltage DMOS, driven synchronously with the low side driver (LVG), with in series a diode, as shown in Figure 13 - part b. Figure 13. Bootstrap driver To drive the synchronized DMOS it is necessary a voltage higher than the supply voltage Vs. This voltage is obtained by means of an internal charge pump (Figure 13 - part b). The diode connected in series to the DMOS has been added to avoid undesirable turn on of it. The introduction of the diode prevents any current can flow from the Vboot pin to the VS one in case that the supply is quickly turned off when the internal capacitor of the pump is not fully discharged. The bootstrap driver introduces a voltage drop during the recharging of the capacitor Cboot (i.e. when the low side driver is on), which increases with the frequency and with the size of the external power MOS. It is the sum of the drop across the R DSON and of the diode DocID6554 Rev 8 13/23 23
Block diagram description L6598 threshold voltage. At low frequency this drop is very small and can be neglected. Anyway increasing the frequency it must be taken in to account. In fact the drop, reducing the amplitude of the driving signal, can significantly increase the R DSON of the external power MOS (and so the dissipation). To be considered that in resonant power supplies the current which flows in the power MOS decreases increasing the switching frequency and generally the increases of R DSON is not a problem because power dissipation is negligible. Equation 8 is useful to compute the drop on the bootstrap driver: Equation 8 V drop = I charge R dson + V diode V drop = Q g ------------------ R dson + V diode T charge where Qg is the gate charge of the external power MOS, Rdson is the on-resistance of the bootstrap DMOS, and Tcharge is the time in which the bootstrap driver remains on (about the semi-period of the switching frequency minus the deadtime). The typical resistance value of the bootstrap DMOS is 150. For example using a power MOS with a total gate charge of 30 nc the drop on the bootstrap driver is about 3 V, at a switching frequency of 200 khz. In fact: Equation 9 V drop 30nC = ------------------ 150 + 0.6V 2.6V 2.23s To summaries, if a significant drop on the bootstrap driver (at high switching frequency when large power MOS are used) represents a problem, an external diode can be used, avoiding the drop on the R DSON of the DMOS. 5.4 Op amp section The integrated op amp is designed to offer low output impedance, wide band, high input impedance and wide common mode range. It can be readily used to implement protection features or a closed loop control. For this purpose the op amp output can be properly connected to R fmin pin to adjust the oscillation frequency. 14/23 DocID6554 Rev 8
Block diagram description 5.5 Comparators Two CMOS comparators are available to perform protection schemes. Short pulses ( 200 ns) on comparators input are recognized. The EN1 input (active high), has a threshold of 0.6 V (typical value) forces the device in a latched shut down state (e.g. LVG low, HVG low, oscillator stopped), as in the under voltage conditions. Normal operating conditions are resumed after a power-off power-on sequence. The EN2 input (active high), with a threshold of 1.2 V (typical value) restarts a soft-start sequence (see timing diagrams in Figure 3, Figure 4, and Figure 5). In addition the EN2 comparator, when activated, removes a latched shutdown caused by EN1. Figure 14. Switching time waveform definitions Figure 15. Deadtime and duty cycle waveform definition DocID6554 Rev 8 15/23 23
Block diagram description L6598 Figure 16. Typ. fmin vs. temperature Figure 17. Startup current vs. temperature Figure 18. Typ. fstart vs. temperature Figure 19. Quiescent current vs. temperature 16/23 DocID6554 Rev 8
Block diagram description Figure 20. Vs thresholds and clamp vs. temp. Figure 21. HVG source and sink current vs. temperature Figure 22. LVG source and sink current vs. temperature Figure 23. Soft-start timing constant vs. temperature DocID6554 Rev 8 17/23 23
Block diagram description L6598 Figure 24. Wide range AC/DC adapter application 18/23 DocID6554 Rev 8
Package information 6 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Figure 25. Plastic DIP16 (0.25) package outline Table 6. Plastic DIP16 (0.25) package mechanical data Dimensions Symbol mm inch Min. Typ Max. Min. Typ. Max. a1 0.51 0.020 B 0.77 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L 3.3 0.130 Z 1.27 0.050 DocID6554 Rev 8 19/23 23
Package information L6598 Figure 26. SO16 package outline Symbol Table 7. SO16 package mechanical data mm Dimensions inch Min. Typ Max. Min. Typ. Max. A 1.75 0.068 a 1 0.1 0.25 0.004 0.010 a2 1.64 0.063 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45 (typ.) D 9.8 10 0.385 0.393 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M 0.62 0.024 S 8 (max.) 20/23 DocID6554 Rev 8
Ordering codes 7 Ordering codes Table 8. Ordering information Order codes Package Packing L6598 DIP16 Tube L6598D L6598D013TR SO16N Tube Tape and reel DocID6554 Rev 8 21/23 23
Revision history L6598 8 Revision history Table 9. Document revision history Date Revision Changes 21-Jun-2004 5 Changed the impagination following the new release of corporate technical publication design guide. Done a few of corrections in the text. 09-Sep-2004 6 02-Oct-2009 7 Updated Table 4 on page 4 18-Nov-2013 8 Added ordering number for the tape and reel version, updated Table 4 on page 4 Added cross-reference in Section 5. Updated Section 6: Package information (reformatted - added title of Figure 25 and Table 6, Figure 26 and Table 7 and reversed order of figures and tables, minor modifications). Updated Table 8 (replaced L6598D016TR device by L6598D013TR device). Minor corrections throughout document. 22/23 DocID6554 Rev 8
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