Getting Started with PCB Design Studio (Concept HDL Version) Product Version 14.2 January 2002

(Concept HDL Version) Product Version 14.2 January 2002

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Contents 1 Introduction......................................................... 5 Overview.............................................................. 5 About Concept HDL................................................... 5 A note on this document................................................ 6 2......................................... 7 Contents.............................................................. 7 Cadence PCB Design Studio with Concept HDL................................ 8 Setting Up a Project with Project Manager.................................. 8 Allegro for Board Layout................................................. 17 Starting Allegro...................................................... 17 Allegro Design Flow.................................................. 18 Importing Concept HDL Schematic Data into Allegro........................ 19 Exporting Allegro Data (Backannotating) to Concept HDL..................... 20 Exporting Allegro Data for SPECCTRA Routing............................ 20 SPECCTRA for Automatic Routing......................................... 20 Starting SPECCTRA................................................. 21 Exporting SPECCTRA Routing Data (Backannotating) to Allegro............... 21 Generating Manufacturing Output With Allegro................................ 21 3 PCB Design Studio Options..................................... 23 CheckPlus for Checking Your Design....................................... 24 Variant Editor for Creating Versions......................................... 26 signal explorer for Inter-connect Analysis.................................... 28 January 2002 3 Product Version 14.2

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1 Introduction Overview PCB design studio is a complete printed circuit board (PCB) design solution that integrates PCB tools for creating projects, managing libraries, capturing schematics, packaging, physical placement and routing, and producing manufacturing output. This manual provides you with the information you need to get up and running with Cadence Design System s schematic capture tool Concept HDL and premier layout tool, Allegro. The high-level project flow to create a PCB is as follows: 1. Set up and manage the project using Project Manager. 2. Capture the schematic using Concept HDL. 3. Import the schematic data from Concept HDL to Allegro. 4. Lay out the design in Allegro. 5. Route the design using SPECCTRA. 6. Backannotate to Concept HDL. 7. Create the manufacturing output using Allegro. About Concept HDL Concept HDL is a design environment that supports behavioral and structural design descriptions that are designed using text and graphics. Concept HDL comes with a large library of schematic symbols and EDIF schematic and netlist interfaces and supports EDIF 3 0 0 and VHDL models. Concept HDL accommodates teams that work on complex design projects by supporting a top-down approach to design that incorporates hierarchical stack editing functions for quick architectural design. January 2002 5 Product Version 14.2

Introduction Concept HDL lets a design architect create a top-level schematic and refine underlying areas while team members work on their respective sub-designs. One engineer can work on a schematic if he or she references the next engineer s schematic externally through a hierarchical reference (hierarchical block). A note on this document This Getting Started guide provides a high-level description of the front-to-back (schematicto-design) flow. It does not include details on the types of files generated during the transfer of logic between Concept HDL and Allegro, nor does it cover any issues related to property translation between the tools. For this type of information, please see the documentation associated with Concept HDL, Allegro, and SPECCTRA. January 2002 6 Product Version 14.2

2 Contents Cadence PCB Design Studio with Concept HDL on page 8 Setting Up a Project with Project Manager on page 8 Allegro for Board Layout on page 17 Starting Allegro on page 17 Allegro Design Flow on page 18 Importing Concept HDL Schematic Data into Allegro on page 19 Exporting Allegro Data (Backannotating) to Concept HDL on page 20 Exporting Allegro Data for SPECCTRA Routing on page 20 SPECCTRA for Automatic Routing on page 20 Starting SPECCTRA on page 21 Exporting SPECCTRA Routing Data (Backannotating) to Allegro on page 21 Generating Manufacturing Output With Allegro on page 21 Each PCB design studio tool has extensive online information that is available from the tool s graphical interface. To access this information, choose a topic from the Help menu or click on a Help button from any dialog box. In addition to online Help, information for some tools may also be provided in the form of printable online books (user guides) and tutorials. January 2002 7 Product Version 14.2

Cadence PCB Design Studio with Concept HDL The following illustration shows the tool flow that you use to create a PCB with PCB design studio with Concept HDL. This flow includes integration of the PSpice Analog/Digital Simulator and SPECCTRAQuest signal explorer. PSpice simulates analog-only circuits. PSpice formulates the file set into meaningful graphical plots, which you can mark for display directly from your schematic page using markers. For more information about PSpice, access the online information from the PSpice Help menu. SPECCTRAQuest signal explorer (SigXP) is a tool that you can purchase in addition to PCB design studio with Concept HDL to analyze signal integrity on pre-route and post-route nets. For information about SigXP, access the online information from the SigXP Help menu. Project Manager Engineering Input Concept Allegro PCB PSpice A/D SPECCTRAQuest signal explorer SPECCTRA Setting Up a Project with Project Manager The logical directory structure for designs is Lib:Cell:View:File. Each library, cell, and view is a physical directory that is organized as shown in the following table: Directory Lib Description A directory of cells. January 2002 8 Product Version 14.2

Cell View A design directory that contains all of the data for the design. The directory is organized into views. For example, design cpu can have the views schematic, symbol, chips, package and physical. The configurations of a design are also stored as views in the cell directory. A directory that contains all of the data of a particular unit of a design. For example, all the files for a schematic are in the sch_n view; where n can be the version number of the design. All the information for a symbol representation of the design is in the sym_n view. The packaged design data is in the package view. Configurations, including the default cfg_package, cfg_verilog, and cfg_vhdl configurations, are also views in a cell. The following shows a typical Lib:Cell:View directory structure: To set up a project and directory structure with Project Manager, perform the following steps: 1. Invoke the Project Manager from the Start Cadence menu in the Windows task bar. or January 2002 9 Product Version 14.2

Entering projmgr at a UNIX operating system prompt. Note: If you have a license for only PCB design studio with Concept HDL, Project Manager starts. If you have more than one licensed product, the Project Manager Product Choices dialog box (not pictured) appears and displays a list of the products for which you have licenses. Select PCB design studio and click OK. The Project Manager window appears. 2. Click on the New button in the Project Manager window to start a new project. The New Project wizard starts up and the first dialog box appears. January 2002 10 Product Version 14.2

3. Enter the name of your new project in the Project Name field of the Project Name and Location dialog box. You can accept the default location or change it. Click Next to continue. 4. Select the libraries that you need for the project. Click Next to continue. January 2002 11 Product Version 14.2

5. Enter the name of the cell that you want to use as the top-level drawing in the Design Name field. You can accept the default library or choose another. Click Next to continue. 6. Project Manager displays a summary of your choices to create a new project in Concept HDL. If these choices are correct, click Finish; otherwise click Previous and specify January 2002 12 Product Version 14.2

some of your choices again. When you click Finish, Project Manager displays a new graphic flow. 7. You can click on the following buttons in Project Manager: Setup lets you modify project settings. Design Entry invokes Concept HDL. Design Sync lets you import and export design data. Layout invokes Allegro. Floor Planner invokes SPECCTRAQuest (if you have a SPECCTRAQuest license). January 2002 13 Product Version 14.2

Starting Concept HDL Start Concept HDL from the Project Manager in one of the following ways: Choose Tools Concept Click on the Design Entry button. To start Concept HDL from the windows task bar, choose Start Programs Cadence Concept HDL. Concept HDL Design Flow The schematic layout design process consists of the following general flow. You can tailor the tasks in the flow to your specific design needs. Refer to the online information in Concept HDL for more information about the operations in each step. Step 1 Develop libraries. Create symbols. Create schematic-to-allegro mapping (for example, pin numbers to package types). January 2002 14 Product Version 14.2

Step 2 Create a new project. Step 3 Decide on a flat or hierarchical design style. Step 4 If you are creating a hierarchical design, create a symbol. Step 5 Create another schematic module. Step 6 Assign constraints to your design. Step 7 Assign reference designators. Step 8 Create the physical netlist. Step 9 Backannotate the schematic. Step 10 Import the netlist into Allegro. Invoke Project Manager to set up the project. Select the libraries. Select the top-level design name. Add a page border to empty page. Add components from the library. Use the physical part table browser to specify the properties of each logical symbol. Add connectivity to your design. Add the correct PORT symbol (Inport, Output, IOport) for each signal that interfaces with another module. Add more pages and repeat step 3. Use the GenView utility to create a symbol that represents the schematic. Customize the symbol that comes out of the automated utility. If you are designing hierarchically, repeat Step 3 to create another design. Add the symbol that represents the previously created design. Using the Attribute form, attach properties to the components, pins and signals. You use these properties to control the board layout process. You can also pass this data into the High Speed SPECCTRAQuest environment. You can assign reference designators in Concept, or you can let Packager-XL (the physical netlister) assign designators. Packager-XL does not change any reference designators that you assign in Concept. Execute Packager-XL to create the netlist for Allegro. Provide the pin numbers and reference designators as properties on the schematic. The Design Sync option of the Project Manager creates the netlist and creates or updates the Allegro board. January 2002 15 Product Version 14.2

Step 11 Layout the board with Allegro. Step 12 Export the logic to Concept. See Allegro Design Flow on page 18. Backannotate the schematic with your Allegro changes. Exporting Concept HDL Data for Allegro Board Layout To export Concept HDL schematic data for Allegro processing, in Concept HDL choose File Export Physical. You can also click Design Sync in the Project Manager and select Export Physical from the menu. The Export Physical dialog box appears. For information about this dialog box, click on Help. You must specify an existing board (which may be blank) to which Concept exports the schematic data. You can create a different board file from the composite data or overwrite the existing board file. Using Librarian Utilities Librarian is a collection of utilities that output data for Concept schematics and Allegro designs. You can use the Librarian utilities to create logical part data, construct physical packages, and manage library data for modification and release. For more information about these utilities, access the online information from the Help menu of each tool. The following tools are available as part of the Librarian: Part Developer Creates, edits, and tests component data. It lets you edit the schematic symbol, physical pin data, and part number information from a single environment. You can start Part Developer from Project Manager by choosing Tools Part Developer. January 2002 16 Product Version 14.2

Library Explorer Manages a build area for creating new components and updating existing components before promoting them to a reference area. Library Explorer also ensures correct part generation through comprehensive error checking routines. You can start Library Explorer from Project Manager by choosing Tools Library Explorer. Allegro Librarian You can also choose Start Programs Cadence PCB Systems Library Explorer. Enables you to generate physical packages, board outlines, and detailed dimension drawings. Allegro Librarian also lets you establish design constraints, drawing details such as cross sections, and other manufacturing output parameters. To start the Allegro Librarian, enter allegro_librarian at the MS-DOS command prompt. Allegro for Board Layout Allegro is the physical layout system for PCB design. With Allegro you can place and route a design, and then generate the output and documentation necessary for the manufacture of that design. Allegro s rules-driven editing tools provide you with instant feedback on design rule violations. Seamless integration with SPECCTRA provides access to interconnect routing of critical signals, buses, areas, or for the whole design. Allegro comes with a variety of third party CAD interfaces, such as AutoCAD DXF and IDF, and third-party PCB database translators, such as PADS and PCAD. Starting Allegro You can start Allegro in one of the following ways: Choose Start Programs Cadence Allegro. From the Project Manager, choose Tools Allegro or click on the Layout button. The Cadence Product Choices dialog box appears if you have more than one license. This dialog box lets you choose from the available tools for which you have licenses. The Allegro January 2002 17 Product Version 14.2

PCB tool is licensed with PCB design studio with Concept HDL. For other Allegro products, see your Cadence representative. Allegro Design Flow The physical layout process consists of the following general flow. Step 1 Develop libraries. Step 2 Transfer logic and physical data. Create padstacks. Create symbols. Create board templates. Transfer native logic. Transfer third-party logic. Transfer third-party design data. January 2002 18 Product Version 14.2

Step 3 Prepare layout. Step 4 Layout the design. Step 5 Prepare final design. Step 6 Generate manufacturing outputs. Create a new drawing. Set drawing size. Define cross section layers. Assign and define properties. Define constraints. Define placement. Swap pins and gates. Add power and ground planes. Route connections. Run testprep. Run glossing. Rename reference designators. Run design rule checking. Create silkscreen. Backannotate to Concept or a third-party tool. Generate reports. Generate fabrication and assembly output. Create plot files. Create artwork. Output third-party design data. Importing Concept HDL Schematic Data into Allegro To import Concept HDL schematic design data into Allegro, from Allegro choose File Import Logic. The Import Logic dialog box appears. For information about this dialog box, click the Help button. Allegro reads and compiles the netlist and also generates a netin.log file. January 2002 19 Product Version 14.2

Exporting Allegro Data (Backannotating) to Concept HDL Use one of the following methods to use your Allegro board design data to update (backannotate) your schematic design in Concept HDL. For information about any of the resulting dialog boxes, click the Help button. From Allegro (for export to Concept HDL) Choose File Export Logic. The Export Logic dialog box appears. This dialog box lets you create schematic data files to be read into Concept HDL or supported third-party tools. (See the Allegro/ APD Design Guide: Transferring Design Data Logic, for information on third-party logic transfer.) From Project Manager (for export to Concept HDL only) Click the Design Sync button and select Import Physical from the menu. or The Import Physical dialog box appears. This dialog box lets you import Allegro board design data into Concept HDL. Click the Design Sync button and select Design Differences from the menu. The Design Differences dialog box appears. This dialog box lets you view the differences between the schematic and the board designs. You can choose to update the schematic or board design after assessing the differences. Exporting Allegro Data for SPECCTRA Routing To create data files for use with SPECCTRA, choose File Export SPECCTRA. The Export to SPECCTRA dialog box appears. For information about this dialog box, click the Help button. SPECCTRA for Automatic Routing Using its powerful shape-based architecture, the SPECCTRA automatic router defines the most efficient use of a PCB routing area. SPECCTRA performs design rule checks (DRCs) on Allegro constraints and design rules, including those that the engineer defines in Concept HDL. January 2002 20 Product Version 14.2

SPECCTRA handles staggered pin components and routes through them easily. Its diagonal routing algorithms handle components of non-standard dimensions (that previously required manual routing). The SPECCTRA automatic router is tightly integrated with the Allegro layout tool through the SPECCTRA Interface (SPIF). Starting SPECCTRA You can start SPECCTRA from Allegro or as a stand-alone batch program as follows: To start SPECCTRA from Allegro, choose one of the following menu items: Route SPECCTRA Route Automatic to set routing parameters and initiate routing of the entire board. Route SPECCTRA Route by Pick to route specific nets and components. Route SPECCTRA Interactive Editor to update your design with information based on parameters that you set up in the SPECCTRA Automatic Router Interface (SPIF). Choose Start Programs Cadence SPECCTRA Interface to update your design with information based on parameters that you set up in the SPECCTRA Automatic Router Interface (SPIF). Exporting SPECCTRA Routing Data (Backannotating) to Allegro Routing data is automatically added to a design if you use SPECCTRA from the Allegro interface. If you use SPECCTRA as a batch program, you can generate routing data for Allegro by selecting File Write Session from the SPECCTRA interface. The Write Session dialog box appears. SPECCTRA creates a session (.ses) file. Generating Manufacturing Output With Allegro Allegro provides you with several commands that produce manufacturing output. These commands are available from the Manufacture menu. One of these options is Manufacture Artwork, which creates data for manufacturers to physically put the printed circuit design onto film. Allegro supports vector-based and raster-based artwork processes. For more information about the Manufacture menu commands, see the online information that is available from the Allegro interface. January 2002 21 Product Version 14.2

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3 PCB Design Studio Options In addition to the products you get in PCB Design Studio, you can also add the following tools to enhance your design initiatives. This chapter contains the following information: CheckPlus for Checking Your Design on page 24 Variant Editor for Creating Versions on page 26 signal explorer for Inter-connect Analysis on page 28 January 2002 23 Product Version 14.2

PCB Design Studio Options CheckPlus for Checking Your Design CheckPlus is an electronic design rule checker that automatically detects a wide range of common design errors and oversights that can often occur in the design entry process. As project complexity increases, more rules, constraints, and properties must be a part of the initial phases of the design. CheckPlus ensures that accurate data is tested before moving to downstream processes. Error Checking CheckPlus checks your design for problems such as missing terminators, insufficient power supplies, short circuits, unconnected pins, constraint range violations, and the use of mismatched technologies. Automatic Highlighting CheckPlus automatically flags violations of predetermined design parameters and constraints, advising you of errors and oversights with on-screen reports and schematic highlighting. Customizable You can tailor the checking process based on company-specific knowledge, design practices, and manufacturing constraints. CheckPlus features include: A basic rule set to facilitate immediate use Alerts for common errors and design oversights with on-screen reports and schematic highlighting Customizable parameters and messages that provide flexibility for a perfect fit into your environment Quick feedback through a high-speed evaluation engine Centralized rule checking and rule development tasks January 2002 24 Product Version 14.2

PCB Design Studio Options An advanced rule development language (ARL) that allows for the addition of project- or company-specific rules through the CheckPlus toolkit. January 2002 25 Product Version 14.2

PCB Design Studio Options Variant Editor for Creating Versions You can use the Variant Editor to create and manage designs that have minor differences. These differing designs are called variants. Each variant includes a common base design consisting of a set of core elements. The presence or absence of a component, or slight differences in a component s properties (such as, resistance or voltage), for example, can cause variations. The Variant Editor reduces the maintenance effort of a design set, decreases the development time by providing faster time to market, reduces the chance of errors, and reduces the cost through consistent part selection. The Variant Editor allows you to: Define variant design components by using the Concept Component Browser that lists physical part table (PPT) rows. To simplify finding components from the Component List, you can filter components from the list of available components. Generate BOM that reflects the electrical stuff list for a variant. Generate a delta list of components from the base design for a variant. Generate a comparative BOM of different variants. Annotate a special designator to any component in the schematic that contains variant data. Merge a Variant database and a base schematic with the understanding that either the reference designator or the canonical path property must be in sync. Annotate variant data from the Variant database into the schematic. Generate the interface file that is read by Allegro to create variant assembly drawings. January 2002 26 Product Version 14.2

PCB Design Studio Options Cross-probe between the Concept-HDL schematic and the Variant user interface (UI). January 2002 27 Product Version 14.2

PCB Design Studio Options signal explorer for Inter-connect Analysis signal explorer is an entry-level PCB interconnect analysis tool available as an add-on option to Allegro studio. Using signal explorer, you can create and edit a virtual prototype of a net topology. You can simulate the circuit topology and examine the simulation results. After analyzing the simulation results, you can explore different circuit topologies by repositioning parts and modifying the parameters and part models of the circuit, adjusting the simulation setup, and resimulating. You can repeat this process multiple times to experiment with various what-if scenarios until the desired results are realized. You can save and reuse topology files and their attributes later. Allegro studio signal explorer offers a number of helpful capabilities for users who will typically be designing high-speed and high-performance digital systems that contain large applicationspecific ICs (ASICs), or processors, that communicate with multiple sub-system components. These include: Graphical topology exploration and analysis Allows the engineer to rapidly develop and review interconnect topology effectiveness and investigate topology element sensitivity Use of industry-standard IBIS simulation models Eliminates the need to create or translate models before using the tool Extraction of routed interconnect for analysis and what-if exploration Removes the need for random post-route interconnect editing to improve signal integrity Scalability Can be scaled into full constraint-driven place and route with advanced analysis capabilities for electromagnetic interference (EMI) and powerplane optimization. Can also define topology templates containing electrical constraints to drive PCB placement January 2002 28 Product Version 14.2

PCB Design Studio Options and routing in the high-end Allegro expert system and SPECCTRA expert autorouter, as well as the high-end version of SPECCTRAQuest interconnect designer. January 2002 29 Product Version 14.2