MUSES89 High Quality Audio J-FET Input Dual Operational Amplifier GENERAL DESCRIPTION The MUSES89 is a high quality Audio J-FET input dual operational amplifier. This is a mass production model of MUSES Series. By inheriting MUSES Technology we pursued in the "MUSES series", the MUSES89 is compatible in high-quality sound and productivity. The MUSES89 has improved the chip layout and the material, and is developing by thoroughly repeating the listening sound. The characteristics Low noise (8nV/ Hz), high-sr (5V/µs) and low distortion (.%, Av=) suitable for audio preamplifiers, active filters, and line amplifiers. In addition, taking advantage of the low input bias current that J-FET has, it is suitable for transimpedance amplifier (I/V converter). PACKAGE OUTLINE MUSES89D (DIP8) MUSES89E (SOP8) FEATURES PIN CONFIGLATION Operating Voltage ±3.5V to ±6V Low Noise 8nV/ Hz typ. THD.% typ. (Av=) Slew Rate 5V/µs typ. Channel Separation 5dB typ. High Current ma typ.(short-circuit current) Phase Margin 7 deg typ. Input Offset Voltage.8mV typ. 5mV max. Input Bias Current 5pA typ. 5pA max Voltage Gain 35dB typ. J-FET technology Package Outline DIP8, SOP8 JEDEC 5mil 3 Top View A B 8 7 6 5 PIN FUNCTION. A OUTPUT. A -INPUT 3. A +INPUT. V- 5. B +INPUT 6. B -INPUT 7. B OUTPUT 8.V+ APPLICATIONS Current to Voltage (I/V) Converters Hi-end Audio Active Filters Integrators I/V Digital Input DA Converter I/V LPF Buff DAC I/V converter + LPF circuit MUSES and this logo are trademarks of New Japan Radio Co., Ltd. Ver.3--5 - -
MUSES89 ABSOLUTE MAXIMUM RATING (Ta=5ºC unless otherwise specified) PARAMETER SYMBOL RATING UNIT Supply Voltage V + /V - ±8 V Differential Input Voltage Range V ID ±3(Note) V Common Mode Input Voltage Range V ICM ±5(Note) V Power Dissipation P D DIP8:87 SOP8:9(Note) mw Operating Temperature Range Topr -~+85 ºC Storage Temperature Range Tstg -5~+5 ºC (Note) For supply Voltages less than ±5 V, the maximum input voltage is equal to the Supply Voltage. (Note) Mounted on the EIA/JEDEC standard board (.3 76..6mm, two layer, FR-). (Note3) NJM89 is ESD (electrostatic discharge) sensitive device. Therefore, proper ESD precautions are recommended to avoid permanent damage or loss of functionality. RECOMMENDED OPERATING VOLTAGE (Ta=5ºC) PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT Supply Voltage V + /V - ±3.5 - ±6 V ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS (, Ta=5ºC, Vcm=V unless otherwise specified) PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT Supply Current Icc RL=, No Signal - 9 ma Input Offset Voltage V IO R S =5Ω ( -.8 5 mv Input Bias Current I B (Note) - 5 5 pa Input Offset Current I IO (Note) - pa Voltage Gain A V R L =kω, Vo=±3V 6 35 - db Voltage Gain A V R L =kω, Vo=±.8V 5 33 - db Voltage Gain3 A V3 R L =6Ω, Vo=.5V 5 3 - db Common Mode Rejection Ratio CMR V ICM =±.5V (Note5) 8 - db Supply Voltage Rejection Ratio SVR V + /V - =±3.5 to ±6V 8 - db Maximum Voltage V OM R L =kω ±3 ± - V Maximum Voltage V OM R L =kω ±.8 ±3.8 - V Maximum Voltage3 V OM3 R L =6Ω ±.5 ±3.5 - V Common Mode Input Voltage Range V ICM CMR 8dB ±.5 ± - V (Note) Written by absolute ratio. (Note5) CMR is calculated by specified change in offset voltage. (V ICM =V to +.5V, V ICM =V to -.5V) AC CHARACTERISTICS (, Ta=5ºC, Vcm=V unless otherwise specified) PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT Gain Bandwidth Product GB f=khz - - MHz Unity Gain Frequency f T A V =+, R S =Ω, R L =kω, C L =pf - - MHz Phase Margin Φ M A V =+, R S =Ω, R L =kω, C L =pf - 7 - Deg Equivalent Input Noise Voltage V NI f=khz - 8 - nv/ Hz Equivalent Input Noise Voltage V NI RIAA, R S =.kω, 3kHz, LPF -. 3.5 µvrms Total Harmonic Distortion THD f=khz, A V =+, Vo=5Vrms, R L =kω -. - % Channel Separation CS f=khz, A V =-, R L =kω - 5 - db Slew Rate SR A V =, V IN =Vp-p, R L =kω, C L =pf - 5 - V/us - - Ver.3--5
MUSES89 Application Notes Package Power, Power Dissipation and Power IC is heated by own operation and possibly gets damage when the junction power exceeds the acceptable value called Power Dissipation P D. The dependence of the MUSES89 P D on ambient temperature is shown in Fig. The plots are depended on following two points. The first is P D on ambient temperature 5ºC, which is the maximum power dissipation. The second is W, which means that the IC cannot radiate any more. Conforming the maximum junction temperature Tjmax to the storage temperature Tstg derives this point. Fig. is drawn by connecting those points and conforming the P D lower than 5ºC to it on 5ºC. The P D is shown following formula as a function of the ambient temperature between those points. Dissipation Power P D = Tjmax - Ta θja [W] (Ta=5ºC to Ta=5ºC) Where, θja is heat thermal resistance which depends on parameters such as package material, frame material and so on. Therefore, P D is different in each package. While, the actual measurement of dissipation power on MUSES89 is obtained using following equation. (Actual Dissipation Power) = (Supply Current Icc) X (Supply Voltage V + V-) ( Power Po) The MUSES89 should be operated in lower than P D of the actual dissipation power. To sustain the steady state operation, take account of the Dissipation Power and thermal design. P D [mw] 9 87 SOP8 DIP8-5 85 (Topr max.) 5 (Tstg max.) Ta [deg] Fig. Power Dissipations vs. Ambient Temperature on the MUSE89 Ver.3--5-3 -
MUSES89 TYPICAL CARACTERISTICS THD+N vs. Voltage (Frequency), A V =+, R L =k, Ta=5ºC THD+N vs. Voltage (Frequency), A V =+, R L =k, Ta=5ºC f=hz THD+N [%]... f=khz f=khz f=khz THD+N [%]... f=khz f=khz... Voltage [Vrms]... Voltage [Vrms] Voltage Noise vs. Frequency, A V =+, R S =Ω, R L =, Ta=5ºC - Channel Separation vs. Frequency, A V =-, R L =kω, Ta=5ºC Equivalent Input Noise Voltage [nv/ Hz] 8 6 Channel Separation [db] -5-3 -35 - -5-5 -55 k k k Frequency [Hz] -6 k k k Frequency [Hz] 6 Gain vs. Frequency, A V =+, R L =kω, C L =pf Phase Margin vs. Temperature (Supply Voltage), A V =+, R S =Ω, R L =kω, C L =pf, V IN =-3dBm 9 Gain Voltage Gain [db] - - Phase -5-9 -35 Phase [deg] Phase Margin [deg] 8 7-6 -8 k k M M M Frequency [Hz] 6-5 -5 5 5 75 5 5 - - Ver.3--5
MUSES89 TYPICAL CARACTERISTICS Pulse Response, Gv=dB, C L =pf, R L =kω, Ta=5ºC Input 8 7 Slew Rate vs. Temperature, V IN =V P-P, f=khz, Gv=dB, C L =pf, R L =kω Voltage [V/div] Slew Rate [V/µs] 6 5 3 Fall Rise Time [µs/div] -5-5 5 5 75 5 5 Supply Current vs. Supply Voltage A V =db Supply Current vs. Temperature (Supply Voltage) A V =db Supply Current [ma] 8 6 Supply Current [ma] 8 6 ± ± ±8 ± ±6 Supply Voltage V + /V - [V] -5-5 5 5 75 5 5 Input Offset Voltage vs. Supply Voltage V ICM =V, V IN =V. Input Offset Voltage vs. Temperature (Supply Voltage) V ICM =V, V IN =V. Input Offset Voltage [mv].5..5. -.5 Input Offset Voltage [mv].5..5. -.5 -. ± ±8 ± ±6 Supply Voltage V + /V - [V] -. -5-5 5 5 75 5 5 Ver.3--5-5 -
MUSES89 TYPICAL CARACTERISTICS. Input Offset Voltage vs. Common Mode Input Voltage. Input Offset Voltage vs. Common Mode Input Voltage Input Offset Voltage [mv].5..5. -.5 Input Offset Voltage [mv].5..5. -.5 -. -5 - -5 5 5 Common Mode Input Voltage [V] -. - -3 - - 3 Common Mode Input Voltage [V] Input Bias Current vs. Temperature (Supply Voltage) V ICM =V, n n Input Bias Current vs. Common Mode Input Voltage, Ta=5ºC 9 Input Bias Current [A] n n p p Input Bias Current [pa] 8 7 6 5 p -5-5 5 5 75 5 5 3-5 - -5 5 5 Common Mode Input Voltage [V] CMR vs. Temperature SVR vs. Temperature V ICM =V, ±6V Common Mode Rejection Ratio [db] 3 9 V ICM =-.5V V V ICM =V +.5V Supply Voltage Rejection Ratio [db] 3 9 8-5 -5 5 5 75 5 5 8-5 -5 5 5 75 5 5-6 - Ver.3--5
MUSES89 TYPICAL CARACTERISTICS Voltage [V] 5 5-5 - Voltage vs. Current Isource Isink Voltage [V] 3 - - -3 Voltage vs. Current Isource Isink Ta=+5ºC -5 k Current [ma] - k Current [ma] 5 Maximum Voltage vs. Load Resistance, Gv=open, R L to V Maximum Voltage vs. Load Resistance, Gv=open, R L to V Maximum Voltage [V] 5-5 - Maximum Voltage [V] 3 - - -3-5 k k k Load Resistance [Ω] - k k k Load Resistance [Ω] Ver.3--5-7 -
MUSES89 APPLICATION CIRCUIT Input Gain Stage Att Buff AD Converter Digital Digital Input DA Converter I/V I/V LPF Buff (Fig.: ADC Input) (Fig.:DAC ) L-ch. Intput L-ch. HPF DAC R-ch. Intput R-ch. Vcc /Vcc (Fig.:DAC LPF Circuit ) /Vcc (Fig.3: Half Vcc Buffer on Single Supply Application) <CAUTION> The specifications on this data book are only given for information, without any guarantee as regards either mistakes or omissions. The application circuits in this data book are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. - 8 - Ver.3--5