ST Sitronix ST792 Main Features Operation Voltage Range: 2.7V to 5.5V Support 8-bit, 4-bit and serial bus MPU interface 64 x 6-bit display RAM (DDRAM) Supports 6 words x 4 lines (Max) LCD display range 6 words x 2 lines 64 x 256-bit Graphic Display RAM (GDRAM) 2M-bits Character Generation ROM (CGROM): Support 892 Chinese words (6x6 dot matrix) 6K-bit half-width Character Generation ROM (HCGROM): Supports 26 characters (6x8 dot matrix) 32-common x 64-segment (2 lines of character) LCD drivers Automatic power on reset (POR) External reset pin (XRESET) With the extension segment drivers, the display area can up to 6x2 lines Built-in RC oscillator: Frequency is adjusted by an external resistor Function Description Chinese Fonts built in LCD controller/driver Low power consumption design Normal mode (45uA Typ VDD=5V) Standby mode (3uA Max VDD=5V) VLCD (V to V SS ): max 7V Graphic and character mixed display mode Multiple instructions: Display Clear Return Home Display ON/OFF Cursor ON/OFF Display Character Blink Cursor Shift Display Shift Vertical Line Scroll Reverse Display (by line) Standby Mode Built-in voltage booster (2 times) VOUT: max 7V /33 Duty (with ICON) ST792 LCD controller/driver IC can display alphabets, numbers, Chinese fonts and self-defined characters. It supports 3 kinds of bus interface, namely 8-bit, 4-bit and serial. All functions, including display RAM, Character Generation ROM, LCD display drivers and control circuits are all in a one-chip solution. With a minimum system configuration, a Chinese character display system can be easily achieved. ST792 includes character ROM with 892 6x6 dots Chinese fonts and 26 6x8 dots half-width alphanumerical fonts. Besides, it supports 64x256 dots graphic display area for graphic display (GDRAM). Mix-mode display with both character and graphic data is possible. ST792 has built-in CGRAM and provide 4 sets software programmable 6x6 fonts. ST792 has wide operating voltage range (2.7V to 5.5V). It also has low power consumption. So ST792 is suitable for battery-powered portable device. ST792 LCD driver consists of 32-common and 64-segment. Company with the extension segment driver (ST792) ST792 can support up to 32-common x 256-segment display. Part Number ST792-A ST792-B ST792-C ST792-F Font Code BIG-5 Code Set (Traditional Chinese) GB Code Set (Simplified Chinese) Chinese (Traditional/Simplified) & Japanese Chinese (Traditional/Simplified), Japanese & Korean V4. /49 28/8/8
ST792 ST792 Specification Reversion History Version Date Description C.7 2/2/5 C.8 2/3/ C.9 2/5/28 C2. 2/7/3 V2. 2/8/7. VCC changed to VDD. 2. VLCD changed from VCC-V5 to V-VSS. 3. DC characteristics input High voltage (Vih) changed to.7vdd. 4. DC characteristics output High voltage (Voh) changed to.8vdd.. Chip Size changed. 2. ICON 256 dots changed to 24 dots. 3. XOFF normal high sleep Low changed to normal low sleep High. 4. Added XOFF application. 5. Modified application of ST792: PIN 4~6 are floating. (PIN 4~6 are test pin) 6. Modified voltage doubler CAPP, CAPM, CAP2M capacitors polarity. Icon RAM TABLE changed. (TABLE-6) 2. Booster description modified. (PAGE-29) 3. AC Characteristics modified. 4. Added 2Line 6 Chinese Word (32Com X 256Seg) application circuit. 5. Added oscillation resistor s relation to power consumption and frequency.. Added Register initial values. 2. Voltage booster CAPM CAPP polarity changed (PAGE-3).. Modified Table 7 (PAGE-4). 2. Change to English version. V2.c 2//8. Modified page-38 Serial interface timing diagram. V2.d 22/5/9. Add the standard code (Japan, GB code, BIG-5 code). V3. 22//. Delete sleep mode function. V3. 23/4/. Modified GDRAM Address (AC5 AC, h 3Fh). V3.2 23/9/9. Add the CGROM and HCGROM test application circuit. V3.3 24/3/29. Updat the using method for ICON. V3.4 25/5/24. ICON no used. V3.5 25/5/24. Add VOUT voltage limitation. 2. Remove IRAM related descriptions. V3.6 25/6/6. Fix the check sum count number on Page 28~3. 65536->655362, 24->242. 2. Modify the description about serial interface. V3.7 27/7/24. Add CGROM/HCGROM checksum operation time. V3.8 27/2/2. Add Clear DDRAM step before check sum process. V3.9 28/3/3. Modify 4-bit initial sequence. V4. 28/8/8. Add Font Code F at Page. 2. Modify the description of Font Code Table at Page. V4. 2/49 28/8/8
ST792 System Block Diagram PSB Reset Circuit RESI RESO CL CL2 M CLK Timing Generator DOUT RS RW E DB4 to DB7 MPU Interface Instruction Register (IR) Instruction Decoder Address Counter Display Data RAM (DDRAM) 64 x 6 bits 64-bit shift register 33/49-bit shift register 64-bit latch circuit Common Signal Driver Segment Signal Driver COM to COM32 SEG to SEG64 DB to DB3 Input/ Output Buffer Data Register (DR) LCD Drive Voltage Selector Busy Flag Graphic RAM (GDRAM) 24 x 6 bits Half size Character ROM (HCGROM) 24x6 bits Character Generator RAM (CGRAM) 24 bits Character Generator ROM (CGROM) 2M bits Cursor Blink Scroll Controller Vss Parallel/Serial converter and Attribute Circuit VDD XRESET V V V2 V3 V4 XOFF V4. 3/49 28/8/8
ST792 Pad Diagram 3 3 ST792 ST792 36 (,) 68 99 69 98 Origin: center of chip Coordinates: from pad center Chip size: 535 X 474 Pad open: 9 X 9 Pad pitch: 25 unit: μm * Chip substrate must connect to VSS V4. 4/49 28/8/8
ST792 PAD Coordinates (Unit: um) No. Name X Y V -2548 82 2 V -2548 688 3 V2-2548 562 4 CLK -2548 438 5 TT -2548 32 6 TT2-2548 88 7 V3-2548 62 8 V4-2548 938 9 VSS -2548 82 VDD -2548 688 XRESET -2548 562 2 CL -2548 438 3 CL2-2548 32 4 VDD -2548 88 5 M -2548 62 6 DOUT -2548-62 7 RS -2548-88 8 RW -2548-32 9 E -2548-438 2 VSS -2548-562 2 OSC -2548-688 22 OSC2-2548 -82 23 PSB -2548-938 24 D -2548-62 25 D -2548-88 26 D2-2548 -32 27 D3-2548 -438 28 D4-2548 -562 29 D5-2548 -688 3 D6-2548 -82 3 D7-236 -933 32 XOFF -28-933 33 VOUT -256-933 34 CAP3M -93-933 35 CAPP -86-933 36 CAPM -68-933 37 CAP2P -556-933 38 CAP2M -43-933 No. Name X Y 39 VD2-36 -933 4 C[] -8-933 4 C[2] -56-933 42 C[3] -93-933 43 C[4] -86-933 44 C[5] -68-933 45 C[6] -556-933 46 C[7] -43-933 47 C[8] -36-933 48 C[9] -8-933 49 C[] -56-933 5 C[] 69-933 5 C[2] 94-933 52 C[3] 39-933 53 C[4] 444-933 54 C[5] 569-933 55 C[6] 694-933 56 C[7] 89-933 57 C[8] 944-933 58 C[9] 69-933 59 C[2] 94-933 6 C[2] 39-933 6 C[22] 444-933 62 C[23] 569-933 63 C[24] 694-933 64 C[25] 89-933 65 C[26] 944-933 66 C[27] 269-933 67 C[28] 294-933 68 C[29] 239-933 69 C[3] 2548-82 7 C[3] 2548-688 7 C[32] 2548-562 72 C[33] Not use 2548-438 73 S[64] 2548-32 74 S[63] 2548-88 75 S[62] 2548-62 76 S[6] 2548-938 V4. 5/49 28/8/8
ST792 No. Name X Y 77 S[6] 2548-82 78 S[59] 2548-688 79 S[58] 2548-562 8 S[57] 2548-438 8 S[56] 2548-32 82 S[55] 2548-88 83 S[54] 2548-62 84 S[53] 2548 62 85 S[52] 2548 88 86 S[5] 2548 32 87 S[5] 2548 438 88 S[49] 2548 562 89 S[48] 2548 688 9 S[47] 2548 82 9 S[46] 2548 938 92 S[45] 2548 62 93 S[44] 2548 88 94 S[43] 2548 32 95 S[42] 2548 438 96 S[4] 2548 562 97 S[4] 2548 688 98 S[39] 2548 82 99 S[38] 239 933 S[37] 294 933 S[36] 269 933 2 S[35] 944 933 3 S[34] 89 933 4 S[33] 694 933 5 S[32] 569 933 6 S[3] 444 933 7 S[3] 39 933 8 S[29] 94 933 9 S[28] 69 933 S[27] 944 933 S[26] 89 933 2 S[25] 694 933 3 S[24] 569 933 4 S[23] 444 933 5 S[22] 39 933 No. Name X Y 6 S[2] 94 933 7 S[2] 69 933 8 S[9] -56 933 9 S[8] -8 933 2 S[7] -36 933 2 S[6] -43 933 22 S[5] -556 933 23 S[4] -68 933 24 S[3] -86 933 25 S[2] -93 933 26 S[] -56 933 27 S[] -8 933 28 S[9] -36 933 29 S[8] -43 933 3 S[7] -556 933 3 S[6] -68 933 32 S[5] -86 933 33 S[4] -93 933 34 S[3] -256 933 35 S[2] -28 933 36 S[] -236 933 V4. 6/49 28/8/8
ST792 Pin Description Name No. I/O Connects to Function XRESET I System reset input (low active). PSB 23 I Interface selection: : serial mode; : 8/4-bit parallel bus mode. RS(CS*) 7 I MPU Parallel Mode: Register select. : Select instruction register (write) or busy flag, address counter (read); : Select data register (write/read). Serial mode: Chip select. : chip enabled; : chip disabled. When chip is disabled, SID and SCLK should be set as H or L. Transcient of SID and SCLK is not allowed. RW(SID*) 8 I MPU Parallel Mode: Read/Write control. : Write; : Read. Serial Mode: Sserial data input. E(SCLK*) 9 I MPU Parallel Mode: : Enable trigger. Serial Mode: Serial clock. D4 to D7 28~3 I/O MPU Higher nibble data bus of 8-bit interface and data bus for 4-bit interface D to D3 24~27 I/O MPU Lower nibble data bus of 8-bit interface. CL 2 O Latch signal for extension segment Extension segment drv. drivers. CL2 3 O Shift clock for extension segment Extension segment drv. drivers. M 5 O AC signal for extension segment drivers Extension segment drv. voltage inversion. DOUT 6 O Data output for extension segment Extension segment drv. drivers. COM to COM32 4~7 O LCD Common signals. SEG to SEG64 36~73 O LCD Segment signals. V to V4 ~3,7,8 LCD bias voltage. V ~ V4 7V. V DD,4 I Power V DD : 2.7V to 5.5V. Vss 9,2 I Power VSS: V. OSC, OSC2 2,22 I, O Resistors VOUT 33 O Resistors Using internal oscillator: 5.V R=33K; 2.7V R=8K. Using external clock: Use OSC as external clock input. LCD voltage doubler output. VOUT 7V. *Note: The OSC pin must have the shortest wiring pattern of all other pins. To prevent noise from other signal lines, it should also be enclosed by the largest GND pattern. Poor anti-noise characteristics on the OSC line will result in malfunction, or adversely affect the clock s duty ratio. V4. 7/49 28/8/8
ST792 Pin Description (continued) Name No. I/O Connects to Description CAP3M CAPP CAPM CAP2M 34 35 36 38 I/O Capacitors Capacitor pins for voltage doubler Voltage 7V. XOFF 32 O Reserved (no connection). CAP2P 37 Reserved (no connection). C[33] 72 O Reserved (no connection). VD2 39 I Reference voltage Voltage doubler reference voltage. If use internal voltage doubler, please make sure that: VD2 3.5V or VOUT 7V and CAP3M 7V. CLK TT TT2 4 5 6 I For CGROM/HCGROM checksum. Refer to checksum application. Note:. 7V>=VOUT>=V>=V>=V2>=V3>=V4 must be maintained 2. Two clock options: As shown below. OSC OSC2 OSC OSC2 R Clock input R=33K (VDD=5.V) R=8K (VDD=2.7V) 8 External Resistor vs. Current (VDD=5V) 9 External Resistor vs. Frequency (VDD=5V) 7 8 Iss (ua) 6 5 4 3 2 Frequency(KHz) 7 6 5 4 3 2 5 5 25 4 6 8 Resistor(K) 5 5 25 4 6 8 Resistor(K) 3. When using voltage doubler (VOUT), it is recommended that the sum of those divide resistors (R~R5) should be larger than 2K Ohm. So that the voltage doubler can provide sufficient power. V4. 8/49 28/8/8
ST792 Voltage Doubler Voltage Doubler Reference Voltage Vss VD2 CAPM CAPP CAP2M CAP2P CAP3M VOUT VOUT 9 8 VOUT vs. VD2 Do not operate in this area. 7 VOUT (V) 6 5 4 3 2 5 4.8 4.6 4.4 4.2 4 3.8 3.6 3.4 3.2 3 2.8 2.6 2.4 2.2 2.8 VD2 (V) Voltage Doubler mode: VD2 & Vout output characteristic Notes: Total resistance of the Follower deviding resistors should larger than 2K Ohm. Booster Capacitor uses 4.7uF Panel size: 8mm x 28mm (check display) V4. 9/49 28/8/8
ST792 Function Description System interface ST792 supports 3 kinds of bus interface to communicate with MPU: 8-bit parallel, 4-bit parallel and clock synchronized serial interface. Parallel interface is selected by PSB= and serial interface is by PSB=. 8-bit / 4-bit interface is selected by function set instruction DL bit. Two 8-bit registers (Data Register DR and Instruction Register IR) are used in ST792 to access DRAM or Register. Data Register (DR) can access DDRAM, CGRAM and GDRAM through the address pointer implemented by Address Counter (AC). Instruction Register (IR) stores the instruction sent by MPU to ST792. 4 kinds of parallel interface access mode can be selected through RS and RW: RS RW Description L L MPU write instruction to instruction register (IR) L H MPU read busy flag (BF) and address counter (AC) H L MPU write data to data register (DR) H H MPU read data from data register (DR) * The serial interface access modes do not have Read operation. Busy Flag (BF) ST792 needs a process time for any received instruction. Before finishing the received instruction, any further instruction is not accepted. The process time of each instruction is not equal and the internal process is finished or not can be determined by the BF. Internal operation is in progress while BF=, that means ST792 is in busy state. No further instructions will be accepted until BF=. MPU must check BF to determine whether the internal operation is finished or not before issuing instruction. Address Counter (AC) Address Counter (AC) is used as the address pointer of DDRAM, CGRAM and GDRAM. (AC) can be set by instruction. After that, accesses (Read/Write operations) to the memories, such as DDRAM, CGRAM or GDRAM, (AC) will be increased or decreased by (according to the setting in Entry Mode Set Register). When RS=, RW= and E= the value of (AC) will be output to DB6~DB. Character Generation ROM (CGROM) and Half-width Character Generation ROM (HCGROM) ST792 is built in a Character Generation ROM (CGROM) to provide 892 6x6 character fonts and a Half-width Character Generation ROM to provide 26 8x6 alphanumeric characters. It is easy to support multi-language applications such as Chinese and English. Two consecutive bytes are used to specify one 6x6 character or two 8x6 half-width characters. Character codes are written into DDRAM and the corresponding fonts are mapped from CGROM or HCGROM to the display drivers. Character Generation RAM (CGRAM) ST792 is built in a Character Generation RAM (CGRAM) to support user-defined fonts. Four sets of 6x6 bit-maped RAM spaces are available. These user-defined fonts are displayed the same ways as CGROM fonts by writing the related character code into the DDRAM. V4. /49 28/8/8
ST792 Display Data RAM (DDRAM) There are 64x2 bytes RAM spaces for the Display Data RAM. It can store display data such as 6 characters (6x6) by 4 lines or 32 characters (8x6) by 4 lines. However, only 2 character-lines (maximum 32 common outputs) can be displayed at one time. Character codes stored in DDRAM will refer to the fonts specified by CGROM, HCGROM and CGRAM. ST792 can display half-width HCGROM fonts, user-defined CGRAM fonts and full 6x6 CGROM fonts. The character codes in H~6H will use user-defined fonts in CGRAM. The character codes in 2H~7FH will use half-width alpha numeric fonts. The character code larger than AH will be treated as 6x6 fonts and will be combined with the next byte automatically. The 6x6 BIG5 fonts are stored in A4H~D75FH while the 6x6 GB fonts are stored in AAH~F7FFH. In short:. To display HCGROM fonts: Write 2 bytes of data into DDRAM to display two 8x6 fonts. Each byte represents character. The data is among 2H~7FH. 2. To display CGRAM fonts: Write 2 bytes of data into DDRAM to display one 6x6 font. Only H, 2H, 4H and 6H are acceptable. 3. To display CGROM fonts: Write 2 bytes of data into DDRAM to display one 6x6 font. A4H~D75FH are BIG5 code, AAH~F7FFH are GB code. The higher byte (D5~D8) is written first and the lower byte (D7~D) is the next. Please refer to Table 5 for the relationship between DDRAM and the address/data of CGRAM. CGRAM fonts and CGROM fonts can only be displayed in the start position of each address. (Refer totable 4) 8 8 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L S i t r o n i x S T 7 9 2 矽 創 電 子.. 中 文 編 碼 ( 正 確 ) 矽 創 電 子... 中 文 編 碼 Incorrect start position Table 4 V4. /49 28/8/8
ST792 Graphic RAM (GDRAM) Graphic Display RAM has 64x256 bits bit-mapped memory space. GDRAM address is set by writing 2 consecutive bytes of vertical address and horizontal address. Two-byte data (6 bits) configures one GDRAM horizontal address. The Address Counter (AC) will be increased by one automatically after receiving the 6-bit data for the next operation. After the horizontal address reaching FH, the horizontal address will be set to H and the vertical address will not change. The procedure is summarized below:. Set vertical address (Y) for GDRAM 2. Set horizontal address (X) for GDRAM 3. Write D5~D8 to GDRAM (first byte) 4. Write D7~D to GDRAM (second byte) Please refer to Table 7 for Graphic Display RAM mapping. LCD driver ST792 embedded LCD driver has 33 commons and 64 segments to drive the LCD panel. Segment data from CGRAM, CGROM and HCGROM are shifted into the 64 bits segment latche to display. Extended segment driver (ST792) can be used to extend the segment outputs upto 256 segments. V4. 2/49 28/8/8
ST792 DDRAM data (char. code) B B B B B B5~ B4 3 2 5 X X X X CGRAM Addr. B B B B B 4 3 2 CGRAM data (higher byte) CGRAM data (lower byte) D D D D D D D D 7 6 5 4 3 2 D D D D D D D D 9 8 5 4 3 2 Table 5: DDRAM data (character code) vs. CGRAM data/address map Note:. DDRAM data (character code) bit and bit2 are identical with CGRAM address bit4 and bit5. 2. CGRAM address bit to bit3 specify total 6 rows. Row-6 is for cursor display. The data in Row-6 will be logically OR to the cursor. 3. CGRAM data for each address is 6 bits. 4. To select the CGRAM font, the bit4 through bit5 of DDRAM data must be while bit and bit3 are don t care. V4. 3/49 28/8/8
ST792 Table 6 6x8 half-width characters V4. 4/49 28/8/8
ST792 GDRAM Vertical address Y ( ) 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 2 2 22 23 24 25 26 27 28 29 3 3 32 33 34 35 36 37 38 39 4 4 42 43 44 45 46 47 48 49 5 5 52 53 54 55 56 57 58 59 6 6 62 63 GDRAM Horizontal address ( X )... 5...... b5 b4 b3... b Table 7 GDRAM display coordinates and corresponding address V4. 5/49 28/8/8
ST792 Instructions ST792 offers basic instruction set and extended instruction set: Instruction Set : (RE=: Basic Instruction) Inst. Display Clear Return Home Entry Mode Set Display Control Cursor Display Control Function Set Set CGRAM Address. Set DDRAM Address. Read Busy Flag (BF) & AC. Code RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB X I/D S D C B S/C R/L X X DL X RE X X Description Fill DDRAM with "2H" and set DDRAM address counter (AC) to "H". Set DDRAM address counter (AC) to "H", and put cursor to origin ;the content of DDRAM are not changed Set cursor position and display shift when doing write or read operation D=: Display ON C=: Cursor ON B=: Character Blink ON Cursor position and display shift control; the content of DDRAM are not changed DL= 8-bit interface DL= 4-bit interface RE=: extended instruction RE=: basic instruction Set CGRAM address to address counter (AC) AC5 AC4 AC3 AC2 AC AC Make sure that in extended instruction SR= (scroll or AC6 RAM address select) AC5 AC4 AC3 AC2 AC AC Set DDRAM address to address counter (AC) AC6 is fixed to Read busy flag (BF) for completion of internal operation, also BF AC6 AC5 AC4 AC3 AC2 AC AC Read out the value of address counter (AC) Write RAM D7 D6 D5 D4 D3 D2 D D Read RAM D7 D6 D5 D4 D3 D2 D D Write data to internal RAM (DDRAM/CGRAM/GDRAM) Read data from internal RAM (DDRAM/CGRAM/GDRAM) Exec time (54KHZ).6 ms 72 us 72 us 72 us 72 us 72 us 72 us 72 us us 72 us 72 us V4. 6/49 28/8/8
ST792 Instruction set 2: (RE=: extended instruction) Inst. Code Exec time Description RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB (54KHZ) Standby Enter standby mode, any other instruction can terminate. COM 32 are halted. 72 us Scroll or RAM SR=: enable vertical scroll position SR Address. SR=: enable CGRAM address (basic instruction) 72 us Select Select out of 4 line (in DDRAM) and decide whether to Reverse R R reverse the display by toggling this instruction (by line) R,R initial value is, 72 us DL= :8-bit interface DL= :4-bit interface Extended RE=: extended instruction set Function DL X G RE RE=: basic instruction set Set G= :graphic display ON 72 us G= :graphic display OFF Set Scroll Address AC5 AC4 AC3 AC2 AC AC SR=: AC5~AC the address of vertical scroll 72 us Set GDRAM address to address counter (AC) Set Graphic Set the vertical address first and followed the horizontal Display AC3 AC2 AC AC address by consecutive writings RAM AC5 AC4 AC3 AC2 AC AC Vertical address range: AC5 AC Address Horizontal address range: AC3 AC 72 us Note:. Make sure that ST792 is not in busy state by reading the busy flag before sending instruction or data. If using delay loop instead, please make sure the delay time is enough. Please refer to the instruction execution time. 2. RE is the selection bit of basic and extended instruction set. After setting the RE bit, the value will be kept. So that the software doesn t have to set RE every time when using the same instruction set. V4. 7/49 28/8/8
ST792 Initial Setting (Register flag) (RE=: basic instruction) Inst. Entry Mode Set Code RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB I/D S Description Cursor move to right,ddram address counter (AC) plus Display Control D C B Display, cursor and blink are ALL OFF CURSOR DISPLAY S/C R/L X X SHIFT X X No cursor or display shift operation FUNCTION SET DL X RE X X 8-bit MPU interface, basic instruction set Initial Setting (Register flag) (RE=: extended instruction set) Inst. SCROLL OR RAM ADDR. SELECT Code Description RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB SR Allow vertical scroll or set CGRAM address REVERSE R R Begin with normal and toggle to reverse EXTENDED DL X RE FUNCTION G SET Graphic display OFF V4. 8/49 28/8/8
ST792 Description of basic instruction set Display Clear RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code This instruction will change the following items:. Fill DDRAM with "2H"(space code). 2. Set DDRAM address counter (AC) to"h". 3. Set Entry Mode I/D bit to be "". Cursor moves right and AC adds after write or read operation. Return Home RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code X Set address counter (AC) to "H". Cursor moves to origin. Then content of DDRAM is not changed. Enry Mode Set RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code I/D S Set the cursor movement and display shift direction when doing write or read operation. I/D: Address Counter Control: (Increase/Decrease) When I/D = "", cursor moves right, address counter (AC) is increased by. When I/D = "", cursor moves left, address counter (AC) is decreased by. S: Display Shift Control: (Shift Left/Right) S I/D DESCRIPTION H H Entire display shift left by H L Entire display shift right by V4. 9/49 28/8/8
ST792 Display Control RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code D C B Controls display, cursor and blink ON/OFF. D: Display ON/OFF control bit When D = "", display ON When D = "", display OFF, the content of DDRAM is not changed C: Cursor ON/OFF control bit When C = "", cursor ON. When C = "", cursor OFF. B: Character Blink ON/OFF control bit When B = "", cursor position blink ON. Then display data (character) in cursor position will blink. When B = "", cursor position blink OFF Cursor/Display Shift Control RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code S/C R/L X X This instruction configures the cursor moving direction or the display shifting direction. The content of DDRAM is not changed. S/C R/L Description AC Value L L Cursor moves left by position AC=AC- L H Cursor moves right by position AC=AC+ H L Display shift left by, cursor also follows to shift. AC=AC H H Display shift right by, cursor also follows to shift. AC=AC V4. 2/49 28/8/8
ST792 Function Set RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code DL X RE X X DL: 4/8-bit interface control bit When DL = "", 8-bit MPU bus interface When DL = "", 4-bit MPU bus interface RE: extended instruction set control bit When RE = "", extended instruction set When RE = "", basic instruction set In same instruction cannot alter DL and RE at once. Make sure that change DL first then RE. Set CGRAM Address RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code AC5 AC4 AC3 AC2 AC AC Set CGRAM address into address counter (AC) AC range is H 3FH Make sure that in extended instruction SR= (scroll address or RAM address select) Set DDRAM Address RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code AC6 AC5 AC4 AC3 AC2 AC AC Set DDRAM address into address counter (AC). First line AC range is 8H 8FH Second line AC range is 9H 9FH Third line AC range is AH AFH Fourth line AC range is BH BFH Please note that only 2 lines can be display with one ST792. Read Busy Flag (BF) and Address RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code BF AC6 AC5 AC4 AC3 AC2 AC AC Read busy flag (BF) can check whether the internal operation is finished or not. At the same time, the value of address counter (AC) is also read. When BF =, further instruction(s) will not be accepted until BF =. V4. 2/49 28/8/8
ST792 Write Data to RAM RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code D7 D6 D5 D4 D3 D2 D D Write data to the internal RAM and increase/decrease the (AC) by Each RAM address (CGRAM, DDRAM and GDRAM ) must write 2 consecutive bytes for 6-bit data. After receiving the second byte, the address counter will increase or decrease by according to the entry mode set control bit. Read RAM Data RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code D7 D6 D5 D4 D3 D2 D D Read data from the internal RAM and increase/decrease the (AC) by After the operation mode changed to Read (CGRAM, DDRAM and GDRAM ), a Dummy Read is required. There is no need to add a Dummy Read for the following bytes unless a new address set instruction is issued. V4. 22/49 28/8/8
ST792 Description of extended instruction set Standby RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code This Instruction will set ST792 entering the standby mode. Any other instruction follows this instruction will terminate the standby mode. The content of DDRAM remains the same. Vertical Scroll or RAM Address Select RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code SR When SR = "", the Vertical Scroll mode is enabled. When SR = "", Set CGRAM Address instruction (basic instruction) is enabled. Reverse RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code R R Select out of 4 lines to reverse the display and to toggle the reverse condition by repeating this instruction. R, R initial vale is. The first time issuing this instruction, the display will be reversed while the second time will return the display become normal. R R Description L L First line normal or reverse L H Second line normal or reverse H L Third line normal or reverse H H Fourth line normal or reverse Please note that only 2 lines out of 4 lines of display data can be displayed with one ST792. V4. 23/49 28/8/8
ST792 Extended Function Set RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code DL X RE G X DL: 4/8-bit interface control bit When DL = "", 8-bit MPU interface. When DL = "", 4-bit MPU interface. RE: extended instruction set control bit When RE = "", extended instruction set When RE = "", basic instruction set G: Graphic display control bit When G = "", Graphic Display ON When G = "", Graphic Display OFF In same instruction cannot alter DL, RE and G at once. Make sure that change DL or G first and then RE. Set Scroll Address RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code AC5 AC4 AC3 AC2 AC AC SR=: AC5~AC is vertical scroll displacement address Set Graphic RAM Address RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code AC5 AC4 AC3 AC2 AC AC RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code AC3 AC2 AC AC Set GDRAM address into address counter (AC). This is a 2-byte instruction. The first instruction sets the vertical address while the second one sets the horizontal address (write 2 consecutive bytes to complete the vertical and horizontal address setting). Vertical address range is AC5...AC Horizontal address range is AC3 AC The address counter (AC) of graphic RAM (GRAM) will be increased automatically after the vertical and horizontal addresses are set. After horizontal address is increased upto FH, it will automatically return to H. However, the vertical address will not increase as the result of the same action. V4. 24/49 28/8/8
ST792 Parallel interface: ST792 is in parallel mode by pulling up PSB pin. ST792 can select 8-bit or 4-bit bus interface by setting the DL control bit in Function Set instruction. MPU can control RS, RW, E and DB DB7 pins to complete the data transmission. In 4-bit transfer mode, every 8-bit data or instruction is separated into 2 parts. The higher 4 bits (bit-7~bit-4) data will be transfered first through data pins (DB7~DB4). The lower 4 bits (bit-3~bit-) data will be transfered second through data pins (DB7~DB4). The (DB3~DB) data pins are not used during 4-bit transfer mode. RS RW E DB-DB7 Instruction write Dummy read RAM read Timing Diagram of 8-bit Parallel Bus Mode Data Transfer RS RW E DB-DB7 Upper Lower Upper Lower Upper Lower 4-bit 4-bit 4-bit 4-bit 4-bit 4-bit Instruction write Dummy read RAM read Timing Diagram of 4-bit Parallel Bus Mode Data Transfer V4. 25/49 28/8/8
ST792 Serial interface: ST792 is in serial interface mode when pulling down PSB pin. Two pins (SCLK and SID) are used to complete the data transfer. Only write data is available in the serial interface mode. When chip select (CS) is low, ST792 serial clock counter and serial data will be reset. Serial transfer counter is set to the first bit and data register is cleared. After CS is L, any further change on SID or SCLK is not allowed. It is recommended to keep SCLK at L and SID at the last status before set CS to L. For a minimal system with only one ST792 and one MPU, only SCLK and SID pins are necessary. CS pin should pull to high. ST792 s serial clock (SCLK) is asynchronous to the internal clock and is generated by MPU. When multiple instruction/data is transferred, the instruction execution time must be considered. MPU must wait till the previous instruction is finished and then send the next instruction. ST792 has no internal instruction buffer area. When starting a transmission, a start byte is required. It consists of 5 consecutive (sync character). Serial transfer counter will be reset and synchronized. Followed by 2-bit flag that indicates: read/write (RW) and register/data selected (RS) operation. Last 4 bits are filled by. After receiving the sync character, RW and RS bits, every 8 bits instruction/data will be separated into 2 groups. Higher 4 bits (DB7~DB4) will be placed in the first section followed by 4 s. And lower 4 bits (DB3~DB) will be placed in the second section followed by 4 s. CS SCLK 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 2 2 22 23 24 SID RW RS D7 D6 D5 D4 D3 D2 D D Synchronizing Bit string Higher data Lower data st byte 2 nd byte Timing Diagram of Serial Mode Data Transfer V4. 26/49 28/8/8
ST792 85 demo program for serial interface ;-------------------------------------------------------------- ; Write data from A into INSTRUCTION Register ;-------------------------------------------------------------- WRINS: SETB CS SETB SID ; SID = CLR SID ; SID = MOVBIT SID, A.7 ; SID = A.7 MOVBIT SID, A.6 ; SID = A.6 MOVBIT SID, A.5 ; SID = A.5 MOVBIT SID, A.4 ; SID = A.4 CLR SID ; SID = MOVBIT SID, A.3 ; SID = A.3 MOVBIT SID, A.2 ; SID = A.2 MOVBIT SID, A. ; SID = A. MOVBIT SID, A. ; SID = A. CLR SID ; SID = CLR CS CALL DLY8 RET ;------------------------------------------------- ; Write data from A into DATA Register ;------------------------------------------------- WRDATA: SETB CS SETB SID ; SID = CLR SID ; SID = SETB SID ; SID = CLR SID ; SID = MOVBIT SID, A.7 ; SID = A.7 MOVBIT SID, A.6 ; SID = A.6 MOVBIT SID, A.5 ; SID = A.5 MOVBIT SID, A.4 ; SID = A.4 CLR SID ; SID = MOVBIT SID, A.3 ; SID = A.3 MOVBIT SID, A.2 ; SID = A.2 MOVBIT SID, A. ; SID = A. MOVBIT SID, A. ; SID = A. CLR SID ; SID = CLR CS CALL DLY8 RET V4. 27/49 28/8/8
ST792 Application circuit for testing CGROM and HCGROM: We can use the function of CHECK SUM to check the CGROM is right or error. See the following notes: Useing IC Pad (Pin4 CLK, Pin5 TT, Pin6 TT2) to do the CHECK SUM function. The application circuit is at Page49. Timing Diagram for checking CGROM (TT=, TT2=) The ST792 check sum process: (DDRAM must be cleared by x before this process) In the first place: Resetting the internal counter (set TT and TT2 to Height) In the second place: Setting CGROM mode (set TT to Low, TT2 to Height). In the third place: CLK starts to count 655362 times. In the final place: Finishing the counting, read the last four bytes to CHECK SUM (reading only when the CLK is Height). ST792 check sum circuit: Data is available when CLK is height; if CLK is low then the data is always FFH. The last four bytes are Y, Y, Y2, and Y3. The fatest execution time is: tcyc=us (MHz at 5V). The table below is a comparing table of CGROM for different versions. Version (Font) CGROM Last four bytes Y Y Y2 Y3 Big5 (A) 38 88 CC F 2 GB (B) 9D 8 79 29 3 C FD 6F B5 85 V4. 28/49 28/8/8
ST792 Timing Diagram for checking HCGROM (TT=, TT2=) The ST792 check sum process: (DDRAM must be cleared by x before this process) In the first place: Resetting the internal counter (set TT and TT2 to Height) In the second place: Setting CGROM mode (set TT to Height, TT2 to Low). In the third place: CLK starts to count 242 times. In the final place: Finishing the counting, read the last four bytes to CHECK SUM (reading only when the CLK is Height). ST792 check sum circuit: Data is available when CLK is height; if CLK is low then the data is always FFH. The last four bytes are Y, Y, Y2, and Y3. The fatest execution time is: tcyc=2us (.5MHz at 5V). The table below is a comparing table of HCGROM for different versions. Version (Font) HCGROM last four bytes Y Y Y2 Y3 Big5 (A) B5 B5 2 GB (B) B5 B5 3 C B5 B5 V4. 29/49 28/8/8
ST792 Testing Step:. Clear whole DDRAM area by writing data x. 2. Composing TT and TT2 to make the Reset action, and clear the internal counter. 3. Selecting the test mode by setting TT and TT2 (CGROM or HCGROM). 4. After setp and setp2, entering some impulse signals through Pin4 (CLK). 5. Reading the CHECK SUM data through D to D7. 6. Comparing CHECK SUM with the Code Table (upper table) to check if the data is correct or not. TT TT2 No. of counts Status -- RESET 655362 CGROM 242 HGROM Test process flow: V4. 3/49 28/8/8
ST792 85 CGROM HCGROM illustrative test program ;* CHECK_ROM *; ;* Definition of outside Pin *; CLK REG P3.5 ; TT REG P3. ; TT2 REG P3. ; TT3 REG P3.2 ;CHECK CGROM FLAG TT4 REG P3.3 ;CHECK HCGROM FLAG TT5 REG P3.4 ;ERROR FLAG ;* Definition of internal RAM *; STACK EQU 6FH ; FUNC EQU 2H ; ; Interrupt set *; ORG H ; AJMP RESET ; ;* PROGRAM START *; RESET: MOV SP,#STACK ; MOV P,#FFH ; MOV P3,#FFH ; ;* CHECK_CGROM *; ;* Initial DDRAM *; CALL WRx ;Write x to whole DDRAM ;* Initial setting *; CGROM: SETB TT ; SETB TT2 ;TT,TT2 SET HIGH (RESET) CALL DELAY_US ;Wait Reset us CLR TT ;TT=LOW TT2=HIGH ( CHECK CGROM) SETB CLK ; CALL DELAY_US ; ;* start counter *; MOV R3,#9 ; CN4: MOV R2,# ;<---- CN3: MOV R,# ; CN2: CLR CLK ; SETB CLK ; DJNZ R,CN2 ; DJNZ R2,CN3 ; DJNZ R3,CN4 ; ; MOV R3,# ; CN5: MOV R2,#255 ; CN6: CLR CLK ; SETB CLK ; DJNZ R2,CN6 ; DJNZ R3,CN5 ; ; V4. 3/49 28/8/8
ST792 MOV R3,#63 ; CN7: MOV R2,#2 ; CN8: MOV R,#2 ; CN9: CLR CLK ; SETB CLK ; DJNZ R,CN9 ; DJNZ R2,CN8 ; DJNZ R3,CN7 ; CLR CLK ; SETB CLK ; CLR CLK ; SETB CLK ;<---- Counter 655356 ;-------------------------------; CLR CLK ;Counter 655357 SETB CLK ; MOV A,P ;A=Y CJNE A,#FDH,ERRORC ;COMPARE Y DATA CLR CLK ;Counter 655358 SETB CLK ; MOV A,P ;A=Y CJNE A,#6FH,ERRORC ;COMPARE Y DATA CLR CLK ;Counter 655359 SETB CLK ; MOV A,P ;A=Y2 CJNE A,#B5H,ERRORC ;COMPARE Y2 DATA CLR CLK ;Counter 65536 SETB CLK ; MOV A,P ;A=Y3 CJNE A,#85H,ERRORC ;COMPARE Y3 DATA CLR CLK ; CLR TT3 ;IF OK CLR TT3 CALL HCGROM ; ERRORC: ; CLR TT5 ;IF CGROM CHECK ERROR CLR TT5 ;---------------------------------------; ;* CHECK_HCGROM *; ;* Initial setting *; HCGROM: SETB TT ; SETB TT2 ;TT,TT2 SET HIGH (RESET) CALL DELAY_US ;Wait Reset us CLR TT2 ;TT2=LOW TT=HIGH ( CHECK HCGROM) SETB CLK ; CALL DELAY_US ; ;* start counter *; MOV R3,#9 ; N4: MOV R2,#32 ;<---- N3: MOV R,#32 ; N2: CLR CLK ; SETB CLK ; DJNZ R,N2 ; DJNZ R2,N3 ; DJNZ R3,N4 ; ; MOV R3,#32 ; N5: MOV R2,#3 ; N6: CLR CLK ; SETB CLK ; DJNZ R2,N6 ; DJNZ R3,N5 ; ; MOV R2,#3 ; V4. 32/49 28/8/8
ST792 N7: CLR CLK ; SETB CLK ; DJNZ R2,N7 ; ;---------------------------------------;<---- Counter 236 CLR CLK ;Counter 237 SETB CLK ; MOV A,P ;A=Y CJNE A,#B5H,ERROR ;COMPARE Y DATA CLR CLK ;Counter 238 SETB CLK ; MOV A,P ;A=Y CJNE A,#H,ERROR ;COMPARE Y DATA CLR CLK ;Counter 239 SETB CLK ; MOV A,P ;A=Y2 CJNE A,#B5H,ERROR ;COMPARE Y2 DATA CLR CLK ;Counter 24 SETB CLK ; MOV A,P ;A=Y3 CJNE A,#H,ERROR ;COMPARE Y3 DATA CLR CLK ; CLR TT4 ;IF HCGROM CHECK OK THEN CLR TT4 AJMP $ ; ERROR: ; CLR TT5 ;IF HCGROM CHECK ERROR THEN CLR TT5 AJMP $ ; ;* DELAY TIME US *; DELAY_US ; DEL_ MOV R6,#5 ; DEL_9 MOV R7,#3 ; DJNZ R7,$ ; DJNZ R6,DEL_9 ; RET ; END ; V4. 33/49 28/8/8
ST792 8-bit interface: POWER ON Wait time >4ms XRESET LOW HIGH Function set RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB X X X Wait time >us Function set RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB X X X Wait time >37uS Display ON/OFF control RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB D C B Wait time >us Display clear RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Wait time >ms Entry mode set RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB I/D S Initialization end V4. 34/49 28/8/8
ST792 4-bit interface: POWER ON Wait time > 4mS (for VDD stable) XRESET: LOW HIGH Function set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB X X X X X X X X X X X Wait time > μs Function set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB X X X X X X X X X X X Wait time > μs Display ON/OFF Control RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB D C B X X X X X X X X Wait time > μs Display Clear RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB X X X X X X X X Wait time > ms Entry Mode Set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB I/D S X X X X X X X X INITIALIZATION END V4. 35/49 28/8/8
ST792 Built in voltage booster V OUT Voltage Doubler Reference Voltage Vss VD2 Voltage Doubler Reference Voltage VD2 CAPM CAPP CAP2M V SS VOUT CAP2P CAP3M VOUT External reset timing VDD Tres XRESET Trw XRESET pulse width Trw us RESET start time Tres 5ns V4. 36/49 28/8/8
ST792 LCD driving wave form (/33 duty, /5 bias ) When oscillation frequency is 54KHZ, clock cycle time =.85us frame =.85us x 3 x 33 = 835us=8.3ms 3 clocks 2 3 4 33 2 3 4 33 2 3 4 33 COM V V V2 V3 V4 VSS COM2 V V V2 V3 V4 VSS COM33 V V V2 V3 V4 VSS SEGx off V V V2 V3 V4 VSS SEGx on V V V2 V3 V4 VSS frame V4. 37/49 28/8/8
ST792 Absolute Maximum Ratings Characteristics Symbol Value Power Supply Voltage V DD -.3V to +6.V LCD Driver Voltage V LCD or V -.3V to +7.V Voltage Doubler Output V OUT -.3V to +7.V Input Voltage V IN -.3V to V DD +.3V Operating Temperature T A -3 to + 85 Storage Temperature T STO -65 to + 5 DC Characteristics (T A = -3 ~ 85, V DD = 2.7 V - 4.5 V) Symbol Characteristics Test Condition Min. Typ. Max. Unit V DD Operating Voltage - 2.7-5.5 V V LCD LCD Voltage V-VSS 3. - 7 V I CC Power Supply Current f OSC = 53KHz, V DD =3.V Rf=8KΩ -.2.45 ma V IH Input High Voltage (Except OSC) -.7V DD - V DD V V IL Input Low Voltage (Except OSC) - -.3 -.6 V V IH2 Input High Voltage (OSC) - V DD - V DD V V IL2 Input Low Voltage (OSC) - - -. V V OH Output High Voltage (DB - DB7) I OH = -.ma.8v DD - V DD V V OL Output Low Voltage (DB - DB7) I OL =.ma - -. V V OH2 Output High Voltage (Except DB - DB7) I OH = -.4mA.8V DD - V DD V V OL2 Output Low Voltage (Except DB - DB7) I OL =.4mA - -.V DD V I LEAK Input Leakage Current V IN = V to V DD - - µa I PUP Pull Up MOS Current V DD = 3V 22 27 32 µa V4. 38/49 28/8/8
ST792 DC Characteristics (T A = -3 ~ 85, V DD = 4.5 V - 5.5 V) Symbol Characteristics Test Condition Min. Typ. Max. Unit V DD Operating Voltage - 4.5-5.5 V V LCD LCD Voltage V-V SS 3. - 7 V I CC Power Supply Current f OSC = 54KHz, V DD =5V Rf=33KΩ -.45.75 ma V IH Input High Voltage (Except OSC) -.7V DD - V DD V V IL Input Low Voltage (Except OSC) - -.3 -.6 V V IH2 Input High Voltage (OSC) - V DD - - V DD V V IL2 Input Low Voltage (OSC) - - -. V V OH Output High Voltage (DB - DB7) I OH = -.ma.8v DD - V DD V V OL Output Low Voltage (DB - DB7) I OL =.ma - -.4 V V OH2 Output High Voltage (Except DB - DB7) I OH = -.4mA.8V DD - V D D V V OL2 Output Low Voltage (Except DB - DB7) I OL =.4mA - -.V DD V I LEAK Input Leakage Current V IN = V to V DD - - µa I PUP Pull Up MOS Current V DD = 5V 75 8 85 µa V4. 39/49 28/8/8
ST792 AC Characteristics (T A = -3 ~ 85, V DD = 4.5V) Parallel Mode Interface Symbol Characteristics Test Condition Min. Typ. Max. Unit Internal Clock Operation f OSC OSC Frequency R = 33KΩ 48 54 6 KHz External Clock Operation f EX External Frequency - 48 54 6 KHz Duty Cycle - 45 5 55 % T R,T F Rise/Fall Time - - -.2 µs Write Mode (Writing data from MPU to ST792) T C Enable Cycle Time Pin E 2 - - ns T PW Enable Pulse Width Pin E 4 - - ns T R,T F Enable Rise/Fall Time Pin E - - 25 ns T AS Address Setup Time Pins: RS,RW,E - - ns T AH Address Hold Time Pins: RS,RW,E 2 - - ns T DSW Data Setup Time Pins: DB - DB7 4 - - ns T H Data Hold Time Pins: DB - DB7 2 - - ns Read Mode (Reading Data from ST792 to MPU) T C Enable Cycle Time Pin E 2 - - ns T PW Enable Pulse Width Pin E 4 - - ns T R,T F Enable Rise/Fall Time Pin E - - 25 ns T AS Address Setup Time Pins: RS,RW,E - - ns T AH Address Hold Time Pins: RS,RW,E 2 - - ns T DDR Data Delay Time Pins: DB - DB7 - - ns T H Data Hold Time Pins: DB - DB7 2 - - ns Interface Mode with LCD Driver(ST792) T CWH Clock Pulse with High Pins: CL, CL2 8 - - ns T CWL Clock Pulse with Low Pins: CL, CL2 8 - - ns T CST Clock Setup Time Pins: CL, CL2 5 - - ns T SU Data Setup Time Pin: D 3 - - ns T DH Data Hold Time Pin: D 3 - - ns T DM M Delay Time Pin: M - - ns V4. 4/49 28/8/8
ST792 AC Characteristics (T A = -3 ~ 85, V DD = 2.7V) Parallel Mode Interface Symbol Characteristics Test Condition Min. Typ. Max. Unit Internal Clock Operation f OSC OSC Frequency R = 8KΩ 47 53 59 KHz External Clock Operation f EX External Frequency - 47 53 59 KHz Duty Cycle - 45 5 55 % T R,T F Rise/Fall Time - - -.2 µs Write Mode (Writing data from MPU to ST792) T C Enable Cycle Time Pin E 8 - - ns T PW Enable Pulse Width Pin E 6 - - ns T R,T F Enable Rise/Fall Time Pin E - - 25 ns T AS Address Setup Time Pins: RS,RW,E - - ns T AH Address Hold Time Pins: RS,RW,E 2 - - ns T DSW Data Setup Time Pins: DB - DB7 4 - - ns T H Data Hold Time Pins: DB - DB7 2 - - ns Read Mode (Reading Data from ST792 to MPU) T C Enable Cycle Time Pin E 8 - - ns T PW Enable Pulse Width Pin E 32 - - ns T R,T F Enable Rise/Fall Time Pin E - - 25 ns T AS Address Setup Time Pins: RS,RW,E - - ns T AH Address Hold Time Pins: RS,RW,E 2 - - ns T DDR Data Delay Time Pins: DB - DB7 - - 26 ns T H Data Hold Time Pins: DB - DB7 2 - - ns Interface Mode with LCD Driver(ST792) T CWH Clock Pulse with High Pins: CL, CL2 8 - - ns T CWL Clock Pulse with Low Pins: CL, CL2 8 - - ns T CST Clock Setup Time Pins: CL, CL2 5 - - ns T SU Data Setup Time Pin: D 3 - - ns T DH Data Hold Time Pin: D 3 - - ns T DM M Delay Time Pin: M - - ns V4. 4/49 28/8/8
ST792 8-bit interface timing diagram MPU write data to ST792 RS VIH VIL TAS TAH R/W TPW TAH E DB-DB7 TR TDSW Valid data TH TC MPU read data from ST792 RS R/W E DB-DB7 VIH VIL TR TAS TDDR TPW Valid data TAH TAH TH TC V4. 42/49 28/8/8
ST792 AC Characteristics (T A = -3 ~ 85, V DD = 4.5V) Serial Mode Interface Symbol Characteristics Test Condition Min. Typ. Max. Unit Internal Clock Operation f OSC OSC Frequency R = 33KΩ 47 53 59 KHz External Clock Operation f EX External Frequency - 47 53 59 KHz Duty Cycle - 45 5 55 % T R,T F Rise/Fall Time - - -.2 µs T SCYC Serial clock cycle Pin E 4 - - ns SCLK high pulse T SHW width Pin E 2 - - ns T SLW SCLK low pulse width Pin E 2 - - ns T SDS SID data setup time Pins RW 4 - - ns T SDH SID data hold time Pins RW 4 - - ns T CSS CS setup time Pins RS 6 - - ns T CSH CS hold time Pins RS 6 - - ns AC Characteristics (T A = -3 ~ 85, V DD = 2.7V) Serial Mode Interface Symbol Characteristics Test Condition Min. Typ. Max. Unit Internal Clock Operation f OSC OSC Frequency R = 8KΩ 47 53 59 KHz External Clock Operation f EX External Frequency - 47 53 59 KHz Duty Cycle - 45 5 55 % T R,T F Rise/Fall Time - - -.2 µs T SCYC Serial clock cycle Pin E 6 - - ns T SHW SCLK high pulse width Pin E 3 - - ns T SLW SCLK low pulse width Pin E 3 - - ns T SDS SID data setup time Pins RW 4 - - ns T SDH SID data hold time Pins RW 4 - - ns T CSS CS setup time Pins RS 6 - - ns T CSH CS hold time Pins RS 6 - - ns V4. 43/49 28/8/8
ST792 Serial interface timing diagram MPU write data to ST792 CS TCSS TCSH TSCYC SCLK Tf TSLW TSDS Tr TSHW TSDH SID Valid data V4. 44/49 28/8/8
ST792 I/O pin diagram Input PAD: E (No Pull-up) Input PAD: RS, RW (with Pull-up) Output PAD: CL, CL2, M, D Enable DATA I/O PAD: DB DB7 V4. 45/49 28/8/8
ST792 V4. 46/49 28/8/8 Application circuit : LCD : 32-COM x 6-SEG LCD Voltage : VCC 2 3 4 5 6 A B C D 6 5 4 3 2 D C B A Title Number Revision Size B Date: -Mar-2 Sheet of File: D:\Buffer-2\792V.DDB Drawn By: V V 2 V2 3 VXA 4 VXB 5 VXC 6 V3 7 V4 8 VSS 9 VDD XRESET CL 2 CL2 3 VDD 4 M 5 DOUT 6 RS 7 RW 8 E 9 VSS 2 OSC 2 OSC2 22 PSB 23 D 24 D 25 D2 26 D3 27 D4 28 D5 29 D6 3 D7 3 XOFF 32 VOUT 33 CAP3M 34 CAPP 35 CAPM 36 CAP2P 37 CAP2M 38 VD2 39 C 4 C2 4 C3 42 C4 43 C5 44 C6 45 C7 46 C8 47 C9 48 C 49 C 5 C2 5 C3 52 C4 53 C5 54 C6 55 C7 56 C8 57 C9 58 C2 59 C2 6 C22 6 C23 62 C24 63 C25 64 C26 65 C27 66 C28 67 C29 68 C3 69 C3 7 C32 7 C33 72 S64 73 S63 74 S62 75 S6 76 S6 77 S59 78 S58 79 S57 8 S56 8 S55 82 S54 83 S53 84 S52 85 S5 86 S5 87 S49 88 S48 89 S47 9 S46 9 S45 92 S44 93 S43 94 S42 95 S4 96 S4 97 S39 98 S38 99 S37 S36 S35 2 S34 3 S33 4 S32 5 S3 6 S3 7 S29 8 S28 9 S27 S26 S25 2 S24 3 S23 4 S22 5 S2 6 S2 7 S9 8 S8 9 S7 2 S6 2 S5 22 S4 23 S3 24 S2 25 S 26 S 27 S9 28 S8 29 S7 3 S6 3 S5 32 S4 33 S3 34 S2 35 S 36 U ST792 S5 S5 2 S52 3 S53 4 S54 5 S55 6 S56 7 S57 8 S58 9 S59 S6 S6 2 S62 3 S63 4 S64 5 S65 6 S66 7 S67 8 S68 9 S69 2 S7 2 S7 22 S72 23 S73 24 S74 25 S75 26 S76 27 S77 28 S78 29 S79 3 S8 3 S8 32 S82 33 S83 34 S84 35 S85 36 S86 37 S87 38 S88 39 S89 4 S9 4 S9 42 S92 43 S93 44 S94 45 S95 46 S96 47 S48 48 S47 49 S46 5 S45 5 S44 52 S43 53 S42 54 S4 55 S4 56 S39 57 S38 58 S37 59 S36 6 S35 6 S34 62 S33 63 S32 64 S3 65 S3 66 S29 67 S28 68 S27 69 S26 7 S25 7 S24 72 S23 73 S22 74 S2 75 S2 76 S9 77 S8 78 S7 79 S6 8 S5 8 S4 82 S3 83 S2 84 S 85 S 86 S9 87 S8 88 S7 89 S6 9 S5 9 S4 92 S3 93 S2 94 S 95 V 96 V2 97 V3 98 VSS 99 VDD CL SHL 2 SHL2 3 CL2 4 DL 5 DR 6 DL2 7 DR2 8 M 9 S49 U2 ST792 C8 C7 2 C6 3 C5 4 C4 5 C3 6 C2 7 C 8 S 9 S2 S3 S4 2 S5 3 S6 4 S7 5 S8 6 S9 7 S 8 S 9 S2 2 S3 2 S4 22 S5 23 S6 24 S7 25 S8 26 S9 27 S2 28 S4 29 S42 3 S43 3 S44 32 S45 33 S46 34 S47 35 S48 36 S49 37 S5 38 S5 39 S52 4 S53 4 S54 42 S55 43 S56 44 S57 45 S58 46 S59 47 S6 48 S8 49 S82 5 S83 5 S84 52 S85 53 S86 54 S87 55 S88 56 S89 57 S9 58 S9 59 S92 6 S93 6 S94 62 S95 63 S96 64 S97 65 S98 66 S99 67 S 68 S2 69 S22 7 S23 7 S24 72 S25 73 S26 74 S27 75 S28 76 S29 77 S3 78 S3 79 S32 8 S33 8 S34 82 S35 83 S36 84 S37 85 S38 86 S39 87 S4 88 C7 89 C8 9 C9 9 C2 92 C2 93 C22 94 C23 95 C24 96 C9 97 C 98 C 99 C2 C3 C4 2 C5 3 C6 4 S2 5 S22 6 S23 7 S24 8 S25 9 S26 S27 S28 2 S29 3 S3 4 S3 5 S32 6 S33 7 S34 8 S35 9 S36 2 S37 2 S38 22 S39 23 S4 24 S6 25 S62 26 S63 27 S64 28 S65 29 S66 3 S67 3 S68 32 S69 33 S7 34 S7 35 S72 36 S73 37 S74 38 S75 39 S76 4 S77 4 S78 42 S79 43 S8 44 S 45 S2 46 S3 47 S4 48 S5 49 S6 5 S7 5 S8 52 S9 53 S 54 S 55 S2 56 S3 57 S4 58 S5 59 S6 6 S7 6 S8 62 S9 63 S2 64 S4 65 S42 66 S43 67 S44 68 S45 69 S46 7 S47 7 S48 72 S49 73 S5 74 S5 75 S52 76 S53 77 S54 78 S55 79 S56 8 S57 8 S58 82 S59 83 S6 84 C32 85 C3 86 C3 87 C29 88 C28 89 C27 9 C26 9 C25 92 L WDG63P C 4 2 3 4 5 6 7 8 9 2 3 4 5 6 JP HEADER 6 2 JA CON2 2 JK CON2 2 3 J CON3 R 4.7K R2 4.7K R3 2.2K R4 4.7K R5 4.7K R6 33K R7 2K R9 33 R8 33 VCC VCC VCC VCC 2 JP2 HEADER 2 VCC VCC C C2 C3 C4 C5 C6 C7 C8 C9 C C C2 C3 C4 C5 C6 C7 C8 C9 C2 C2 C22 C23 C24 C25 C26 C27 C28 C29 C3 C3 C32 S39 S4 S4 S42 S43 S44 S45 S46 S47 S48 S49 S5 S5 S52 S53 S54 S55 S56 S57 S58 S59 S6 S6 S62 S63 S64 S S2 S3 S4 S5 S6 S7 S8 S9 S S S2 S3 S4 S5 S6 S7 S8 S9 S2 S2 S22 S23 S24 S25 S26 S27 S28 S29 S3 S3 S32 S33 S34 S35 S36 S37 S38 S65 S66 S67 S68 S69 S7 S7 S72 S73 S74 S75 S76 S77 S78 S79 S8 S8 S82 S83 S84 S85 S86 S87 S88 S89 S9 S9 S92 S93 S94 S95 S96 S97 S98 S99 S S S2 S3 S4 S5 S6 S7 S8 S9 S S S2 S3 S4 S5 S6 S7 S8 S9 S2 S2 S22 S23 S24 S25 S26 S27 S28 S29 S3 S3 S32 S33 S34 S35 S36 S37 S38 S39 S4 S4 S42 S43 S44 S45 S46 S47 S48 S49 S5 S5 S52 S53 S54 S55 S56 S57 S58 S59 S6 C25 C26 C27 C28 C29 C3 C3 C32 C C2 C3 C4 C5 C6 C7 C8 C9 C C C2 C3 C4 C5 C6 C7 C8 C9 C2 C2 C22 C23 C24 S S2 S3 S4 S5 S6 S7 S8 S9 S S S2 S3 S4 S5 S6 S7 S8 S9 S2 S2 S22 S23 S24 S25 S26 S27 S28 S29 S3 S3 S32 S33 S34 S35 S36 S37 S38 S39 S4 S4 S42 S43 S44 S45 S46 S47 S48 S49 S5 S5 S52 S53 S54 S55 S56 S57 S58 S59 S6 S6 S62 S63 S64 S65 S66 S67 S68 S69 S7 S7 S72 S73 S74 S75 S76 S77 S78 S79 S8 S8 S82 S83 S84 S85 S86 S87 S88 S89 S9 S9 S92 S93 S94 S95 S96 S97 S98 S99 S S S2 S3 S4 S5 S6 S7 S8 S9 S S S2 S3 S4 S5 S6 S7 S8 S9 S2 S2 S22 S23 S24 S25 S26 S27 S28 S29 S3 S3 S32 S33 S34 S35 S36 S37 S38 S39 S4 S4 S42 S43 S44 S45 S46 S47 S48 S49 S5 S5 S52 S53 S54 S55 S56 S57 S58 S59 S6 Paul Yung.2 Sitronix ST792 LCM R K CLK TT TT2
ST792 V4. 47/49 28/8/8 Application circuit 2: LCD : 32-COM x 6-SEG LCD Voltage : VCC x 2 (Voltage doubler is used). *V LCD (V), V OUT and V CAP3M should not over 7V. 2 3 4 5 6 A B C D 6 5 4 3 2 D C B A Title Number Revision Size B Date: 7-Aug-2 Sheet of File: D:\adom\Documents\sch\792_B~3.DDB Drawn By: V V 2 V2 3 VXA 4 VXB 5 VXC 6 V3 7 V4 8 VSS 9 VDD XRESET CL 2 CL2 3 VDD 4 M 5 DOUT 6 RS 7 RW 8 E 9 VSS 2 OSC 2 OSC2 22 PSB 23 D 24 D 25 D2 26 D3 27 D4 28 D5 29 D6 3 D7 3 XOFF 32 VOUT 33 CAP3M 34 CAPP 35 CAPM 36 CAP2P 37 CAP2M 38 VD2 39 C 4 C2 4 C3 42 C4 43 C5 44 C6 45 C7 46 C8 47 C9 48 C 49 C 5 C2 5 C3 52 C4 53 C5 54 C6 55 C7 56 C8 57 C9 58 C2 59 C2 6 C22 6 C23 62 C24 63 C25 64 C26 65 C27 66 C28 67 C29 68 C3 69 C3 7 C32 7 C33 72 S64 73 S63 74 S62 75 S6 76 S6 77 S59 78 S58 79 S57 8 S56 8 S55 82 S54 83 S53 84 S52 85 S5 86 S5 87 S49 88 S48 89 S47 9 S46 9 S45 92 S44 93 S43 94 S42 95 S4 96 S4 97 S39 98 S38 99 S37 S36 S35 2 S34 3 S33 4 S32 5 S3 6 S3 7 S29 8 S28 9 S27 S26 S25 2 S24 3 S23 4 S22 5 S2 6 S2 7 S9 8 S8 9 S7 2 S6 2 S5 22 S4 23 S3 24 S2 25 S 26 S 27 S9 28 S8 29 S7 3 S6 3 S5 32 S4 33 S3 34 S2 35 S 36 U ST792 S5 S5 2 S52 3 S53 4 S54 5 S55 6 S56 7 S57 8 S58 9 S59 S6 S6 2 S62 3 S63 4 S64 5 S65 6 S66 7 S67 8 S68 9 S69 2 S7 2 S7 22 S72 23 S73 24 S74 25 S75 26 S76 27 S77 28 S78 29 S79 3 S8 3 S8 32 S82 33 S83 34 S84 35 S85 36 S86 37 S87 38 S88 39 S89 4 S9 4 S9 42 S92 43 S93 44 S94 45 S95 46 S96 47 S48 48 S47 49 S46 5 S45 5 S44 52 S43 53 S42 54 S4 55 S4 56 S39 57 S38 58 S37 59 S36 6 S35 6 S34 62 S33 63 S32 64 S3 65 S3 66 S29 67 S28 68 S27 69 S26 7 S25 7 S24 72 S23 73 S22 74 S2 75 S2 76 S9 77 S8 78 S7 79 S6 8 S5 8 S4 82 S3 83 S2 84 S 85 S 86 S9 87 S8 88 S7 89 S6 9 S5 9 S4 92 S3 93 S2 94 S 95 V 96 V2 97 V3 98 VSS 99 VDD CL SHL 2 SHL2 3 CL2 4 DL 5 DR 6 DL2 7 DR2 8 M 9 S49 U2 ST792 C8 C7 2 C6 3 C5 4 C4 5 C3 6 C2 7 C 8 S 9 S2 S3 S4 2 S5 3 S6 4 S7 5 S8 6 S9 7 S 8 S 9 S2 2 S3 2 S4 22 S5 23 S6 24 S7 25 S8 26 S9 27 S2 28 S4 29 S42 3 S43 3 S44 32 S45 33 S46 34 S47 35 S48 36 S49 37 S5 38 S5 39 S52 4 S53 4 S54 42 S55 43 S56 44 S57 45 S58 46 S59 47 S6 48 S8 49 S82 5 S83 5 S84 52 S85 53 S86 54 S87 55 S88 56 S89 57 S9 58 S9 59 S92 6 S93 6 S94 62 S95 63 S96 64 S97 65 S98 66 S99 67 S 68 S2 69 S22 7 S23 7 S24 72 S25 73 S26 74 S27 75 S28 76 S29 77 S3 78 S3 79 S32 8 S33 8 S34 82 S35 83 S36 84 S37 85 S38 86 S39 87 S4 88 C7 89 C8 9 C9 9 C2 92 C2 93 C22 94 C23 95 C24 96 C9 97 C 98 C 99 C2 C3 C4 2 C5 3 C6 4 S2 5 S22 6 S23 7 S24 8 S25 9 S26 S27 S28 2 S29 3 S3 4 S3 5 S32 6 S33 7 S34 8 S35 9 S36 2 S37 2 S38 22 S39 23 S4 24 S6 25 S62 26 S63 27 S64 28 S65 29 S66 3 S67 3 S68 32 S69 33 S7 34 S7 35 S72 36 S73 37 S74 38 S75 39 S76 4 S77 4 S78 42 S79 43 S8 44 S 45 S2 46 S3 47 S4 48 S5 49 S6 5 S7 5 S8 52 S9 53 S 54 S 55 S2 56 S3 57 S4 58 S5 59 S6 6 S7 6 S8 62 S9 63 S2 64 S4 65 S42 66 S43 67 S44 68 S45 69 S46 7 S47 7 S48 72 S49 73 S5 74 S5 75 S52 76 S53 77 S54 78 S55 79 S56 8 S57 8 S58 82 S59 83 S6 84 C32 85 C3 86 C3 87 C29 88 C28 89 C27 9 C26 9 C25 92 L WDG63P + C3 4.7u + C2 4.7u C 4 2 3 4 5 6 7 8 9 2 3 4 5 6 JP HEADER 6 2 JA CON2 2 JK CON2 2 3 J CON3 R 4.7K R2 4.7K R3 2.2K R4 4.7K R5 4.7K R6 33K R7 2K R9 33 R8 33 VCC VCC VCC 2 JP2 HEADER 2 VCC VCC C C2 C3 C4 C5 C6 C7 C8 C9 C C C2 C3 C4 C5 C6 C7 C8 C9 C2 C2 C22 C23 C24 C25 C26 C27 C28 C29 C3 C3 C32 S39 S4 S4 S42 S43 S44 S45 S46 S47 S48 S49 S5 S5 S52 S53 S54 S55 S56 S57 S58 S59 S6 S6 S62 S63 S64 S S2 S3 S4 S5 S6 S7 S8 S9 S S S2 S3 S4 S5 S6 S7 S8 S9 S2 S2 S22 S23 S24 S25 S26 S27 S28 S29 S3 S3 S32 S33 S34 S35 S36 S37 S38 S65 S66 S67 S68 S69 S7 S7 S72 S73 S74 S75 S76 S77 S78 S79 S8 S8 S82 S83 S84 S85 S86 S87 S88 S89 S9 S9 S92 S93 S94 S95 S96 S97 S98 S99 S S S2 S3 S4 S5 S6 S7 S8 S9 S S S2 S3 S4 S5 S6 S7 S8 S9 S2 S2 S22 S23 S24 S25 S26 S27 S28 S29 S3 S3 S32 S33 S34 S35 S36 S37 S38 S39 S4 S4 S42 S43 S44 S45 S46 S47 S48 S49 S5 S5 S52 S53 S54 S55 S56 S57 S58 S59 S6 C25 C26 C27 C28 C29 C3 C3 C32 C C2 C3 C4 C5 C6 C7 C8 C9 C C C2 C3 C4 C5 C6 C7 C8 C9 C2 C2 C22 C23 C24 S S2 S3 S4 S5 S6 S7 S8 S9 S S S2 S3 S4 S5 S6 S7 S8 S9 S2 S2 S22 S23 S24 S25 S26 S27 S28 S29 S3 S3 S32 S33 S34 S35 S36 S37 S38 S39 S4 S4 S42 S43 S44 S45 S46 S47 S48 S49 S5 S5 S52 S53 S54 S55 S56 S57 S58 S59 S6 S6 S62 S63 S64 S65 S66 S67 S68 S69 S7 S7 S72 S73 S74 S75 S76 S77 S78 S79 S8 S8 S82 S83 S84 S85 S86 S87 S88 S89 S9 S9 S92 S93 S94 S95 S96 S97 S98 S99 S S S2 S3 S4 S5 S6 S7 S8 S9 S S S2 S3 S4 S5 S6 S7 S8 S9 S2 S2 S22 S23 S24 S25 S26 S27 S28 S29 S3 S3 S32 S33 S34 S35 S36 S37 S38 S39 S4 S4 S42 S43 S44 S45 S46 S47 S48 S49 S5 S5 S52 S53 S54 S55 S56 S57 S58 S59 S6 Paul Yang.4 Sitronix ST792 LCM (Booster) R K CLK TT TT2
ST792 Application circuit 3: LCD : 2Line 6Chinese Word (32-COM x 256-SEG) Com -32 ST792 DB-DB7 To MPU Seg -64 Dout VDD VSS CL2 CL M V V V2 V3 V4 Vcc(+5V/+3V) VR DL VDD SHL SHL2 VSS V Dot Matrix LCD Panel Seg -96 ST792 DR2 DL2 DR CL CL2 M V2 V3 Regsister Regsister Regsister DL VDD Seg -96 SHL SHL2 VSS V ST792 V2 V3 Regsister Regsister VSS Note:Regsister=2.2K~K ohm VR=K~3Kohm DR2 DL2 DR CL CL2 M V4. 48/49 28/8/8
R R2 R2 R2 ST792 Application circuit for testing CGROM and HCGROM: V4. 49/49 28/8/8