Capacitor Bank Switching with Vacuum Circuit Breakers

Technical collection Capacitor Bank Switching with Vacuum Circuit Breakers 2008 - Conferences publications H. Schellekens

2008 China International Conference on Electricity Distribution (CICED 2008) 1 Capacitor Bank Switching with Vacuum Circuit Breakers Hans Schellekens Schneider Electric, Power SBU, Medium Voltage Development, Usine 38V, ZAC Champ Saint-Ange, Varces, France Abstract: After interruption of a capacitive current sometimes Non Sustained Disruptive Discharges (NSDDs) are observed when using vacuum circuit breakers. According to network calculations, NSDDs generate significant over-voltage on the terminal of the capacitor bank to ground and across the circuit breaker (CB) terminals. In a full scale experiment at 12kV on an 8Mvar capacitor bank artificial NSDDs are produced using a Triggered Vacuum Gap. The over-voltage depends on the momentary voltage difference across the breaker and, hence, varies with the phase angle. The over-voltage on the terminal of the capacitor bank to ground varies from 1.5 to 4.2 pu, and to maximum 5.2 pu. across the CB terminals. The effectiveness of surge arrestors on the limitation of the over-voltages is measured. The over-voltages are limited to 2.2 pu. on the terminals of the capacitor bank to ground and 3.2 pu. across the CB terminals. A single surge arrestor on the neutral point of the capacitor bank yields the same level of protection and, therefore, is a cost effective alternative. An application guide for switchgear and arrestors is presented. 1. INTRODUCTION The capacitive current switching duty is characterised by frequent, day to day or hour by hour, switching of low to moderate currents in industrial or public networks, and by a low rate of rise of recovery voltage. Modern circuit breakers (CB s) which claim a long mechanical but also electrical life without maintenance seem to be best adapted to this switching duty [1,2,3]. Yet the behaviour of vacuum CB s is rather different from that of gas CB s. Today, the circuit breaker envisioned for capacitor bank switching is either a vacuum or SF6 circuit breaker or a vacuum or SF6 contactor. All these devices are known for their long service life. The circuit breaker offers a protection against short circuit currents with an electrical life between 10.000 and 30.000 operations at nominal current. Contactors offer an electrical life up to 1 million operations depending on load conditions. SF6 CB s, in the past referred to as restrike free breakers, are according to the new IEC62271-100 class C2 breakers with proven very low restrike probability [4]. Field experience indicates that the restrike probability even for the electrically very stressed 36 kv networks is lower than 1/50.000. For vacuum CB s, the physical processes during the capacitive switching duty have been studied by [5]. They found that the pre-ignition at contact closing and the subsequent inrush current heavily eroded the contacts leading to detached particles. These particles cause late breakdowns which appear as NSDDs 1. Breakdown frequencies of typically 3/1000 where found under the experimental conditions studied. The probability of breakdown depends on the dielectric conception or contact stroke of the vacuum interrupter. So for the same voltage rating different designs lead to different probabilities of occurrence of NSDD. Fig. 1 shows the experimentally found relation between dielectric conception, based on contact gap, and the probability of a NSDD during an operation. It shows that a minimum contact distance of 16 mm is necessary to reduce this probability below 1/500. The overvoltage produced by a NSDD differs notably from the overvoltage produced by a restrike. A restrike can generate an overvoltage of 3 pu. between the terminals of the capacitor bank, whereas a NSDD causes a sudden voltage shift of the neutral capacitor bank voltage, which leaves the voltage across the capacitor unchanged, but creates an overvoltage between 1.5 and 5 pu. on the terminal of capacitor bank to ground and between 2.5 and 6 pu. across the CB terminals. Due to this high overvoltage a second NSDD in the adjacent phases becomes more likely. When two NSDDs occur simultaneously, the phenomenon turns into a restrike. Typically, a vacuum CB with a contact gap of about 16 mm has a probability of about 1 NSDD or non-sustained disruptive discharge [7] is a disruptive discharge associated with current interruption that does not result in the resumption of power frequency current or, in the case of capacitive current interruption does not result in current in the main load circuit.

2 2008 China International Conference on Electricity Distribution (CICED 2008)) 1/500 for producing a NSDD and belongs to the class C2 with proven very low restrike probability. Fig.1 : Experimentally found dependence between probability of a NSDD and nominal contact stroke of vacuum interrupter. Due to the rare occurrence and the random nature of the phenomenon, the relation between NSDD and overvoltage is not evident. Therefore in this paper this question is addressed in section II using a numerical network simulation. By this the worst case overvoltage for different voltage levels is determined. Then in section III an experiment designed to verify the simulation results is shown. Here the NSDD is created artificially, which permits to measure the influence of phase angle and network parameters. A good understanding of the origin of the overvoltage enables the definition of protective measures adapted to the switchgear and capacitor bank. In section IV protection schemes based on surge arrestors are tested and compared on their effectiveness. Finally in section V the results are discussed and an application guideline is presented for the choice of switchgear and arrestor. 2. ORIGIN OF OVERVOLTAGES The source side of the network is represented by: - a generator with a driving voltage of U - a short circuit impedance of value Ls - a TRV network as defined by IEC for short circuit conditions - a capacitor Cp to account for parallel feeders The load side of the network is represented by: - a 8Mvar capacitor bank with floating neutral - single phase cables between CB and the bank. The load and the source side of the network are connected to each other by the CB. The CB is treated as an ideal breaker with a NSDD some time after current interruption. The moment of NSDD has been chosen in order to create the worst possible case. The CB is allowed to recover immediately at the first occurring current zero. At a NSDD, on the R phase for the case illustrated by Fig. 2, the voltage across the breaker moves as a travelling wave through the line impedance towards the capacitor bank. The capacitor bank being a high frequency short circuit allows the wave to pass on to the neutral point of the bank. At the neutral point the wave splits itself and continues its propagation in the neighbouring phases towards the healthy CB poles. These healthy poles are in fact open terminals for the incoming wave causing it to reflect by doubling the voltage. After reflection the wave travels back to the failing CB pole. Here it creates a current zero passage on which the breaker can interrupt. The frequency of this current is typically of the order of 100 khz for cable connected capacitor banks. Fig. 3 shows the voltage swing on the bank terminals with respect to ground. Note that 2.1 Numerical simulation The simplified electrical circuit, Fig. 2, will be used here to simulate the phenomena associated with a NSDD; the NSDD is simulated as a temporary loss of dielectric strength in the vacuum interrupter of a vacuum CB. Fig. 3 : The voltage on all 3 capacitor bank terminals during current interruption (at 0.1s) followed by a NSDD (at 0.13s) in R phase in a 12kV network. Fig. 2 : Electric circuit used to calculate overvoltage on capacitor bank during a NSDD. TVG see section III. - For each of the three bank terminals the voltage jumps to a new value, which means that the neutral point of the bank attains also a different value. - The voltage difference between terminals remains

2008 China International Conference on Electricity Distribution (CICED 2008) 3 unchanged. The capacitors themselves are not stressed by the breakdown. - The maximum terminal voltage to earth attains a high value (see table I). This is a dc voltage, so all parts of the installation are stressed during a long period. - The CB is stressed by the composed voltage of network voltage and capacitor bank terminal voltage. - The capacity of the bank itself is of no significance for the phenomenon. Table 1: Compilation of voltages associated with capacitor bank switching for nominal network voltages U m U S U C-bank U VCB BIL Power frequency kvrms kvrms kv kv kv kvrms 12 10 47 55 75 28 24 20 93 110 125 50 36 30 140 164 170 70 2.2. Identification of zones at risk In table I the maximum possible overvoltage produced by a NSDD is shown for three commonly used classes of network voltages. For each voltage class column 2 gives Us the nominal network voltage. Column 3 gives the maximum overvoltage on the capacitor bank terminal to ground and column 4 the maximum overvoltage across the CB terminals. For reference the BIL and power frequency withstand voltages of the equipment are given. For all three voltage classes both overvoltages exceed the peak value of the power frequency withstand voltage. For the CB the overvoltage comes very close to the rated BIL voltage for 36 kv class networks. 2. EXPERIMENTAL VERIFICATION 3.1 Test procedure The objective was to create in a reproducible way NSDD type breakdowns in a capacitive current interruption test. This allowed to minimize the number of tests to obtain the desired NSDD. NSDDs do not occur frequently and are therefore difficult to reproduce. A triggered vacuum gap (TVG) parallel to the R-phase of the VCB is used to create an artificial NSDD in a controllable way. A separate experiment confirmed that the TVG was able to interrupt high frequency currents of, for instance, 300A at 100kHz and 10 A at 900 khz at the first current zero. Hence, the duration of the artificial NSDD is determined by the circuit topology and only one half cycle of high frequency current will pass through the TVG. Numerical modelling showed that this will lead to the highest possible overvoltage. Using the TVG provided a measurement window with high frequency sampling centred at the time of breakdown allowing precise measurements to be made. Full scale tests are performed in a direct test circuit fed by a generator 2000 MVA at 12 kv with short circuit current limited at 14 ka. The capacitive load was a 8 Mvar capacitor bank; nominal current of 430 A. The detailed characteristics of the test circuit are given in Fig. 4 and table II. Fig. 4 : 3-phase test circuit with generator and 8 Mvar capacitor bank. 3.2 Test results Fig. 5a shows an oscillogram of a normal interruption with NSDD. The first phase to interrupt, R, creates a dc voltage on the capacitor bank terminal of 1.5 pu. Then 30 milliseconds after current interruption a NSDD is generated in phase R at a maximum voltage difference across the CB. At this moment the voltages on all C-bank terminals change suddenly and settle to a new constant value. The highest overvoltage is found in phase T. The instant of occurrence of the NSDD was varied by firing the TVG at a predetermined

4 2008 China International Conference on Electricity Distribution (CICED 2008)) moment to see the influence of the phase angle on the nature and the value of the over-voltage. The waveform of the overvoltage is a dc voltage and is the same for all tested phase angles. the most severe one, the experiment was repeated by keeping the first phase to clear in phase R and generating the NSDD in phase T. The highest overvoltage is now found in phase R. The instant of occurrence of the NSDD was varied by firing the TVG at a predetermined moment to see the influence of the phase angle on the nature and the value of the over-voltage. The waveform of the overvoltage is a dc voltage and is the same for all tested phase angles. Fig. 6b shows the measured voltage on the capacitor bank terminal in phase R to ground after the NSDD in phase T. Before the NSDD the voltage is about 1.5 pu. The voltage jump is between 0 and 2.5 pu. resulting into an over-voltage of maximum 4.0 pu. The height of the overvoltage varies harmonically with the phase angle. Fig.5a: Normal interruption of capacitive current followed by NSDD in R phase after 30 ms. Fig.5b: As Fig. 5a Surge arrestor in phase T limits the overvoltage. For each phase (R, S, T). Red : Source side voltage on CB. Green : Load side voltage on CB and capacitor bank terminal. Blue : Current through CB. Time scale: 1ms/div. Fig. 6a shows the measured voltage on the capacitor bank terminal in phase T to ground after the NSDD in phase R. Before the NSDD the voltage is about 0.89 pu. The voltage jump is between 0.6 and 3.2 pu. leading to an over-voltage of maximum 4.1 pu. The height of the overvoltage varies harmonically with the phase angle. Fig. 6a : Variation of over-voltage in phase T expressed in pu due to instant of occurrence (phase angle) of the NSDD in 1 st phase R to interrupt. In order to investigate whether the above condition is Fig. 6b : Variation of over-voltage in phase R expressed in pu due to instant of occurrence (phase angle) of the NSDD in 2 nd phase T to interrupt. Note that the over-voltage is the addition of the original capacitor bank voltage after current interruption and a voltage jump due to the NSDD. The amplitude of the voltage jump depends on two factors : the voltage across the breaker at the instant of breakdown, which varies with time or phase angle, and which is maximum 2.5 pu. (see Fig. 5a). an amplitude multiplication K-factor (section IIIC) The voltage difference at breakdown is transmitted integrally to the neighbouring phases as predicted by the numerical simulation. Except for a reduced amplitude factor the behaviour found is identical to the simulation. Moreover, the most severe overvoltage is produced by a NSDD in the first phase to interrupt at the moment of the largest voltage difference across the CB. 3.3 Influence of TRV circuit The influence of the TRV circuit on the high frequency behaviour of the breakdown has been studied with the following circuits:

2008 China International Conference on Electricity Distribution (CICED 2008) 5 TRV-1 : The standard TRV circuit composed of 2 branches see Fig. 2. TRV-2 : No TRV circuit; only stray capacitance between Generator and CB. TABLE III : Influence TRV circuit on peak value of overvoltage TRV-1 TRV-2 Voltage jump K-theoretical 2 2 K-Immediate 1.6 1.7 K-Late 1.3 1.6 Damping time 16.5µs 13.5µs Frequency NSDD current 150 khz 28 khz Current 28 A 6 A Results are shown in table III. The voltage jump after breakdown can be characterised by : A peak voltage immediately after the NSDD: with K factor : K-immediate. A dc voltage after a transition period: K-late. The transition is characterised by a time constant here called damping time. The frequency of the NSDD current. Fig. 7 shows an oscillogram of the voltage on both sides of the CB during the NSDD for TRV-2 circuit. During the NSDD, between 12 and 30 µsec, both voltages are identical as an arc in the CB allows for current to pass from the source side to the load side. Due to the small TRV capacitance, the source side voltage collapses at 12 µsec and joins the load side voltage. During the current flow the voltage makes an oscillation around the driving voltage (the source voltage before the NSDD). When this reaches a new maximum at 30 µsec the current passes through zero and interruption takes place. After interruption, the source voltage is subject to the Fig. 7 Zoom at voltage behaviour at NSDD in R phase with TRV-2. Green (1) : Load side voltage on CB and capacitor bank terminal. Red (2) : Source side voltage on CB. Time scale 10µs/div. TRV generated by the driving voltage of the generator and the TRV circuit. The load side voltage settles to a new dc voltage level. Numerical simulation suggests voltage doubling with a K-factor equal to 2. Therefore the reduced value of K-immediate is attributed to damping of the high frequency current at NSDD. 4. PROTECTION BY SURGE ARRESTORS Arrestors are commonly proposed as means to protect the capacitor bank against excessive overvoltages due to restrikes [6]. In such a case the overvoltage rise-time is of the order of milliseconds. Yet in case of an NSDD the overvoltage rise-time is only several microseconds. In order to verify the effectiveness of the surge arrestor the following two cases are investigated. 4.1 Surge arrestors on all three phases to ground Test conditions are similar as under section IIIA but with surge arrestors on the load side of the CB to ground. On initiation of a NSDD in phase R, the highest overvoltage of 2.2 pu. was in phase T due to immediate limitation of the overvoltage by the surge arrestor in phase T; the associated oscillogram is shown in Fig. 5b. A significant current flows through the surge arrestor: 890 A during 1 ms; representing an energy of about 8 kjoule. This current is determined by : 1. The series impedance of two branches R and T of the capacitor bank and the series inductance of phase R and the resistance to ground of the generator. 2. The voltage difference across the capacitor prior to breakdown minus the voltage of the arrestor. Notice, that during the limitation of an overvoltage due to a NSDD only one surge arrestor is conductive and dissipates the energy. Due to the random nature of current interruption the maximum overvoltage can be in any of the three phases. Therefore, surge arrestors have to be installed on all three phases. 4.2 Surge arrestor on neutral to ground Test conditions are similar as under section IIIA but with a single surge arrestor on the neutral point of the capacitor bank. If a NSDD was initiated in phase R, the highest overvoltage of 2.1 pu. was in phase T due to immediate limitation of the overvoltage by the surge arrestor. A significant current flows through the surge arrestor: 575 A during 2.5 ms; representing an energy of about 13 kjoule. This current is determined by 1. The series impedance of one branch of the capacitor bank, the inductance of one phase of the circuit and the resistance to ground of the generator.

6 2008 China International Conference on Electricity Distribution (CICED 2008)) 2. The voltage difference across the capacitor prior to breakdown minus the voltage of the arrestor. The energy dissipated in the arrestor is higher than under IV-A due to the lower COV of the arrestor. Yet here the arrestor will function regardless the phase in which the maximum overvoltage will occur. This limits the number of surge arrestors to install to one. Table IV : Choice of continuous operating voltage of the arrestor and the resulting overvoltage protection level depends on network operation conditions and arrestor location. networks with highohmic insulated neutral system and automatic earth fault clearing networks with earth fault compensation or with a high-ohmic insulated neutral system Arrestor location CB terminals Neutral point CB terminals Neutral point Continuous Operating Voltage Overvoltage protection level [pu] or Un (2/3) Un/ 3 2.2 0.5*Un/ 3 2.1 1.5*Un/ 3 3.3 1*Un/ 3 3.2 4.3 Choice of the surge arrestor The surge arrestor limits effectively the overvoltage by suppressing the high frequency (150 khz) peak overvoltage. The absolute value of the remaining overvoltage depends though on the choice of the surge arrestor. The voltage limitation is effective at a level of 3.1 times the rated continuous operating voltage of the surge arrestor. The choice of the rated voltage of the surge arrestor must take into account abnormal circuit conditions as well. In table IV two common situations are compared. For networks with high-ohmic insulated neutral system and automatic earth fault clearing the nominal voltage of each phase is fixed at Un/ 3 and the neutral point of the capacitor bank has 0 (zero) voltage. The continuous operating voltage of the surge arrestor can be chosen accordingly. The surge arrestor with associated continuous operating voltage (COV) gives a protection of 2.2 pu. During a normal breaking operation the neutral point attains a peak voltage of 0.5*Un (2/3), which lasts until discharging of the capacitor bank; this corresponds to a COV of 0.5*Un/ 3; the resulting level of protection is 2.1 pu. For networks with earth fault compensation or with a high-ohmic insulated neutral system a possible persistent single phase earth failure increases the nominal voltage of the healthy phases a factor 3, and the voltage on the neutral point of the capacitor bank increases to 1 pu. These more severe conditions determine the continuous operating voltage of the surge arrestor. For arrestors on the circuit-breaker terminals the nominal voltage can reach 1.5*Un/ 3; the resulting level of protection is 3.3 pu. For a single arrestor on the neutral of the bank the continuous voltage can reach Un/ 3; the resulting level of protection is 3.2 pu. During interruption of the capacitive current the voltage of the neutral can increase slightly more. Yet, the surge arrestor is capable of dealing with this temporary overvoltage under this rare abnormal network condition. 5. DISCUSSION The main results of this study are summarized in table V. An important difference is found between the numerically and experimentally obtained overvoltage values. The measured overvoltage on the bank terminal to ground is significantly lower than calculated. This is due to natural damping of the high frequency phenomena by dissipative elements in the circuit and by the very small capacitance on the source side due to the absence of parallel feeders. The peak over-voltage has a limited duration of about 10µs. Surge arrestors effectively limit these overvoltages to values as low as 2.2 pu between terminal and ground. The capacitors themselves are stressed neither by the NSDD nor by the action of the surge arrestors during limitation, as the discharge current is a single phase current flowing towards ground. TABLE V : Over-voltages in capacitor bank switching Situation Capacitor Across CB bank terminal 1 Normal Interruption 1.5 pu 2.5 pu 2 NSDD : Predicted 6.0 pu 7.0 pu 3a NSDD (K-Late = 1.3) 4.2 pu 5.2 pu 3b NSDD (K-Immediate = 1.7) 5.2 pu 6.2 pu 4 Surge arrestors on all terminals 2.2 pu 3.2 pu 5 Surge arrestor on C-bank neutral 2.2 pu 3.2 pu In the introduction it was outlined that NSDDs are a common phenomenon in vacuum interrupters and that the simultaneous occurrence of NSDDs in 2 phases give rise to a restrike. The frequency of occurrence of a NSDD is related to design parameters like the contact opening stroke. Hence it is possible to design a vacuum CB according to the requirements of either low restrike probability class C1 or very low restrike probability class C2 of [7]. For 24 kv Class C2 vacuum CBs with very low restriking probability this leads to a nominal contact gap of 16 mm, see Fig. 1. For voltages of 36 kv and above [8] proposes to use two vacuum

2008 China International Conference on Electricity Distribution (CICED 2008) 7 interrupters in series. Although these measures are effective from a normative point of view, they do not contribute to an economically conclusive and reliable solution as shown by the following numerical example. For instance, contactors which allow for frequent operations have a small contact opening stroke. Even with a NSDD frequency of only 1/500 they will produce over 2000 NSDDs in their entire lifespan. Therefore, only the application of surge arrestors is an effective solution to suppress overvoltages and eliminate any risk for equipment: capacitor bank, circuit breaker and switch board. The application guide in table VI summarises this recommendation relating the choice of switchgear to the application duty. If the CB is used only occasionally for energizing and de-energizing the capacitor bank a vacuum CB with class C1 or C2 can be used. Yet for daily operation of the capacitor bank a protection by surge arrestor is recommended, and in this case a class C1 rating is sufficient, as the suppression of overvoltage during a NSDD reduces significantly the probability of a second simultaneous NSDD, and hence the risk of a restrike. For more than daily operation a vacuum contactor with surge arrestor is an economical viable solution in series with a vacuum CB for protection. Table VI : Vacuum-C B Vacuum-C ontactors Application guide Capacitive switching duty Protection and Daily operation Occasional operation Class C1 + Class C1 or C2 Surge arrestors Surge arrestors Frequent operation Surge arrestors When applying surge arrestors, special attention must be given to the energy dissipation in the arrestor. It is proposed to dimension the arrestor to be capable to carry out 3 consecutive protective actions without cooling down. Furthermore the dimensioning is related to the reactive power of the capacitor bank, Sk. Guidelines are given by [6, 9] in the case of restriking CBs, in which case the arrestor has to be dimensioned for an energy of 6*Sk/ω, where ω : angular frequency of the network. Transposing this approach to a protection against NSDD the guidelines as presented in table VII dimension the energy dissipation capability of the arrestor. Hence, for the protection against NSDDs the arrestor can be designed 3 to 6 times smaller. Table VII : the requested energy dissipation capability of the arrestor Protection against NSDD Arrestor on CB terminals to ground 1 * Sk/ω Arrestor on C-bank neutral to ground 2 * Sk/ω I. CONCLUSION This study focussed on the interaction of the vacuum circuit breaker with a capacitor bank during switching operation. The occurrence of a NSDD leads to a shift of the voltage of the neutral point of the bank. Although the phenomenon in itself is rare, the over-voltages produced are deterministic and depend on the recovery voltage of the phase in which the NSDD occurs and on the moment of breakdown. The experimental study shows that the overvoltage after NSDD is limited to about 4.2 pu. on the capacitor bank terminals. Surge arrestors are shown to be an effective means to limit this overvoltage. As cost efficient solution it is proposed to use a single surge arrestor on the neutral point of the capacitor bank. Guidelines are presented to dimension these arrestors. REFERENCES [1] T. Yokoyama, Y. Matsui, K. Ikemoto and M. Inoyama Technique on Overvoltage Phenomenon Analysis for Vacuum Switching Equipment by, Meiden Review Series No. 78,1986 [2] Y. Sunada,N.Ito, S. Yanabu, H. Awaji, H. Okumura and Y. Kanai, Research and Development on 13.8kV 100kA Vacuum CB with Huge capacity and Frequent Operation, CIGRE, Paris, 1982 [3] P. Huhse and E. Zielke, 3AF Vacuum CBs for Switching in Capacitor Banks, Siemens Power ENGENEERING III (1981) No 8-9 [4] D. Koch, Control equipment for MV capacitor banks, ECT142, Schneider-Electric, Grenoble, 1992 [5] T. Kamakawaji, T. Shioiri, T. Funahashi, Y. Satoh, E. Kaneko and I. Oshima, An Investigation into Major Factors in Shunt Capacitor switching Performances By Vacuum CBs With Copper Chromium Contacts, IEEE Power Engeneering 1993 winter meeting Columbus OHIO [6] L. Gebhardt, B. Richter, Surge arrestor application of MV-capacitor banks to mitigate problems of switching restrikes, paper 0639, 19 th CIRED, 2007, Vienna. [7] International Standard IEC 62271-1, 2008, High Voltage

8 2008 China International Conference on Electricity Distribution (CICED 2008)) Switchgear and Controlgear Part 1: Common specifications [8] E. Dullni, W. Shang, D. Gentsch,I. Kleberg and K. Niayesh, Switching of Capacitive Currents and the Correlation of Restrike and Pre-ignition Behavior, IEEE trans. on dielectrics and electrical insulation, vol. 13, n 1, pp. 65-71, 2006 [9] R. Rudolph and B. Richter, Dimensioning, testing and application of metal oxide surge arrestors in medium voltage networks, open document ABB, Wettingen, 1999 About the author Hans Schellekens (54) received the Ph.D. degree in technical engineering from the Technical University of Eindhoven, The Netherlands, in 1983, with a specialization in plasma physics. He worked at the HOLEC Research Laboratory from 1978 to 1982 and at KEMA testing laboratories from 1983 to 1985. From 1986 to 1993, he was responsible for the development of vacuum interrupters and vacuum circuit breakers at HOLEC. Since 1994, he is involved in the development of vacuum interrupters for Schneider Electric Medium Voltage SBU (formerly Merlin-Gerin) at Grenoble in France. He has been active in the Dutch Brazing Soc. as well as in the CIGRE Working Group 13.01 from 1985 to 1993. Dr. Schellekens is a member of the Current Zero Club. E-mail of author: hans.schellekens@schneider-electric.com